1 /*! 2 \file gd32e50x_gpio.h 3 \brief definitions for the GPIO 4 5 \version 2020-03-10, V1.0.0, firmware for GD32E50x 6 \version 2020-08-26, V1.1.0, firmware for GD32E50x 7 \version 2021-03-23, V1.2.0, firmware for GD32E50x 8 */ 9 10 /* 11 Copyright (c) 2021, GigaDevice Semiconductor Inc. 12 13 Redistribution and use in source and binary forms, with or without modification, 14 are permitted provided that the following conditions are met: 15 16 1. Redistributions of source code must retain the above copyright notice, this 17 list of conditions and the following disclaimer. 18 2. Redistributions in binary form must reproduce the above copyright notice, 19 this list of conditions and the following disclaimer in the documentation 20 and/or other materials provided with the distribution. 21 3. Neither the name of the copyright holder nor the names of its contributors 22 may be used to endorse or promote products derived from this software without 23 specific prior written permission. 24 25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 34 OF SUCH DAMAGE. 35 */ 36 37 #ifndef GD32E50X_GPIO_H 38 #define GD32E50X_GPIO_H 39 40 #include "gd32e50x.h" 41 42 /* GPIOx(x=A,B,C,D,E,F,G) definitions */ 43 #define GPIOA (GPIO_BASE + 0x00000000U) /*!< GPIOA bsae address */ 44 #define GPIOB (GPIO_BASE + 0x00000400U) /*!< GPIOB bsae address */ 45 #define GPIOC (GPIO_BASE + 0x00000800U) /*!< GPIOC bsae address */ 46 #define GPIOD (GPIO_BASE + 0x00000C00U) /*!< GPIOD bsae address */ 47 #define GPIOE (GPIO_BASE + 0x00001000U) /*!< GPIOE bsae address */ 48 #define GPIOF (GPIO_BASE + 0x00001400U) /*!< GPIOF bsae address */ 49 #define GPIOG (GPIO_BASE + 0x00001800U) /*!< GPIOG bsae address */ 50 51 /* AFIO definitions */ 52 #define AFIO AFIO_BASE /*!< AFIO bsae address */ 53 54 /* registers definitions */ 55 /* GPIO registers definitions */ 56 #define GPIO_CTL0(gpiox) REG32((gpiox) + 0x00000000U) /*!< GPIO port control register 0 */ 57 #define GPIO_CTL1(gpiox) REG32((gpiox) + 0x00000004U) /*!< GPIO port control register 1 */ 58 #define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x00000008U) /*!< GPIO port input status register */ 59 #define GPIO_OCTL(gpiox) REG32((gpiox) + 0x0000000CU) /*!< GPIO port output control register */ 60 #define GPIO_BOP(gpiox) REG32((gpiox) + 0x00000010U) /*!< GPIO port bit operation register */ 61 #define GPIO_BC(gpiox) REG32((gpiox) + 0x00000014U) /*!< GPIO bit clear register */ 62 #define GPIO_LOCK(gpiox) REG32((gpiox) + 0x00000018U) /*!< GPIO port configuration lock register */ 63 #define GPIOx_SPD(gpiox) REG32((gpiox) + 0x0000003CU) /*!< GPIO port bit speed register */ 64 65 /* AFIO registers definitions */ 66 #define AFIO_EC REG32(AFIO + 0x00000000U) /*!< AFIO event control register */ 67 #define AFIO_PCF0 REG32(AFIO + 0x00000004U) /*!< AFIO port configuration register 0 */ 68 #define AFIO_EXTISS0 REG32(AFIO + 0x00000008U) /*!< AFIO port EXTI sources selection register 0 */ 69 #define AFIO_EXTISS1 REG32(AFIO + 0x0000000CU) /*!< AFIO port EXTI sources selection register 1 */ 70 #define AFIO_EXTISS2 REG32(AFIO + 0x00000010U) /*!< AFIO port EXTI sources selection register 2 */ 71 #define AFIO_EXTISS3 REG32(AFIO + 0x00000014U) /*!< AFIO port EXTI sources selection register 3 */ 72 #define AFIO_PCF1 REG32(AFIO + 0x0000001CU) /*!< AFIO port configuration register 1 */ 73 #define AFIO_CPSCTL REG32(AFIO + 0x00000020U) /*!< IO compensation control register */ 74 #define AFIO_PCFA REG32(AFIO + 0x0000003CU) /*!< AFIO port configuration register A */ 75 #define AFIO_PCFB REG32(AFIO + 0x00000040U) /*!< AFIO port configuration register B */ 76 #define AFIO_PCFC REG32(AFIO + 0x00000044U) /*!< AFIO port configuration register C */ 77 #define AFIO_PCFD REG32(AFIO + 0x00000048U) /*!< AFIO port configuration register D */ 78 #define AFIO_PCFE REG32(AFIO + 0x0000004CU) /*!< AFIO port configuration register E */ 79 #define AFIO_PCFG REG32(AFIO + 0x00000054U) /*!< AFIO port configuration register G */ 80 81 /* bits definitions */ 82 /* GPIO_CTL0 */ 83 #define GPIO_CTL0_MD0 BITS(0,1) /*!< port 0 mode bits */ 84 #define GPIO_CTL0_CTL0 BITS(2,3) /*!< pin 0 configuration bits */ 85 #define GPIO_CTL0_MD1 BITS(4,5) /*!< port 1 mode bits */ 86 #define GPIO_CTL0_CTL1 BITS(6,7) /*!< pin 1 configuration bits */ 87 #define GPIO_CTL0_MD2 BITS(8,9) /*!< port 2 mode bits */ 88 #define GPIO_CTL0_CTL2 BITS(10,11) /*!< pin 2 configuration bits */ 89 #define GPIO_CTL0_MD3 BITS(12,13) /*!< port 3 mode bits */ 90 #define GPIO_CTL0_CTL3 BITS(14,15) /*!< pin 3 configuration bits */ 91 #define GPIO_CTL0_MD4 BITS(16,17) /*!< port 4 mode bits */ 92 #define GPIO_CTL0_CTL4 BITS(18,19) /*!< pin 4 configuration bits */ 93 #define GPIO_CTL0_MD5 BITS(20,21) /*!< port 5 mode bits */ 94 #define GPIO_CTL0_CTL5 BITS(22,23) /*!< pin 5 configuration bits */ 95 #define GPIO_CTL0_MD6 BITS(24,25) /*!< port 6 mode bits */ 96 #define GPIO_CTL0_CTL6 BITS(26,27) /*!< pin 6 configuration bits */ 97 #define GPIO_CTL0_MD7 BITS(28,29) /*!< port 7 mode bits */ 98 #define GPIO_CTL0_CTL7 BITS(30,31) /*!< pin 7 configuration bits */ 99 100 /* GPIO_CTL1 */ 101 #define GPIO_CTL1_MD8 BITS(0,1) /*!< port 8 mode bits */ 102 #define GPIO_CTL1_CTL8 BITS(2,3) /*!< pin 8 configuration bits */ 103 #define GPIO_CTL1_MD9 BITS(4,5) /*!< port 9 mode bits */ 104 #define GPIO_CTL1_CTL9 BITS(6,7) /*!< pin 9 configuration bits */ 105 #define GPIO_CTL1_MD10 BITS(8,9) /*!< port 10 mode bits */ 106 #define GPIO_CTL1_CTL10 BITS(10,11) /*!< pin 10 configuration bits */ 107 #define GPIO_CTL1_MD11 BITS(12,13) /*!< port 11 mode bits */ 108 #define GPIO_CTL1_CTL11 BITS(14,15) /*!< pin 11 configuration bits */ 109 #define GPIO_CTL1_MD12 BITS(16,17) /*!< port 12 mode bits */ 110 #define GPIO_CTL1_CTL12 BITS(18,19) /*!< pin 12 configuration bits */ 111 #define GPIO_CTL1_MD13 BITS(20,21) /*!< port 13 mode bits */ 112 #define GPIO_CTL1_CTL13 BITS(22,23) /*!< pin 13 configuration bits */ 113 #define GPIO_CTL1_MD14 BITS(24,25) /*!< port 14 mode bits */ 114 #define GPIO_CTL1_CTL14 BITS(26,27) /*!< pin 14 configuration bits */ 115 #define GPIO_CTL1_MD15 BITS(28,29) /*!< port 15 mode bits */ 116 #define GPIO_CTL1_CTL15 BITS(30,31) /*!< pin 15 configuration bits */ 117 118 /* GPIO_ISTAT */ 119 #define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */ 120 #define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */ 121 #define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */ 122 #define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */ 123 #define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */ 124 #define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */ 125 #define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */ 126 #define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */ 127 #define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */ 128 #define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */ 129 #define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */ 130 #define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */ 131 #define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */ 132 #define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */ 133 #define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */ 134 #define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */ 135 136 /* GPIO_OCTL */ 137 #define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */ 138 #define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */ 139 #define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */ 140 #define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */ 141 #define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */ 142 #define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */ 143 #define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */ 144 #define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */ 145 #define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */ 146 #define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */ 147 #define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */ 148 #define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */ 149 #define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */ 150 #define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */ 151 #define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */ 152 #define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */ 153 154 /* GPIO_BOP */ 155 #define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */ 156 #define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */ 157 #define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */ 158 #define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */ 159 #define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */ 160 #define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */ 161 #define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */ 162 #define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */ 163 #define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */ 164 #define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */ 165 #define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */ 166 #define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */ 167 #define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */ 168 #define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */ 169 #define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */ 170 #define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */ 171 #define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */ 172 #define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */ 173 #define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */ 174 #define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */ 175 #define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */ 176 #define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */ 177 #define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */ 178 #define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */ 179 #define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */ 180 #define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */ 181 #define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */ 182 #define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */ 183 #define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */ 184 #define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */ 185 #define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */ 186 #define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */ 187 188 /* GPIO_BC */ 189 #define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */ 190 #define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */ 191 #define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */ 192 #define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */ 193 #define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */ 194 #define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */ 195 #define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */ 196 #define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */ 197 #define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */ 198 #define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */ 199 #define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */ 200 #define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */ 201 #define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */ 202 #define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */ 203 #define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */ 204 #define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */ 205 206 /* GPIO_LOCK */ 207 #define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */ 208 #define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */ 209 #define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */ 210 #define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */ 211 #define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */ 212 #define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */ 213 #define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */ 214 #define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */ 215 #define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */ 216 #define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */ 217 #define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */ 218 #define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */ 219 #define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */ 220 #define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */ 221 #define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */ 222 #define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */ 223 #define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */ 224 225 /* GPIO_SPD */ 226 #define GPIO_SPD_SPD0 BIT(0) /*!< pin 0 set very high output speed when MDx is 0b11 */ 227 #define GPIO_SPD_SPD1 BIT(1) /*!< pin 1 set very high output speed when MDx is 0b11 */ 228 #define GPIO_SPD_SPD2 BIT(2) /*!< pin 2 set very high output speed when MDx is 0b11 */ 229 #define GPIO_SPD_SPD3 BIT(3) /*!< pin 3 set very high output speed when MDx is 0b11 */ 230 #define GPIO_SPD_SPD4 BIT(4) /*!< pin 4 set very high output speed when MDx is 0b11 */ 231 #define GPIO_SPD_SPD5 BIT(5) /*!< pin 5 set very high output speed when MDx is 0b11 */ 232 #define GPIO_SPD_SPD6 BIT(6) /*!< pin 6 set very high output speed when MDx is 0b11 */ 233 #define GPIO_SPD_SPD7 BIT(7) /*!< pin 7 set very high output speed when MDx is 0b11 */ 234 #define GPIO_SPD_SPD8 BIT(8) /*!< pin 8 set very high output speed when MDx is 0b11 */ 235 #define GPIO_SPD_SPD9 BIT(9) /*!< pin 9 set very high output speed when MDx is 0b11 */ 236 #define GPIO_SPD_SPD10 BIT(10) /*!< pin 10 set very high output speed when MDx is 0b11 */ 237 #define GPIO_SPD_SPD11 BIT(11) /*!< pin 11 set very high output speed when MDx is 0b11 */ 238 #define GPIO_SPD_SPD12 BIT(12) /*!< pin 12 set very high output speed when MDx is 0b11 */ 239 #define GPIO_SPD_SPD13 BIT(13) /*!< pin 13 set very high output speed when MDx is 0b11 */ 240 #define GPIO_SPD_SPD14 BIT(14) /*!< pin 14 set very high output speed when MDx is 0b11 */ 241 #define GPIO_SPD_SPD15 BIT(15) /*!< pin 15 set very high output speed when MDx is 0b11 */ 242 243 /* AFIO_EC */ 244 #define AFIO_EC_PIN BITS(0,3) /*!< event output pin selection */ 245 #define AFIO_EC_PORT BITS(4,6) /*!< event output port selection */ 246 #define AFIO_EC_EOE BIT(7) /*!< event output enable */ 247 248 /* AFIO_PCF0 */ 249 #if defined GD32E50X_CL 250 /* memory map and bit definitions for GD32E50X_CL devices */ 251 #define AFIO_PCF0_SPI0_REMAP BIT(0) /*!< SPI0 remapping */ 252 #define AFIO_PCF0_I2C0_REMAP BIT(1) /*!< I2C0 remapping */ 253 #define AFIO_PCF0_USART0_REMAP BIT(2) /*!< USART0 remapping */ 254 #define AFIO_PCF0_USART1_REMAP BIT(3) /*!< USART1 remapping */ 255 #define AFIO_PCF0_USART2_REMAP BITS(4,5) /*!< USART2 remapping */ 256 #define AFIO_PCF0_TIMER0_REMAP BITS(6,7) /*!< TIMER0 remapping */ 257 #define AFIO_PCF0_TIMER1_REMAP BITS(8,9) /*!< TIMER1 remapping */ 258 #define AFIO_PCF0_TIMER2_REMAP BITS(10,11) /*!< TIMER2 remapping */ 259 #define AFIO_PCF0_TIMER3_REMAP BIT(12) /*!< TIMER3 remapping */ 260 #define AFIO_PCF0_CAN0_REMAP BITS(13,14) /*!< CAN0 remapping */ 261 #define AFIO_PCF0_PD01_REMAP BIT(15) /*!< port D0/port D1 mapping on OSC_IN/OSC_OUT */ 262 #define AFIO_PCF0_TIMER4CH3_IREMAP BIT(16) /*!< TIMER4 channel3 internal remapping */ 263 #define AFIO_PCF0_ENET_REMAP BIT(21) /*!< ethernet MAC I/O remapping */ 264 #define AFIO_PCF0_CAN1_REMAP BIT(22) /*!< CAN1 remapping */ 265 #define AFIO_PCF0_ENET_PHY_SEL BIT(23) /*!< ethernet MII or RMII PHY selection */ 266 #define AFIO_PCF0_SWJ_CFG BITS(24,26) /*!< serial wire JTAG configuration */ 267 #define AFIO_PCF0_SPI2_REMAP BIT(28) /*!< SPI2/I2S2 remapping */ 268 #define AFIO_PCF0_TIMER1ITR0_REMAP BIT(29) /*!< TIMER1 internal trigger 0 remapping */ 269 #define AFIO_PCF0_PTP_PPS_REMAP BIT(30) /*!< ethernet PTP PPS remapping */ 270 #elif defined GD32EPRT 271 /* memory map and bit definitions for GD32EPRT devices */ 272 #define AFIO_PCF0_SPI0_REMAP BIT(0) /*!< SPI0 remapping */ 273 #define AFIO_PCF0_I2C0_REMAP BIT(1) /*!< I2C0 remapping */ 274 #define AFIO_PCF0_USART0_REMAP BIT(2) /*!< USART0 remapping */ 275 #define AFIO_PCF0_USART1_REMAP BIT(3) /*!< USART1 remapping */ 276 #define AFIO_PCF0_USART2_REMAP BITS(4,5) /*!< USART2 remapping */ 277 #define AFIO_PCF0_TIMER0_REMAP BITS(6,7) /*!< TIMER0 remapping */ 278 #define AFIO_PCF0_TIMER1_REMAP BITS(8,9) /*!< TIMER1 remapping */ 279 #define AFIO_PCF0_TIMER2_REMAP BITS(10,11) /*!< TIMER2 remapping */ 280 #define AFIO_PCF0_TIMER3_REMAP BIT(12) /*!< TIMER3 remapping */ 281 #define AFIO_PCF0_PD01_REMAP BIT(15) /*!< port D0/port D1 mapping on OSC_IN/OSC_OUT */ 282 #define AFIO_PCF0_TIMER4CH3_IREMAP BIT(16) /*!< TIMER4 channel3 internal remapping */ 283 #define AFIO_PCF0_ENET_REMAP BIT(21) /*!< ethernet MAC I/O remapping */ 284 #define AFIO_PCF0_ENET_PHY_SEL BIT(23) /*!< ethernet MII or RMII PHY selection */ 285 #define AFIO_PCF0_SWJ_CFG BITS(24,26) /*!< serial wire JTAG configuration */ 286 #define AFIO_PCF0_SPI2_REMAP BIT(28) /*!< SPI2/I2S2 remapping */ 287 #define AFIO_PCF0_TIMER1ITR0_REMAP BIT(29) /*!< TIMER1 internal trigger 0 remapping */ 288 #define AFIO_PCF0_PTP_PPS_REMAP BIT(30) /*!< ethernet PTP PPS remapping */ 289 #else 290 /* memory map and bit definitions for GD32E50X_HD devices and GD32E50X_XD devices */ 291 #define AFIO_PCF0_SPI0_REMAP BIT(0) /*!< SPI0 remapping */ 292 #define AFIO_PCF0_I2C0_REMAP BIT(1) /*!< I2C0 remapping */ 293 #define AFIO_PCF0_USART0_REMAP BIT(2) /*!< USART0 remapping */ 294 #define AFIO_PCF0_USART1_REMAP BIT(3) /*!< USART1 remapping */ 295 #define AFIO_PCF0_USART2_REMAP BITS(4,5) /*!< USART2 remapping */ 296 #define AFIO_PCF0_TIMER0_REMAP BITS(6,7) /*!< TIMER0 remapping */ 297 #define AFIO_PCF0_TIMER1_REMAP BITS(8,9) /*!< TIMER1 remapping */ 298 #define AFIO_PCF0_TIMER2_REMAP BITS(10,11) /*!< TIMER2 remapping */ 299 #define AFIO_PCF0_TIMER3_REMAP BIT(12) /*!< TIMER3 remapping */ 300 #define AFIO_PCF0_CAN0_REMAP BITS(13,14) /*!< CAN0 remapping */ 301 #define AFIO_PCF0_PD01_REMAP BIT(15) /*!< port D0/port D1 mapping on OSC_IN/OSC_OUT */ 302 #define AFIO_PCF0_TIMER4CH3_IREMAP BIT(16) /*!< TIMER4 channel3 internal remapping */ 303 #define AFIO_PCF0_ADC0_ETRGINS_REMAP BIT(17) /*!< ADC 0 external trigger inserted conversion remapping */ 304 #define AFIO_PCF0_ADC0_ETRGREG_REMAP BIT(18) /*!< ADC 0 external trigger regular conversion remapping */ 305 #define AFIO_PCF0_ADC1_ETRGINS_REMAP BIT(19) /*!< ADC 1 external trigger inserted conversion remapping */ 306 #define AFIO_PCF0_ADC1_ETRGREG_REMAP BIT(20) /*!< ADC 1 external trigger regular conversion remapping */ 307 #define AFIO_PCF0_CAN1_REMAP BIT(22) /*!< CAN1 remapping */ 308 #define AFIO_PCF0_SWJ_CFG BITS(24,26) /*!< serial wire JTAG configuration */ 309 #define AFIO_PCF0_SPI2_REMAP BIT(28) /*!< SPI2/I2S2 remapping */ 310 #endif /* GD32E50X_CL */ 311 312 /* AFIO_EXTISS0 */ 313 #define AFIO_EXTI0_SS BITS(0,3) /*!< EXTI 0 sources selection */ 314 #define AFIO_EXTI1_SS BITS(4,7) /*!< EXTI 1 sources selection */ 315 #define AFIO_EXTI2_SS BITS(8,11) /*!< EXTI 2 sources selection */ 316 #define AFIO_EXTI3_SS BITS(12,15) /*!< EXTI 3 sources selection */ 317 318 /* AFIO_EXTISS1 */ 319 #define AFIO_EXTI4_SS BITS(0,3) /*!< EXTI 4 sources selection */ 320 #define AFIO_EXTI5_SS BITS(4,7) /*!< EXTI 5 sources selection */ 321 #define AFIO_EXTI6_SS BITS(8,11) /*!< EXTI 6 sources selection */ 322 #define AFIO_EXTI7_SS BITS(12,15) /*!< EXTI 7 sources selection */ 323 324 /* AFIO_EXTISS2 */ 325 #define AFIO_EXTI8_SS BITS(0,3) /*!< EXTI 8 sources selection */ 326 #define AFIO_EXTI9_SS BITS(4,7) /*!< EXTI 9 sources selection */ 327 #define AFIO_EXTI10_SS BITS(8,11) /*!< EXTI 10 sources selection */ 328 #define AFIO_EXTI11_SS BITS(12,15) /*!< EXTI 11 sources selection */ 329 330 /* AFIO_EXTISS3 */ 331 #define AFIO_EXTI12_SS BITS(0,3) /*!< EXTI 12 sources selection */ 332 #define AFIO_EXTI13_SS BITS(4,7) /*!< EXTI 13 sources selection */ 333 #define AFIO_EXTI14_SS BITS(8,11) /*!< EXTI 14 sources selection */ 334 #define AFIO_EXTI15_SS BITS(12,15) /*!< EXTI 15 sources selection */ 335 336 /* AFIO_PCF1 */ 337 #define AFIO_PCF1_TIMER8_REMAP BIT(5) /*!< TIMER8 remapping */ 338 #define AFIO_PCF1_TIMER9_REMAP BIT(6) /*!< TIMER9 remapping */ 339 #define AFIO_PCF1_TIMER10_REMAP BIT(7) /*!< TIMER10 remapping */ 340 #define AFIO_PCF1_TIMER12_REMAP BIT(8) /*!< TIMER12 remapping */ 341 #define AFIO_PCF1_TIMER13_REMAP BIT(9) /*!< TIMER13 remapping */ 342 #define AFIO_PCF1_EXMC_NADV BIT(10) /*!< EXMC_NADV connect/disconnect */ 343 #define AFIO_PCF1_CTC_REMAP BITS(11,12) /*!< CTC remapping */ 344 345 /* AFIO_CPSCTL */ 346 #define AFIO_CPSCTL_CPS_EN BIT(0) /*!< I/O compensation cell enable */ 347 #define AFIO_CPSCTL_CPS_RDY BIT(8) /*!< I/O compensation cell is ready or not */ 348 349 /* AFIO_PCFA */ 350 #define AFIO_PCFA_PA2_AFCFG BIT(4) /*!< PA2 AF function configuration bit */ 351 #define AFIO_PCFA_PA3_AFCFG BIT(6) /*!< PA3 AF function configuration bit */ 352 #define AFIO_PCFA_PA5_AFCFG BIT(10) /*!< PA5 AF function configuration bit */ 353 #define AFIO_PCFA_PA8_AFCFG BITS(16, 17) /*!< PA8 AF function configuration bits */ 354 #define AFIO_PCFA_PA9_AFCFG BITS(18, 19) /*!< PA9 AF function configuration bits */ 355 #define AFIO_PCFA_PA10_AFCFG BITS(20, 21) /*!< PA10 AF function configuration bits */ 356 #define AFIO_PCFA_PA11_AFCFG BITS(22, 23) /*!< PA11 AF function configuration bits */ 357 #define AFIO_PCFA_PA12_AFCFG BITS(24, 25) /*!< PA12 AF function configuration bits */ 358 #define AFIO_PCFA_PA15_AFCFG BIT(30) /*!< PA15 AF function configuration bit */ 359 360 /* AFIO_PCFB */ 361 #define AFIO_PCFB_PB0_AFCFG BIT(0) /*!< PB0 AF function configuration bit */ 362 #define AFIO_PCFB_PB1_AFCFG BITS(2, 3) /*!< PB1 AF function configuration bits */ 363 #define AFIO_PCFB_PB2_AFCFG BITS(4, 5) /*!< PB2 AF function configuration bits */ 364 #define AFIO_PCFB_PB3_AFCFG BIT(6) /*!< PB3 AF function configuration bit */ 365 #define AFIO_PCFB_PB4_AFCFG BITS(8, 9) /*!< PB4 AF function configuration bits */ 366 #define AFIO_PCFB_PB5_AFCFG BITS(10, 11) /*!< PB5 AF function configuration bits */ 367 #define AFIO_PCFB_PB6_AFCFG BIT(12) /*!< PB6 AF function configuration bit */ 368 #define AFIO_PCFB_PB7_AFCFG BIT(14) /*!< PB7 AF function configuration bit */ 369 #define AFIO_PCFB_PB8_AFCFG BITS(16, 17) /*!< PB8 AF function configuration bits */ 370 #define AFIO_PCFB_PB9_AFCFG BITS(18, 19) /*!< PB9 AF function configuration bits */ 371 #define AFIO_PCFB_PB10_AFCFG BITS(20, 21) /*!< PB10 AF function configuration bits */ 372 #define AFIO_PCFB_PB11_AFCFG BITS(22, 23) /*!< PB11 AF function configuration bits */ 373 #define AFIO_PCFB_PB12_AFCFG BITS(24, 25) /*!< PB12 AF function configuration bits */ 374 #define AFIO_PCFB_PB13_AFCFG BITS(26, 27) /*!< PB13 AF function configuration bits */ 375 #define AFIO_PCFB_PB14_AFCFG BITS(28, 29) /*!< PB14 AF function configuration bits */ 376 #define AFIO_PCFB_PB15_AFCFG BIT(30) /*!< PB15 AF function configuration bits */ 377 378 /* AFIO_PCFC */ 379 #define AFIO_PCFC_PC0_AFCFG BIT(0) /*!< PC0 AF function configuration bit */ 380 #define AFIO_PCFC_PC2_AFCFG BITS(4, 5) /*!< PC2 AF function configuration bits */ 381 #define AFIO_PCFC_PC3_AFCFG BIT(6) /*!< PC3 AF function configuration bit */ 382 #define AFIO_PCFC_PC6_AFCFG BITS(12, 13) /*!< PC6 AF function configuration bits */ 383 #define AFIO_PCFC_PC7_AFCFG BITS(14, 15) /*!< PC7 AF function configuration bits */ 384 #define AFIO_PCFC_PC8_AFCFG BITS(16, 17) /*!< PC8 AF function configuration bits */ 385 #define AFIO_PCFC_PC9_AFCFG BITS(18, 19) /*!< PC9 AF function configuration bits */ 386 #define AFIO_PCFC_PC10_AFCFG BIT(20) /*!< PC10 AF function configuration bit */ 387 #define AFIO_PCFC_PC11_AFCFG BITS(22, 23) /*!< PC11 AF function configuration bits */ 388 #define AFIO_PCFC_PC12_AFCFG BIT(24) /*!< PC12 AF function configuration bit */ 389 390 /* AFIO_PCFD */ 391 #define AFIO_PCFD_PD4_AFCFG BIT(8) /*!< PD4 AF function configuration bit */ 392 #define AFIO_PCFD_PD5_AFCFG BIT(10) /*!< PD5 AF function configuration bit */ 393 394 /* AFIO_PCFE */ 395 #define AFIO_PCFE_PE0_AFCFG BITS(0, 1) /*!< PE0 AF function configuration bits */ 396 #define AFIO_PCFE_PE1_AFCFG BITS(2, 3) /*!< PE1 AF function configuration bits */ 397 #define AFIO_PCFE_PE8_AFCFG BIT(16) /*!< PE8 AF function configuration bit */ 398 #define AFIO_PCFE_PE9_AFCFG BIT(18) /*!< PE9 AF function configuration bit */ 399 #define AFIO_PCFE_PE10_AFCFG BIT(20) /*!< PE10 AF function configuration bit */ 400 #define AFIO_PCFE_PE11_AFCFG BIT(22) /*!< PE11 AF function configuration bit */ 401 #define AFIO_PCFE_PE12_AFCFG BIT(24) /*!< PE12 AF function configuration bit */ 402 #define AFIO_PCFE_PE13_AFCFG BIT(26) /*!< PE13 AF function configuration bit */ 403 404 /* AFIO_PCFG */ 405 #define AFIO_PCFG_PG6_AFCFG BIT(12) /*!< PG6 AF function configuration bit */ 406 #define AFIO_PCFG_PG7_AFCFG BITS(14, 15) /*!< PG7 AF function configuration bits */ 407 #define AFIO_PCFG_PG9_AFCFG BIT(18) /*!< PG9 AF function configuration bit */ 408 #define AFIO_PCFG_PG10_AFCFG BIT(20) /*!< PG10 AF function configuration bit */ 409 #define AFIO_PCFG_PG11_AFCFG BIT(22) /*!< PG11 AF function configuration bit */ 410 #define AFIO_PCFG_PG12_AFCFG BIT(24) /*!< PG12 AF function configuration bit */ 411 #define AFIO_PCFG_PG13_AFCFG BIT(26) /*!< PG13 AF function configuration bit */ 412 #define AFIO_PCFG_PG14_AFCFG BIT(28) /*!< PG14 AF function configuration bit */ 413 414 /* constants definitions */ 415 typedef FlagStatus bit_status; 416 417 /* GPIO mode values set */ 418 #define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (4U * (n)))) 419 #define GPIO_MODE_MASK(n) (0xFU << (4U * (n))) 420 421 /* GPIO mode definitions */ 422 #define GPIO_MODE_AIN ((uint8_t)0x00U) /*!< analog input mode */ 423 #define GPIO_MODE_IN_FLOATING ((uint8_t)0x04U) /*!< floating input mode */ 424 #define GPIO_MODE_IPD ((uint8_t)0x28U) /*!< pull-down input mode */ 425 #define GPIO_MODE_IPU ((uint8_t)0x48U) /*!< pull-up input mode */ 426 #define GPIO_MODE_OUT_OD ((uint8_t)0x14U) /*!< GPIO output with open-drain */ 427 #define GPIO_MODE_OUT_PP ((uint8_t)0x10U) /*!< GPIO output with push-pull */ 428 #define GPIO_MODE_AF_OD ((uint8_t)0x1CU) /*!< AFIO output with open-drain */ 429 #define GPIO_MODE_AF_PP ((uint8_t)0x18U) /*!< AFIO output with push-pull */ 430 431 /* GPIO output max speed value */ 432 #define GPIO_OSPEED_10MHZ ((uint8_t)0x01U) /*!< output max speed 10MHz */ 433 #define GPIO_OSPEED_2MHZ ((uint8_t)0x02U) /*!< output max speed 2MHz */ 434 #define GPIO_OSPEED_50MHZ ((uint8_t)0x03U) /*!< output max speed 50MHz */ 435 #define GPIO_OSPEED_MAX ((uint8_t)0x04U) /*!< GPIO very high output speed, max speed more than 50MHz */ 436 437 /* GPIO event output port definitions */ 438 #define GPIO_EVENT_PORT_GPIOA ((uint8_t)0x00U) /*!< event output port A */ 439 #define GPIO_EVENT_PORT_GPIOB ((uint8_t)0x01U) /*!< event output port B */ 440 #define GPIO_EVENT_PORT_GPIOC ((uint8_t)0x02U) /*!< event output port C */ 441 #define GPIO_EVENT_PORT_GPIOD ((uint8_t)0x03U) /*!< event output port D */ 442 #define GPIO_EVENT_PORT_GPIOE ((uint8_t)0x04U) /*!< event output port E */ 443 444 /* GPIO output port source definitions */ 445 #define GPIO_PORT_SOURCE_GPIOA ((uint8_t)0x00U) /*!< output port source A */ 446 #define GPIO_PORT_SOURCE_GPIOB ((uint8_t)0x01U) /*!< output port source B */ 447 #define GPIO_PORT_SOURCE_GPIOC ((uint8_t)0x02U) /*!< output port source C */ 448 #define GPIO_PORT_SOURCE_GPIOD ((uint8_t)0x03U) /*!< output port source D */ 449 #define GPIO_PORT_SOURCE_GPIOE ((uint8_t)0x04U) /*!< output port source E */ 450 #define GPIO_PORT_SOURCE_GPIOF ((uint8_t)0x05U) /*!< output port source F */ 451 #define GPIO_PORT_SOURCE_GPIOG ((uint8_t)0x06U) /*!< output port source G */ 452 453 /* GPIO event output pin definitions */ 454 #define GPIO_EVENT_PIN_0 ((uint8_t)0x00U) /*!< GPIO event pin 0 */ 455 #define GPIO_EVENT_PIN_1 ((uint8_t)0x01U) /*!< GPIO event pin 1 */ 456 #define GPIO_EVENT_PIN_2 ((uint8_t)0x02U) /*!< GPIO event pin 2 */ 457 #define GPIO_EVENT_PIN_3 ((uint8_t)0x03U) /*!< GPIO event pin 3 */ 458 #define GPIO_EVENT_PIN_4 ((uint8_t)0x04U) /*!< GPIO event pin 4 */ 459 #define GPIO_EVENT_PIN_5 ((uint8_t)0x05U) /*!< GPIO event pin 5 */ 460 #define GPIO_EVENT_PIN_6 ((uint8_t)0x06U) /*!< GPIO event pin 6 */ 461 #define GPIO_EVENT_PIN_7 ((uint8_t)0x07U) /*!< GPIO event pin 7 */ 462 #define GPIO_EVENT_PIN_8 ((uint8_t)0x08U) /*!< GPIO event pin 8 */ 463 #define GPIO_EVENT_PIN_9 ((uint8_t)0x09U) /*!< GPIO event pin 9 */ 464 #define GPIO_EVENT_PIN_10 ((uint8_t)0x0AU) /*!< GPIO event pin 10 */ 465 #define GPIO_EVENT_PIN_11 ((uint8_t)0x0BU) /*!< GPIO event pin 11 */ 466 #define GPIO_EVENT_PIN_12 ((uint8_t)0x0CU) /*!< GPIO event pin 12 */ 467 #define GPIO_EVENT_PIN_13 ((uint8_t)0x0DU) /*!< GPIO event pin 13 */ 468 #define GPIO_EVENT_PIN_14 ((uint8_t)0x0EU) /*!< GPIO event pin 14 */ 469 #define GPIO_EVENT_PIN_15 ((uint8_t)0x0FU) /*!< GPIO event pin 15 */ 470 471 /* GPIO output pin source definitions */ 472 #define GPIO_PIN_SOURCE_0 ((uint8_t)0x00U) /*!< GPIO pin source 0 */ 473 #define GPIO_PIN_SOURCE_1 ((uint8_t)0x01U) /*!< GPIO pin source 1 */ 474 #define GPIO_PIN_SOURCE_2 ((uint8_t)0x02U) /*!< GPIO pin source 2 */ 475 #define GPIO_PIN_SOURCE_3 ((uint8_t)0x03U) /*!< GPIO pin source 3 */ 476 #define GPIO_PIN_SOURCE_4 ((uint8_t)0x04U) /*!< GPIO pin source 4 */ 477 #define GPIO_PIN_SOURCE_5 ((uint8_t)0x05U) /*!< GPIO pin source 5 */ 478 #define GPIO_PIN_SOURCE_6 ((uint8_t)0x06U) /*!< GPIO pin source 6 */ 479 #define GPIO_PIN_SOURCE_7 ((uint8_t)0x07U) /*!< GPIO pin source 7 */ 480 #define GPIO_PIN_SOURCE_8 ((uint8_t)0x08U) /*!< GPIO pin source 8 */ 481 #define GPIO_PIN_SOURCE_9 ((uint8_t)0x09U) /*!< GPIO pin source 9 */ 482 #define GPIO_PIN_SOURCE_10 ((uint8_t)0x0AU) /*!< GPIO pin source 10 */ 483 #define GPIO_PIN_SOURCE_11 ((uint8_t)0x0BU) /*!< GPIO pin source 11 */ 484 #define GPIO_PIN_SOURCE_12 ((uint8_t)0x0CU) /*!< GPIO pin source 12 */ 485 #define GPIO_PIN_SOURCE_13 ((uint8_t)0x0DU) /*!< GPIO pin source 13 */ 486 #define GPIO_PIN_SOURCE_14 ((uint8_t)0x0EU) /*!< GPIO pin source 14 */ 487 #define GPIO_PIN_SOURCE_15 ((uint8_t)0x0FU) /*!< GPIO pin source 15 */ 488 489 /* GPIO pin definitions */ 490 #define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */ 491 #define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */ 492 #define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */ 493 #define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */ 494 #define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */ 495 #define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */ 496 #define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */ 497 #define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */ 498 #define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */ 499 #define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */ 500 #define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */ 501 #define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */ 502 #define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */ 503 #define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */ 504 #define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */ 505 #define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */ 506 #define GPIO_PIN_ALL BITS(0,15) /*!< GPIO pin all */ 507 508 /* AFIO remap mask */ 509 #define PCF0_USART2_REMAP(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) /*!< USART2 remapping */ 510 #define PCF0_TIMER0_REMAP(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) /*!< TIMER0 remapping */ 511 #define PCF0_TIMER1_REMAP(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) /*!< TIMER1 remapping */ 512 #define PCF0_TIMER2_REMAP(regval) (BITS(10,11) & ((uint32_t)(regval) << 10)) /*!< TIMER2 remapping */ 513 #define PCF0_CAN0_REMAP(regval) (BITS(13,14) & ((uint32_t)(regval) << 13)) /*!< CAN0 remapping */ 514 #define PCF0_SWJ_CFG(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) /*!< serial wire JTAG configuration */ 515 #define PCF1_CTC_REMAP(regval) (BITS(11,12) & ((uint32_t)(regval) << 11)) /*!< CTC remapping */ 516 517 /* GPIO remap definitions */ 518 #define GPIO_SPI0_REMAP AFIO_PCF0_SPI0_REMAP /*!< SPI0 remapping */ 519 #define GPIO_I2C0_REMAP AFIO_PCF0_I2C0_REMAP /*!< I2C0 remapping */ 520 #define GPIO_USART0_REMAP AFIO_PCF0_USART0_REMAP /*!< USART0 remapping */ 521 #define GPIO_USART1_REMAP AFIO_PCF0_USART1_REMAP /*!< USART1 remapping */ 522 #define GPIO_USART2_PARTIAL_REMAP ((uint32_t)0x00140000U | PCF0_USART2_REMAP(1)) /*!< USART2 partial remapping */ 523 #define GPIO_USART2_FULL_REMAP ((uint32_t)0x00140000U | PCF0_USART2_REMAP(3)) /*!< USART2 full remapping */ 524 #define GPIO_TIMER0_PARTIAL_REMAP ((uint32_t)0x00160000U | PCF0_TIMER0_REMAP(1)) /*!< TIMER0 partial remapping */ 525 #define GPIO_TIMER0_FULL_REMAP ((uint32_t)0x00160000U | PCF0_TIMER0_REMAP(3)) /*!< TIMER0 full remapping */ 526 #define GPIO_TIMER1_PARTIAL_REMAP0 ((uint32_t)0x00180000U | PCF0_TIMER1_REMAP(1)) /*!< TIMER1 partial remapping */ 527 #define GPIO_TIMER1_PARTIAL_REMAP1 ((uint32_t)0x00180000U | PCF0_TIMER1_REMAP(2)) /*!< TIMER1 partial remapping */ 528 #define GPIO_TIMER1_FULL_REMAP ((uint32_t)0x00180000U | PCF0_TIMER1_REMAP(3)) /*!< TIMER1 full remapping */ 529 #define GPIO_TIMER2_PARTIAL_REMAP ((uint32_t)0x001A0000U | PCF0_TIMER2_REMAP(2)) /*!< TIMER2 partial remapping */ 530 #define GPIO_TIMER2_FULL_REMAP ((uint32_t)0x001A0000U | PCF0_TIMER2_REMAP(3)) /*!< TIMER2 full remapping */ 531 #define GPIO_TIMER3_REMAP AFIO_PCF0_TIMER3_REMAP /*!< TIMER3 remapping */ 532 #define GPIO_CAN0_PARTIAL_REMAP ((uint32_t)0x001D0000U | PCF0_CAN0_REMAP(2)) /*!< CAN0 partial remapping */ 533 #define GPIO_CAN0_FULL_REMAP ((uint32_t)0x001D0000U | PCF0_CAN0_REMAP(3)) /*!< CAN0 full remapping */ 534 #define GPIO_PD01_REMAP AFIO_PCF0_PD01_REMAP /*!< PD01 remapping */ 535 #define GPIO_TIMER4CH3_IREMAP ((uint32_t)0x00200000U | (AFIO_PCF0_TIMER4CH3_IREMAP >> 16)) /*!< TIMER4 channel3 internal remapping */ 536 #if (defined(GD32E50X_HD) || defined(GD32E50X_XD)) 537 #define GPIO_ADC0_ETRGINS_REMAP ((uint32_t)0x00200000U | (AFIO_PCF0_ADC0_ETRGINS_REMAP >> 16)) /*!< ADC0 external trigger inserted conversion remapping(only for GD32E50X_HD devices and GD32E50X_XD devices) */ 538 #define GPIO_ADC0_ETRGREG_REMAP ((uint32_t)0x00200000U | (AFIO_PCF0_ADC0_ETRGREG_REMAP >> 16)) /*!< ADC0 external trigger regular conversion remapping(only for GD32E50X_HD devices and GD32E50X_XD devices) */ 539 #define GPIO_ADC1_ETRGINS_REMAP ((uint32_t)0x00200000U | (AFIO_PCF0_ADC1_ETRGINS_REMAP >> 16)) /*!< ADC1 external trigger inserted conversion remapping(only for GD32E50X_HD devices and GD32E50X_XD devices) */ 540 #define GPIO_ADC1_ETRGREG_REMAP ((uint32_t)0x00200000U | (AFIO_PCF0_ADC1_ETRGREG_REMAP >> 16)) /*!< ADC1 external trigger regular conversion remapping(only for GD32E50X_HD devices and GD32E50X_XD devices) */ 541 #endif /* GD32E50X_HD||GD32E50X_XD */ 542 #if (defined(GD32E50X_CL) || defined(GD32EPRT)) 543 #define GPIO_ENET_REMAP ((uint32_t)0x00200000U | (AFIO_PCF0_ENET_REMAP >> 16)) /*!< ENET remapping(only for GD32E50X_CL devices) */ 544 #endif /* GD32E50X_CL */ 545 #define GPIO_CAN1_REMAP ((uint32_t)0x00200000U | (AFIO_PCF0_CAN1_REMAP >> 16)) /*!< CAN1 remapping(only for GD32E50X_CL devices) */ 546 #define GPIO_SWJ_NONJTRST_REMAP ((uint32_t)0x00300000U | (PCF0_SWJ_CFG(1) >> 16)) /*!< full SWJ(JTAG-DP + SW-DP),but without NJTRST */ 547 #define GPIO_SWJ_SWDPENABLE_REMAP ((uint32_t)0x00300000U | (PCF0_SWJ_CFG(2) >> 16)) /*!< JTAG-DP disabled and SW-DP enabled */ 548 #define GPIO_SWJ_DISABLE_REMAP ((uint32_t)0x00300000U | (PCF0_SWJ_CFG(4) >> 16)) /*!< JTAG-DP disabled and SW-DP disabled */ 549 #define GPIO_SPI2_REMAP ((uint32_t)0x00200000U | (AFIO_PCF0_SPI2_REMAP >> 16)) /*!< SPI2 remapping*/ 550 #ifdef GD32E50X_CL 551 #define GPIO_TIMER1ITR0_REMAP ((uint32_t)0x00200000U | (AFIO_PCF0_TIMER1ITR0_REMAP >> 16)) /*!< TIMER1 internal trigger 0 remapping(only for GD32E50X_CL devices) */ 552 #define GPIO_PTP_PPS_REMAP ((uint32_t)0x00200000U | (AFIO_PCF0_PTP_PPS_REMAP >> 16)) /*!< ethernet PTP PPS remapping(only for GD32E50X_CL devices) */ 553 #endif /* GD32E50X_CL */ 554 #define GPIO_TIMER8_REMAP ((uint32_t)0x80000000U | AFIO_PCF1_TIMER8_REMAP) /*!< TIMER8 remapping */ 555 #define GPIO_TIMER9_REMAP ((uint32_t)0x80000000U | AFIO_PCF1_TIMER9_REMAP) /*!< TIMER9 remapping */ 556 #define GPIO_TIMER10_REMAP ((uint32_t)0x80000000U | AFIO_PCF1_TIMER10_REMAP) /*!< TIMER10 remapping */ 557 #define GPIO_TIMER12_REMAP ((uint32_t)0x80000000U | AFIO_PCF1_TIMER12_REMAP) /*!< TIMER12 remapping */ 558 #define GPIO_TIMER13_REMAP ((uint32_t)0x80000000U | AFIO_PCF1_TIMER13_REMAP) /*!< TIMER13 remapping */ 559 #define GPIO_EXMC_NADV_REMAP ((uint32_t)0x80000000U | AFIO_PCF1_EXMC_NADV) /*!< EXMC_NADV connect/disconnect */ 560 #define GPIO_CTC_REMAP0 ((uint32_t)0x801B0000U | PCF1_CTC_REMAP(1)) /*!< CTC remapping(PD15) */ 561 #define GPIO_CTC_REMAP1 ((uint32_t)0x801B0000U | PCF1_CTC_REMAP(2)) /*!< CTC remapping(PF0) */ 562 563 /* AFIO_PCFA AFCFG mask */ 564 #define PCFA_PA8_AFCFG(regval) (BITS(16, 17) & ((uint32_t)(regval) << 16)) /*!< PA8 AFCFG */ 565 #define PCFA_PA9_AFCFG(regval) (BITS(18, 19) & ((uint32_t)(regval) << 18)) /*!< PA9 AFCFG */ 566 #define PCFA_PA10_AFCFG(regval) (BITS(20, 21) & ((uint32_t)(regval) << 20)) /*!< PA10 AFCFG */ 567 #define PCFA_PA11_AFCFG(regval) (BITS(22, 23) & ((uint32_t)(regval) << 22)) /*!< PA11 AFCFG */ 568 #define PCFA_PA12_AFCFG(regval) (BITS(24, 25) & ((uint32_t)(regval) << 24)) /*!< PA12 AFCFG */ 569 570 /* AFIO_PCFB AFCFG mask */ 571 #define PCFB_PB1_AFCFG(regval) (BITS(2, 3) & ((uint32_t)(regval) << 2)) /*!< PB1 AFCFG */ 572 #define PCFB_PB2_AFCFG(regval) (BITS(4, 5) & ((uint32_t)(regval) << 4)) /*!< PB2 AFCFG */ 573 #define PCFB_PB4_AFCFG(regval) (BITS(8, 9) & ((uint32_t)(regval) << 8)) /*!< PB4 AFCFG */ 574 #define PCFB_PB5_AFCFG(regval) (BITS(10, 11) & ((uint32_t)(regval) << 10)) /*!< PB5 AFCFG */ 575 #define PCFB_PB8_AFCFG(regval) (BITS(16, 17) & ((uint32_t)(regval) << 16)) /*!< PB8 AFCFG */ 576 #define PCFB_PB9_AFCFG(regval) (BITS(18, 19) & ((uint32_t)(regval) << 18)) /*!< PB9 AFCFG */ 577 #define PCFB_PB10_AFCFG(regval) (BITS(20, 21) & ((uint32_t)(regval) << 20)) /*!< PB10 AFCFG */ 578 #define PCFB_PB11_AFCFG(regval) (BITS(22, 23) & ((uint32_t)(regval) << 22)) /*!< PB11 AFCFG */ 579 #define PCFB_PB12_AFCFG(regval) (BITS(24, 25) & ((uint32_t)(regval) << 24)) /*!< PB12 AFCFG */ 580 #define PCFB_PB13_AFCFG(regval) (BITS(26, 27) & ((uint32_t)(regval) << 26)) /*!< PB13 AFCFG */ 581 #define PCFB_PB14_AFCFG(regval) (BITS(28, 29) & ((uint32_t)(regval) << 28)) /*!< PB14 AFCFG */ 582 583 /* AFIO_PCFC AFCFG mask */ 584 #define PCFC_PC2_AFCFG(regval) (BITS(4, 5) & ((uint32_t)(regval) << 4)) /*!< PC2 AFCFG */ 585 #define PCFC_PC6_AFCFG(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12)) /*!< PC6 AFCFG */ 586 #define PCFC_PC7_AFCFG(regval) (BITS(14, 15) & ((uint32_t)(regval) << 14)) /*!< PC7 AFCFG */ 587 #define PCFC_PC8_AFCFG(regval) (BITS(16, 17) & ((uint32_t)(regval) << 16)) /*!< PC8 AFCFG */ 588 #define PCFC_PC9_AFCFG(regval) (BITS(18, 19) & ((uint32_t)(regval) << 18)) /*!< PC9 AFCFG */ 589 #define PCFC_PC11_AFCFG(regval) (BITS(22, 23) & ((uint32_t)(regval) << 22)) /*!< PC11 AFCFG */ 590 591 /* AFIO_PCFE AFCFG mask */ 592 #define PCFE_PE0_AFCFG(regval) (BITS(0, 1) & ((uint32_t)(regval))) /*!< PE0 AFCFG */ 593 #define PCFE_PE1_AFCFG(regval) (BITS(2, 3) & ((uint32_t)(regval) << 2)) /*!< PE1 AFCFG */ 594 595 /* AFIO_PCFG AFCFG mask */ 596 #define PCFG_PG7_AFCFG(regval) (BITS(14, 15) & ((uint32_t)(regval) << 14)) /*!< PG7 AFCFG */ 597 598 /* GPIOA AF function definitions */ 599 #define AFIO_PA2_CMP1_CFG AFIO_PCFA_PA2_AFCFG /*!< configure PA2 alternate function to CMP1 */ 600 #define AFIO_PA3_USBHS_CFG AFIO_PCFA_PA3_AFCFG /*!< configure PA3 alternate function to USBHS */ 601 #define AFIO_PA5_USBHS_CFG AFIO_PCFA_PA5_AFCFG /*!< configure PA5 alternate function to USBHS */ 602 #define AFIO_PA8_I2C2_CFG ((uint32_t)0x00300000U | (PCFA_PA8_AFCFG(1) >> 16)) /*!< configure PA8 alternate function to I2C2 */ 603 #define AFIO_PA8_SHRTIMER_CFG ((uint32_t)0x00300000U | (PCFA_PA8_AFCFG(2) >> 16)) /*!< configure PA8 alternate function to SHRTIMER */ 604 #define AFIO_PA9_CAN2_CFG ((uint32_t)0x00320000U | (PCFA_PA9_AFCFG(1) >> 16)) /*!< configure PA9 alternate function to CAN2 */ 605 #define AFIO_PA9_I2C2_CFG ((uint32_t)0x00320000U | (PCFA_PA9_AFCFG(2) >> 16)) /*!< configure PA9 alternate function to I2C2 */ 606 #define AFIO_PA9_SHRTIMER_CFG ((uint32_t)0x00320000U | (PCFA_PA9_AFCFG(3) >> 16)) /*!< configure PA9 alternate function to SHRTIMER */ 607 #define AFIO_PA10_CAN2_CFG ((uint32_t)0x00340000U | (PCFA_PA10_AFCFG(1) >> 16)) /*!< configure PA10 alternate function to CAN2 */ 608 #define AFIO_PA10_CMP5_CFG ((uint32_t)0x00340000U | (PCFA_PA10_AFCFG(2) >> 16)) /*!< configure PA10 alternate function to CMP5 */ 609 #define AFIO_PA10_SHRTIMER_CFG ((uint32_t)0x00340000U | (PCFA_PA10_AFCFG(3) >> 16)) /*!< configure PA10 alternate function to SHRTIMER */ 610 #define AFIO_PA11_USART5_CFG ((uint32_t)0x00360000U | (PCFA_PA11_AFCFG(1) >> 16)) /*!< configure PA11 alternate function to USART5 */ 611 #define AFIO_PA11_SHRTIMER_CFG ((uint32_t)0x00360000U | (PCFA_PA11_AFCFG(2) >> 16)) /*!< configure PA11 alternate function to SHRTIMER */ 612 #define AFIO_PA12_CMP1_CFG ((uint32_t)0x00380000U | (PCFA_PA12_AFCFG(1) >> 16)) /*!< configure PA12 alternate function to CMP1 */ 613 #define AFIO_PA12_USART5_CFG ((uint32_t)0x00380000U | (PCFA_PA12_AFCFG(2) >> 16)) /*!< configure PA12 alternate function to USART5 */ 614 #define AFIO_PA12_SHRTIMER_CFG ((uint32_t)0x00380000U | (PCFA_PA12_AFCFG(3) >> 16)) /*!< configure PA12 alternate function to SHRTIMER */ 615 #define AFIO_PA15_SHRTIMER_CFG ((uint32_t)0x00200000U | AFIO_PCFA_PA15_AFCFG >> 16) /*!< configure PA15 alternate function to SHRTIMER */ 616 617 /* GPIOB AF function definitions */ 618 #define AFIO_PB0_USBHS_CFG ((uint32_t)0x01000000U | AFIO_PCFB_PB0_AFCFG) /*!< configure PB0 alternate function to USBHS */ 619 #define AFIO_PB1_CMP3_CFG ((uint32_t)0x01120000U | PCFB_PB1_AFCFG(1)) /*!< configure PB1 alternate function to CMP3 */ 620 #define AFIO_PB1_USBHS_CFG ((uint32_t)0x01120000U | PCFB_PB1_AFCFG(2)) /*!< configure PB1 alternate function to USBHS */ 621 #define AFIO_PB1_SHRTIMER_CFG ((uint32_t)0x01120000U | PCFB_PB1_AFCFG(3)) /*!< configure PB1 alternate function to SHRTIMER */ 622 #define AFIO_PB2_USBHS_CFG ((uint32_t)0x01140000U | PCFB_PB2_AFCFG(2)) /*!< configure PB2 alternate function to USBHS */ 623 #define AFIO_PB2_SHRTIMER_CFG ((uint32_t)0x01140000U | PCFB_PB2_AFCFG(1)) /*!< configure PB2 alternate function to SHRTIMER */ 624 #define AFIO_PB3_SHRTIMER_CFG ((uint32_t)0x01000000U | AFIO_PCFB_PB3_AFCFG) /*!< configure PB3 alternate function to SHRTIMER */ 625 #define AFIO_PB4_I2S2_CFG ((uint32_t)0x01180000U | PCFB_PB4_AFCFG(1)) /*!< configure PB4 alternate function to I2S2 */ 626 #define AFIO_PB4_I2C2_CFG ((uint32_t)0x01180000U | PCFB_PB4_AFCFG(2)) /*!< configure PB4 alternate function to I2C2 */ 627 #define AFIO_PB4_SHRTIMER_CFG ((uint32_t)0x01180000U | PCFB_PB4_AFCFG(3)) /*!< configure PB4 alternate function to SHRTIMER */ 628 #define AFIO_PB5_I2C2_CFG ((uint32_t)0x011A0000U | PCFB_PB5_AFCFG(1)) /*!< configure PB5 alternate function to I2C2 */ 629 #define AFIO_PB5_USBHS_CFG ((uint32_t)0x011A0000U | PCFB_PB5_AFCFG(2)) /*!< configure PB5 alternate function to USBHS */ 630 #define AFIO_PB5_SHRTIMER_CFG ((uint32_t)0x011A0000U | PCFB_PB5_AFCFG(3)) /*!< configure PB5 alternate function to SHRTIMER */ 631 #define AFIO_PB6_SHRTIMER_CFG ((uint32_t)0x01000000U | AFIO_PCFB_PB6_AFCFG) /*!< configure PB6 alternate function to SHRTIMER */ 632 #define AFIO_PB7_SHRTIMER_CFG ((uint32_t)0x01000000U | AFIO_PCFB_PB7_AFCFG) /*!< configure PB7 alternate function to SHRTIMER */ 633 #define AFIO_PB8_I2C2_CFG ((uint32_t)0x01300000U | (PCFB_PB8_AFCFG(1) >> 16)) /*!< configure PB8 alternate function to I2C2 */ 634 #define AFIO_PB8_SHRTIMER_CFG ((uint32_t)0x01300000U | (PCFB_PB8_AFCFG(2) >> 16)) /*!< configure PB8 alternate function to SHRTIMER */ 635 #define AFIO_PB9_CMP1_CFG ((uint32_t)0x01320000U | (PCFB_PB9_AFCFG(1) >> 16)) /*!< configure PB9 alternate function to CMP1 */ 636 #define AFIO_PB9_SHRTIMER_CFG ((uint32_t)0x01320000U | (PCFB_PB9_AFCFG(2) >> 16)) /*!< configure PB9 alternate function to SHRTIMER */ 637 #define AFIO_PB10_CAN2_CFG ((uint32_t)0x01340000U | (PCFB_PB10_AFCFG(1) >> 16)) /*!< configure PB10 alternate function to CAN2 */ 638 #define AFIO_PB10_USBHS_CFG ((uint32_t)0x01340000U | (PCFB_PB10_AFCFG(2) >> 16)) /*!< configure PB10 alternate function to USBHS */ 639 #define AFIO_PB10_SHRTIMER_CFG ((uint32_t)0x01340000U | (PCFB_PB10_AFCFG(3) >> 16)) /*!< configure PB10 alternate function to SHRTIMER */ 640 #define AFIO_PB11_CAN2_CFG ((uint32_t)0x01360000U | (PCFB_PB11_AFCFG(1) >> 16)) /*!< configure PB11 alternate function to CAN2 */ 641 #define AFIO_PB11_USBHS_CFG ((uint32_t)0x01360000U | (PCFB_PB11_AFCFG(2) >> 16)) /*!< configure PB11 alternate function to USBHS */ 642 #define AFIO_PB11_SHRTIMER_CFG ((uint32_t)0x01360000U | (PCFB_PB11_AFCFG(3) >> 16)) /*!< configure PB11 alternate function to SHRTIMER */ 643 #define AFIO_PB12_USBHS_CFG ((uint32_t)0x01380000U | (PCFB_PB12_AFCFG(2) >> 16)) /*!< configure PB12 alternate function to USBHS */ 644 #define AFIO_PB12_SHRTIMER_CFG ((uint32_t)0x01380000U | (PCFB_PB12_AFCFG(1) >> 16)) /*!< configure PB12 alternate function to SHRTIMER */ 645 #define AFIO_PB13_USBHS_CFG ((uint32_t)0x013A0000U | (PCFB_PB13_AFCFG(2) >> 16)) /*!< configure PB13 alternate function to USBHS */ 646 #define AFIO_PB13_SHRTIMER_CFG ((uint32_t)0x013A0000U | (PCFB_PB13_AFCFG(1) >> 16)) /*!< configure PB13 alternate function to SHRTIMER */ 647 #define AFIO_PB14_I2S1_CFG ((uint32_t)0x013C0000U | (PCFB_PB14_AFCFG(1) >> 16)) /*!< configure PB14 alternate function to I2S1 */ 648 #define AFIO_PB14_SHRTIMER_CFG ((uint32_t)0x013C0000U | (PCFB_PB14_AFCFG(2) >> 16)) /*!< configure PB14 alternate function to SHRTIMER */ 649 #define AFIO_PB15_SHRTIMER_CFG ((uint32_t)0x01200000U | (AFIO_PCFB_PB15_AFCFG >> 16)) /*!< configure PB15 alternate function to SHRTIMER */ 650 651 /* GPIOC AF function definitions */ 652 #define AFIO_PC0_USBHS_CFG ((uint32_t)0x02000000U | AFIO_PCFC_PC0_AFCFG) /*!< configure PC0 alternate function to USBHS */ 653 #define AFIO_PC2_I2S1_CFG ((uint32_t)0x02140000U | PCFC_PC2_AFCFG(1)) /*!< configure PC2 alternate function to I2S1 */ 654 #define AFIO_PC2_USBHS_CFG ((uint32_t)0x02140000U | PCFC_PC2_AFCFG(2)) /*!< configure PC2 alternate function to USBHS */ 655 #define AFIO_PC3_USBHS_CFG ((uint32_t)0x02000000U | AFIO_PCFC_PC3_AFCFG) /*!< configure PC3 alternate function to USBHS */ 656 #define AFIO_PC6_CMP5_CFG ((uint32_t)0x021C0000U | PCFC_PC6_AFCFG(1)) /*!< configure PC6 alternate function to CMP5 */ 657 #define AFIO_PC6_USART5_CFG ((uint32_t)0x021C0000U | PCFC_PC6_AFCFG(2)) /*!< configure PC6 alternate function to USART5 */ 658 #define AFIO_PC6_SHRTIMER_CFG ((uint32_t)0x021C0000U | PCFC_PC6_AFCFG(3)) /*!< configure PC6 alternate function to SHRTIMER */ 659 #define AFIO_PC7_USART5_CFG ((uint32_t)0x021E0000U | PCFC_PC7_AFCFG(2)) /*!< configure PC7 alternate function to USART5 */ 660 #define AFIO_PC7_SHRTIMER_CFG ((uint32_t)0x021E0000U | PCFC_PC7_AFCFG(1)) /*!< configure PC7 alternate function to SHRTIMER */ 661 #define AFIO_PC8_USART5_CFG ((uint32_t)0x02300000U | (PCFC_PC8_AFCFG(2) >> 16)) /*!< configure PC8 alternate function to USART5 */ 662 #define AFIO_PC8_SHRTIMER_CFG ((uint32_t)0x02300000U | (PCFC_PC8_AFCFG(1) >> 16)) /*!< configure PC8 alternate function to SHRTIMER */ 663 #define AFIO_PC9_I2C2_CFG ((uint32_t)0x02320000U | (PCFC_PC9_AFCFG(2) >> 16)) /*!< configure PC9 alternate function to I2C2 */ 664 #define AFIO_PC9_SHRTIMER_CFG ((uint32_t)0x02320000U | (PCFC_PC9_AFCFG(1) >> 16)) /*!< configure PC9 alternate function to SHRTIMER */ 665 #define AFIO_PC10_I2C2_CFG ((uint32_t)0x02200000U | (AFIO_PCFC_PC10_AFCFG >> 16)) /*!< configure PC10 alternate function to I2C2 */ 666 #define AFIO_PC11_I2S2_CFG ((uint32_t)0x02360000U | (PCFC_PC11_AFCFG(2) >> 16)) /*!< configure PC11 alternate function to I2S2 */ 667 #define AFIO_PC11_SHRTIMER_CFG ((uint32_t)0x02360000U | (PCFC_PC11_AFCFG(1) >> 16)) /*!< configure PC11 alternate function to SHRTIMER */ 668 #define AFIO_PC12_SHRTIMER_CFG ((uint32_t)0x02200000U | (AFIO_PCFC_PC12_AFCFG >> 16)) /*!< configure PC12 alternate function to SHRTIMER */ 669 670 /* GPIOD AF function definitions */ 671 #define AFIO_PD4_SHRTIMER_CFG ((uint32_t)0x03000000U | AFIO_PCFD_PD4_AFCFG) /*!< configure PD4 alternate function to SHRTIMER */ 672 #define AFIO_PD5_SHRTIMER_CFG ((uint32_t)0x03000000U | AFIO_PCFD_PD5_AFCFG) /*!< configure PD5 alternate function to SHRTIMER */ 673 674 /* GPIOE AF function definitions */ 675 #define AFIO_PE0_CAN2_CFG ((uint32_t)0x04100000U | PCFE_PE0_AFCFG(1)) /*!< configure PE0 alternate function to CAN2 */ 676 #define AFIO_PE0_SHRTIMER_CFG ((uint32_t)0x04100000U | PCFE_PE0_AFCFG(2)) /*!< configure PE0 alternate function to SHRTIMER */ 677 #define AFIO_PE1_CAN2_CFG ((uint32_t)0x04120000U | PCFE_PE1_AFCFG(1)) /*!< configure PE1 alternate function to CAN2 */ 678 #define AFIO_PE1_SHRTIMER_CFG ((uint32_t)0x04120000U | PCFE_PE1_AFCFG(2)) /*!< configure PE1 alternate function to SHRTIMER */ 679 #define AFIO_PE8_CMP1_CFG ((uint32_t)0x04200000U | (AFIO_PCFE_PE8_AFCFG >> 16)) /*!< configure PE8 alternate function to CMP1 */ 680 #define AFIO_PE9_CMP3_CFG ((uint32_t)0x04200000U | (AFIO_PCFE_PE9_AFCFG >> 16)) /*!< configure PE9 alternate function to CMP3 */ 681 #define AFIO_PE10_CMP5_CFG ((uint32_t)0x04200000U | (AFIO_PCFE_PE10_AFCFG >> 16)) /*!< configure PE10 alternate function to CMP5 */ 682 #define AFIO_PE11_CMP5_CFG ((uint32_t)0x04200000U | (AFIO_PCFE_PE11_AFCFG >> 16)) /*!< configure PE11 alternate function to CMP5 */ 683 #define AFIO_PE12_CMP3_CFG ((uint32_t)0x04200000U | (AFIO_PCFE_PE12_AFCFG >> 16)) /*!< configure PE12 alternate function to CMP3 */ 684 #define AFIO_PE13_CMP1_CFG ((uint32_t)0x04200000U | (AFIO_PCFE_PE13_AFCFG >> 16)) /*!< configure PE13 alternate function to CMP1 */ 685 686 /* GPIOG AF function definitions */ 687 #define AFIO_PG6_SHRTIMER_CFG ((uint32_t)0x06000000U | AFIO_PCFG_PG6_AFCFG) /*!< configure PG6 alternate function to SHRTIMER_CFG */ 688 #define AFIO_PG7_USART5_CFG ((uint32_t)0x061E0000U | PCFG_PG7_AFCFG(1)) /*!< configure PG7 alternate function to USART5 */ 689 #define AFIO_PG7_SHRTIMER_CFG ((uint32_t)0x061E0000U | PCFG_PG7_AFCFG(2)) /*!< configure PG7 alternate function to SHRTIMER */ 690 #define AFIO_PG9_USART5_CFG ((uint32_t)0x06200000U | (AFIO_PCFG_PG9_AFCFG >> 16)) /*!< configure PG9 alternate function to USART5 */ 691 #define AFIO_PG10_SHRTIMER_CFG ((uint32_t)0x06200000U | (AFIO_PCFG_PG10_AFCFG >> 16)) /*!< configure PG10 alternate function to SHRTIMER */ 692 #define AFIO_PG11_SHRTIMER_CFG ((uint32_t)0x06200000U | (AFIO_PCFG_PG11_AFCFG >> 16)) /*!< configure PG11 alternate function to SHRTIMER */ 693 #define AFIO_PG12_SHRTIMER_CFG ((uint32_t)0x06200000U | (AFIO_PCFG_PG12_AFCFG >> 16)) /*!< configure PG12 alternate function to SHRTIMER */ 694 #define AFIO_PG13_SHRTIMER_CFG ((uint32_t)0x06200000U | (AFIO_PCFG_PG13_AFCFG >> 16)) /*!< configure PG13 alternate function to SHRTIMER */ 695 #define AFIO_PG14_USART5_CFG ((uint32_t)0x06200000U | (AFIO_PCFG_PG14_AFCFG >> 16)) /*!< configure PG14 alternate function to USART5 */ 696 697 #if (defined(GD32E50X_CL) || defined(GD32EPRT)) 698 /* ethernet MII or RMII PHY selection */ 699 #define GPIO_ENET_PHY_MII ((uint32_t)0x00000000U) /*!< configure ethernet MAC for connection with an MII PHY */ 700 #define GPIO_ENET_PHY_RMII AFIO_PCF0_ENET_PHY_SEL /*!< configure ethernet MAC for connection with an RMII PHY */ 701 #endif /* GD32E50X_CL||GD32EPRT */ 702 703 /* I/O compensation cell enable/disable */ 704 #define GPIO_COMPENSATION_ENABLE AFIO_CPSCTL_CPS_EN /*!< I/O compensation cell is enable */ 705 #define GPIO_COMPENSATION_DISABLE ((uint32_t)0x00000000U) /*!< I/O compensation cell is disable */ 706 707 /* function declarations */ 708 /* reset GPIO port */ 709 void gpio_deinit(uint32_t gpio_periph); 710 /* reset alternate function I/O(AFIO) */ 711 void gpio_afio_deinit(void); 712 /* GPIO parameter initialization */ 713 void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin); 714 715 /* set GPIO pin bit */ 716 void gpio_bit_set(uint32_t gpio_periph, uint32_t pin); 717 /* reset GPIO pin bit */ 718 void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin); 719 /* write data to the specified GPIO pin */ 720 void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value); 721 /* write data to the specified GPIO port */ 722 void gpio_port_write(uint32_t gpio_periph, uint16_t data); 723 724 /* get GPIO pin input status */ 725 FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin); 726 /* get GPIO port input status */ 727 uint16_t gpio_input_port_get(uint32_t gpio_periph); 728 /* get GPIO pin output status */ 729 FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin); 730 /* get GPIO port output status */ 731 uint16_t gpio_output_port_get(uint32_t gpio_periph); 732 /* configure GPIO pin remap */ 733 void gpio_pin_remap_config(uint32_t remap, ControlStatus newvalue); 734 /* configure AFIO port alternate function */ 735 void gpio_afio_port_config(uint32_t afio_function, ControlStatus newvalue); 736 737 #if (defined(GD32E50X_CL) || defined(GD32EPRT)) 738 /* select ethernet MII or RMII PHY */ 739 void gpio_ethernet_phy_select(uint32_t enet_sel); 740 #endif /* GD32E50X_CL||GD32EPRT */ 741 742 /* select GPIO pin exti sources */ 743 void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin); 744 745 /* configure GPIO pin event output */ 746 void gpio_event_output_config(uint8_t output_port, uint8_t output_pin); 747 /* enable GPIO pin event output */ 748 void gpio_event_output_enable(void); 749 /* disable GPIO pin event output */ 750 void gpio_event_output_disable(void); 751 752 /* lock GPIO pin bit */ 753 void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin); 754 /* configure the I/O compensation cell */ 755 void gpio_compensation_config(uint32_t compensation); 756 /* check the I/O compensation cell is ready or not */ 757 FlagStatus gpio_compensation_flag_get(void); 758 759 #endif /* GD32E50X_GPIO_H */ 760
