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Searched refs:AFIO_CPSCTL_CPS_RDY (Results 1 – 6 of 6) sorted by relevance

/hal_gigadevice-latest/gd32f403/standard_peripheral/source/
Dgd32f403_gpio.c549 if(((uint32_t)RESET) != (AFIO_CPSCTL & AFIO_CPSCTL_CPS_RDY)){ in gpio_compensation_flag_get()
/hal_gigadevice-latest/gd32e10x/standard_peripheral/source/
Dgd32e10x_gpio.c536 if(((uint32_t)RESET) != (AFIO_CPSCTL & AFIO_CPSCTL_CPS_RDY)){ in gpio_compensation_flag_get()
/hal_gigadevice-latest/gd32e50x/standard_peripheral/source/
Dgd32e50x_gpio.c698 if(((uint32_t)RESET) != (AFIO_CPSCTL & AFIO_CPSCTL_CPS_RDY)){ in gpio_compensation_flag_get()
/hal_gigadevice-latest/gd32e10x/standard_peripheral/include/
Dgd32e10x_gpio.h291 #define AFIO_CPSCTL_CPS_RDY BIT(8) /*!< I/O compensation cell is ready or… macro
/hal_gigadevice-latest/gd32f403/standard_peripheral/include/
Dgd32f403_gpio.h296 #define AFIO_CPSCTL_CPS_RDY BIT(8) /*!< I/O compensation cell is ready or… macro
/hal_gigadevice-latest/gd32e50x/standard_peripheral/include/
Dgd32e50x_gpio.h347 #define AFIO_CPSCTL_CPS_RDY BIT(8) /*!< I/O compensation cell is ready or… macro