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Searched refs:AFIO (Results 1 – 6 of 6) sorted by relevance

/hal_gigadevice-latest/gd32e10x/standard_peripheral/include/
Dgd32e10x_gpio.h51 #define AFIO AFIO_BASE macro
65 #define AFIO_EC REG32(AFIO + 0x00U) /*!< AFIO event control register */
66 #define AFIO_PCF0 REG32(AFIO + 0x04U) /*!< AFIO port configuration register …
67 #define AFIO_EXTISS0 REG32(AFIO + 0x08U) /*!< AFIO port EXTI sources selection …
68 #define AFIO_EXTISS1 REG32(AFIO + 0x0CU) /*!< AFIO port EXTI sources selection …
69 #define AFIO_EXTISS2 REG32(AFIO + 0x10U) /*!< AFIO port EXTI sources selection …
70 #define AFIO_EXTISS3 REG32(AFIO + 0x14U) /*!< AFIO port EXTI sources selection …
71 #define AFIO_PCF1 REG32(AFIO + 0x1CU) /*!< AFIO port configuration register …
72 #define AFIO_CPSCTL REG32(AFIO + 0x20U) /*!< IO compensation control register …
/hal_gigadevice-latest/gd32vf103/standard_peripheral/include/
Dgd32vf103_gpio.h49 #define AFIO AFIO_BASE macro
63 #define AFIO_EC REG32(AFIO + 0x00U) /*!< AFIO event control register */
64 #define AFIO_PCF0 REG32(AFIO + 0x04U) /*!< AFIO port configuration register …
65 #define AFIO_EXTISS0 REG32(AFIO + 0x08U) /*!< AFIO port EXTI sources selection …
66 #define AFIO_EXTISS1 REG32(AFIO + 0x0CU) /*!< AFIO port EXTI sources selection …
67 #define AFIO_EXTISS2 REG32(AFIO + 0x10U) /*!< AFIO port EXTI sources selection …
68 #define AFIO_EXTISS3 REG32(AFIO + 0x14U) /*!< AFIO port EXTI sources selection …
69 #define AFIO_PCF1 REG32(AFIO + 0x1CU) /*!< AFIO port configuration register …
/hal_gigadevice-latest/gd32e50x/standard_peripheral/include/
Dgd32e50x_gpio.h52 #define AFIO AFIO_BASE /*!< AFIO bsae address */ macro
66 #define AFIO_EC REG32(AFIO + 0x00000000U) /*!< AFIO event control registe…
67 #define AFIO_PCF0 REG32(AFIO + 0x00000004U) /*!< AFIO port configuration re…
68 #define AFIO_EXTISS0 REG32(AFIO + 0x00000008U) /*!< AFIO port EXTI sources sel…
69 #define AFIO_EXTISS1 REG32(AFIO + 0x0000000CU) /*!< AFIO port EXTI sources sel…
70 #define AFIO_EXTISS2 REG32(AFIO + 0x00000010U) /*!< AFIO port EXTI sources sel…
71 #define AFIO_EXTISS3 REG32(AFIO + 0x00000014U) /*!< AFIO port EXTI sources sel…
72 #define AFIO_PCF1 REG32(AFIO + 0x0000001CU) /*!< AFIO port configuration re…
73 #define AFIO_CPSCTL REG32(AFIO + 0x00000020U) /*!< IO compensation control re…
74 #define AFIO_PCFA REG32(AFIO + 0x0000003CU) /*!< AFIO port configuration re…
[all …]
/hal_gigadevice-latest/gd32f403/standard_peripheral/include/
Dgd32f403_gpio.h52 #define AFIO AFIO_BASE macro
66 #define AFIO_EC REG32(AFIO + 0x00U) /*!< AFIO event control register */
67 #define AFIO_PCF0 REG32(AFIO + 0x04U) /*!< AFIO port configuration register …
68 #define AFIO_EXTISS0 REG32(AFIO + 0x08U) /*!< AFIO port EXTI sources selection …
69 #define AFIO_EXTISS1 REG32(AFIO + 0x0CU) /*!< AFIO port EXTI sources selection …
70 #define AFIO_EXTISS2 REG32(AFIO + 0x10U) /*!< AFIO port EXTI sources selection …
71 #define AFIO_EXTISS3 REG32(AFIO + 0x14U) /*!< AFIO port EXTI sources selection …
72 #define AFIO_PCF1 REG32(AFIO + 0x1CU) /*!< AFIO port configuration register …
73 #define AFIO_CPSCTL REG32(AFIO + 0x20U) /*!< IO compensation control register …
/hal_gigadevice-latest/pinconfigs/
DREADME.md13 devices *AFIO model*. Some other devices, like GD32F450XX, have a simpler
18 *AFIO model*. Alternate function tables (AF0..15) will only be available on
52 ## AFIO model
54 The AFIO model supports the following fields in the configuration file:
117 The AFIO model supports the following fields in the configuration file:
/hal_gigadevice-latest/gd32e50x/standard_peripheral/source/
Dgd32e50x_gpio.c514 temp_reg = REG32(AFIO+0x0000003CU+((afio_function>>24)<<2)); in gpio_afio_port_config()
534 REG32(AFIO+0x0000003CU+((afio_function>>24)<<2)) = temp_reg; in gpio_afio_port_config()