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Searched refs:ADC_CTL1_RSTCLB (Results 1 – 16 of 16) sorted by relevance

/hal_gigadevice-latest/gd32f3x0/standard_peripheral/source/
Dgd32f3x0_adc.c84 ADC_CTL1 |= (uint32_t) ADC_CTL1_RSTCLB; in adc_calibration_enable()
86 while((ADC_CTL1 & ADC_CTL1_RSTCLB)){ in adc_calibration_enable()
/hal_gigadevice-latest/gd32l23x/standard_peripheral/source/
Dgd32l23x_adc.c108 ADC_CTL1 |= (uint32_t) ADC_CTL1_RSTCLB; in adc_calibration_enable()
110 while((ADC_CTL1 & ADC_CTL1_RSTCLB)) { in adc_calibration_enable()
/hal_gigadevice-latest/gd32f403/standard_peripheral/source/
Dgd32f403_adc.c102 ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB; in adc_calibration_enable()
104 while((ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)){ in adc_calibration_enable()
/hal_gigadevice-latest/gd32a50x/standard_peripheral/source/
Dgd32a50x_adc.c92 ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB; in adc_calibration_enable()
94 while((ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)){ in adc_calibration_enable()
/hal_gigadevice-latest/gd32e10x/standard_peripheral/source/
Dgd32e10x_adc.c208 ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB; in adc_calibration_enable()
210 while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)){ in adc_calibration_enable()
/hal_gigadevice-latest/gd32vf103/standard_peripheral/source/
Dgd32vf103_adc.c206 ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB; in adc_calibration_enable()
208 while((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)){ in adc_calibration_enable()
/hal_gigadevice-latest/gd32f4xx/standard_peripheral/source/
Dgd32f4xx_adc.c196 ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB; in adc_calibration_enable()
198 while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)) { in adc_calibration_enable()
/hal_gigadevice-latest/gd32e50x/standard_peripheral/source/
Dgd32e50x_adc.c100 ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB; in adc_calibration_enable()
102 while((ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)){ in adc_calibration_enable()
/hal_gigadevice-latest/gd32f3x0/standard_peripheral/include/
Dgd32f3x0_adc.h95 #define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration… macro
/hal_gigadevice-latest/gd32l23x/standard_peripheral/include/
Dgd32l23x_adc.h94 #define ADC_CTL1_RSTCLB BIT(3) /*!< reset cali… macro
/hal_gigadevice-latest/gd32vf103/standard_peripheral/include/
Dgd32vf103_adc.h95 #define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ macro
/hal_gigadevice-latest/gd32f403/standard_peripheral/include/
Dgd32f403_adc.h98 #define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ macro
/hal_gigadevice-latest/gd32e10x/standard_peripheral/include/
Dgd32e10x_adc.h97 #define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ macro
/hal_gigadevice-latest/gd32a50x/standard_peripheral/include/
Dgd32a50x_adc.h98 #define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ macro
/hal_gigadevice-latest/gd32f4xx/standard_peripheral/include/
Dgd32f4xx_adc.h103 #define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ macro
/hal_gigadevice-latest/gd32e50x/standard_peripheral/include/
Dgd32e50x_adc.h108 #define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ macro