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Searched refs:SPI_CTL0_SWNSS (Results 1 – 16 of 16) sorted by relevance

/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32vf103/standard_peripheral/include/
Dgd32vf103_spi.h65 #define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin select… macro
136 #define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master …
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/standard_peripheral/include/
Dgd32f403_spi.h67 #define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin select… macro
143 #define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master …
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f3x0/standard_peripheral/include/
Dgd32f3x0_spi.h66 #define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin select… macro
142 #define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master …
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/standard_peripheral/include/
Dgd32e10x_spi.h70 #define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin select… macro
146 #define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master …
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/include/
Dgd32e50x_spi.h82 #define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin select… macro
158 #define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master …
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32a50x/standard_peripheral/source/
Dgd32a50x_spi.c361 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS; in spi_nss_internal_high()
372 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS); in spi_nss_internal_low()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32a50x/standard_peripheral/include/
Dgd32a50x_spi.h75 #define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin select… macro
151 #define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master …
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f4xx/standard_peripheral/include/
Dgd32f4xx_spi.h87 #define SPI_CTL0_SWNSS BIT(8) /*!< nss pin select… macro
161 #define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master …
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f3x0/standard_peripheral/source/
Dgd32f3x0_spi.c321 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS; in spi_nss_internal_high()
332 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS); in spi_nss_internal_low()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32vf103/standard_peripheral/source/
Dgd32vf103_spi.c358 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS; in spi_nss_internal_high()
369 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS); in spi_nss_internal_low()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/source/
Dgd32e50x_spi.c383 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS; in spi_nss_internal_high()
394 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS); in spi_nss_internal_low()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32l23x/standard_peripheral/include/
Dgd32l23x_spi.h64 #define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin select… macro
144 #define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master …
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/standard_peripheral/source/
Dgd32e10x_spi.c375 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS; in spi_nss_internal_high()
386 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS); in spi_nss_internal_low()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/standard_peripheral/source/
Dgd32f403_spi.c366 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS; in spi_nss_internal_high()
377 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS); in spi_nss_internal_low()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f4xx/standard_peripheral/source/
Dgd32f4xx_spi.c376 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS; in spi_nss_internal_high()
387 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS); in spi_nss_internal_low()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32l23x/standard_peripheral/source/
Dgd32l23x_spi.c411 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS; in spi_nss_internal_high()
422 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS); in spi_nss_internal_low()