| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32a50x/standard_peripheral/source/ |
| D | gd32a50x_spi.c | 115 reg = SPI_CTL0(spi_periph); in spi_init()
134 SPI_CTL0(spi_periph) = (uint32_t)reg; in spi_init()
147 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN; in spi_enable()
158 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN); in spi_disable()
361 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS; in spi_nss_internal_high()
372 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS); in spi_nss_internal_low()
426 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16); in spi_i2s_data_frame_format_config()
428 SPI_CTL0(spi_periph) |= (uint32_t)frame_format; in spi_i2s_data_frame_format_config()
445 SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT; in spi_bidirectional_transfer_config()
448 SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE; in spi_bidirectional_transfer_config()
[all …]
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f3x0/standard_peripheral/source/ |
| D | gd32f3x0_spi.c | 105 reg = SPI_CTL0(spi_periph); in spi_init()
124 SPI_CTL0(spi_periph) = (uint32_t)reg; in spi_init()
138 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN; in spi_enable()
149 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN); in spi_disable()
321 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS; in spi_nss_internal_high()
332 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS); in spi_nss_internal_low()
386 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16); in spi_i2s_data_frame_format_config()
388 SPI_CTL0(spi_periph) |= (uint32_t)frame_format; in spi_i2s_data_frame_format_config()
428 SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT; in spi_bidirectional_transfer_config()
431 SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE; in spi_bidirectional_transfer_config()
[all …]
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32vf103/standard_peripheral/source/ |
| D | gd32vf103_spi.c | 119 reg = SPI_CTL0(spi_periph); in spi_init()
138 SPI_CTL0(spi_periph) = (uint32_t)reg; in spi_init()
151 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN; in spi_enable()
162 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN); in spi_disable()
358 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS; in spi_nss_internal_high()
369 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS); in spi_nss_internal_low()
423 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16); in spi_i2s_data_frame_format_config()
425 SPI_CTL0(spi_periph) |= (uint32_t)frame_format; in spi_i2s_data_frame_format_config()
465 SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT; in spi_bidirectional_transfer_config()
468 SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE; in spi_bidirectional_transfer_config()
[all …]
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32l23x/standard_peripheral/source/ |
| D | gd32l23x_spi.c | 130 reg1 = SPI_CTL0(spi_periph); in spi_init()
133 reg2 = SPI_CTL0(spi_periph); in spi_init()
161 SPI_CTL0(spi_periph) = (uint32_t)reg1; in spi_init()
177 SPI_CTL0(spi_periph) = (uint32_t)reg2; in spi_init()
199 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN; in spi_enable()
210 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN); in spi_disable()
411 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS; in spi_nss_internal_high()
422 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS); in spi_nss_internal_low()
481 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16); in spi_i2s_data_frame_format_config()
483 SPI_CTL0(spi_periph) |= ((uint32_t)frame_format & SPI_FRAMESIZE_MASK); in spi_i2s_data_frame_format_config()
[all …]
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/source/ |
| D | gd32e50x_spi.c | 120 reg = SPI_CTL0(spi_periph); in spi_init()
139 SPI_CTL0(spi_periph) = (uint32_t)reg; in spi_init()
152 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN; in spi_enable()
163 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN); in spi_disable()
383 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS; in spi_nss_internal_high()
394 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS); in spi_nss_internal_low()
448 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16); in spi_i2s_data_frame_format_config()
450 SPI_CTL0(spi_periph) |= (uint32_t)frame_format; in spi_i2s_data_frame_format_config()
489 SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT; in spi_bidirectional_transfer_config()
492 SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE; in spi_bidirectional_transfer_config()
[all …]
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/standard_peripheral/source/ |
| D | gd32f403_spi.c | 121 reg = SPI_CTL0(spi_periph); in spi_init()
140 SPI_CTL0(spi_periph) = (uint32_t)reg; in spi_init()
153 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN; in spi_enable()
164 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN); in spi_disable()
366 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS; in spi_nss_internal_high()
377 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS); in spi_nss_internal_low()
431 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16); in spi_i2s_data_frame_format_config()
433 SPI_CTL0(spi_periph) |= (uint32_t)frame_format; in spi_i2s_data_frame_format_config()
472 SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT; in spi_bidirectional_transfer_config()
475 SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE; in spi_bidirectional_transfer_config()
[all …]
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/standard_peripheral/source/ |
| D | gd32e10x_spi.c | 126 reg = SPI_CTL0(spi_periph); in spi_init()
145 SPI_CTL0(spi_periph) = (uint32_t)reg; in spi_init()
158 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN; in spi_enable()
169 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN); in spi_disable()
375 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS; in spi_nss_internal_high()
386 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS); in spi_nss_internal_low()
440 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16); in spi_i2s_data_frame_format_config()
442 SPI_CTL0(spi_periph) |= (uint32_t)frame_format; in spi_i2s_data_frame_format_config()
482 SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT; in spi_bidirectional_transfer_config()
485 SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE; in spi_bidirectional_transfer_config()
[all …]
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f4xx/standard_peripheral/source/ |
| D | gd32f4xx_spi.c | 131 reg = SPI_CTL0(spi_periph); in spi_init()
150 SPI_CTL0(spi_periph) = (uint32_t)reg; in spi_init()
163 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN; in spi_enable()
174 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN); in spi_disable()
376 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS; in spi_nss_internal_high()
387 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS); in spi_nss_internal_low()
441 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16); in spi_i2s_data_frame_format_config()
443 SPI_CTL0(spi_periph) |= (uint32_t)frame_format; in spi_i2s_data_frame_format_config()
482 SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT; in spi_bidirectional_transfer_config()
485 SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE; in spi_bidirectional_transfer_config()
[all …]
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32vf103/standard_peripheral/include/ |
| D | gd32vf103_spi.h | 47 #define SPI_CTL0(spix) REG32((spix) + 0x00U) /*!< SPI control re… macro
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/standard_peripheral/include/ |
| D | gd32f403_spi.h | 48 #define SPI_CTL0(spix) REG32((spix) + 0x00U) /*!< SPI control re… macro
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f3x0/standard_peripheral/include/ |
| D | gd32f3x0_spi.h | 47 #define SPI_CTL0(spix) REG32((spix) + 0x00000000U) /*!< SPI control re… macro
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/standard_peripheral/include/ |
| D | gd32e10x_spi.h | 51 #define SPI_CTL0(spix) REG32((spix) + 0x00U) /*!< SPI control re… macro
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/include/ |
| D | gd32e50x_spi.h | 52 #define SPI_CTL0(spix) REG32((spix) + 0x00000000U) /*!< SPI control re… macro
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32a50x/standard_peripheral/include/ |
| D | gd32a50x_spi.h | 45 #define SPI_CTL0(spix) REG32((spix) + 0x00000000U) /*!< SPI control re… macro
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f4xx/standard_peripheral/include/ |
| D | gd32f4xx_spi.h | 57 #define SPI_CTL0(spix) REG32((spix) + 0x00U) /*!< SPI control re… macro
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32l23x/standard_peripheral/include/ |
| D | gd32l23x_spi.h | 45 #define SPI_CTL0(spix) REG32((spix) + 0x00000000U) /*!< SPI control re… macro
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