1 /*! 2 \file gd32l23x_slcd.h 3 \brief definitions for the SLCD 4 5 \version 2021-08-04, V1.0.0, firmware for GD32L23x 6 */ 7 8 /* 9 Copyright (c) 2021, GigaDevice Semiconductor Inc. 10 11 Redistribution and use in source and binary forms, with or without modification, 12 are permitted provided that the following conditions are met: 13 14 1. Redistributions of source code must retain the above copyright notice, this 15 list of conditions and the following disclaimer. 16 2. Redistributions in binary form must reproduce the above copyright notice, 17 this list of conditions and the following disclaimer in the documentation 18 and/or other materials provided with the distribution. 19 3. Neither the name of the copyright holder nor the names of its contributors 20 may be used to endorse or promote products derived from this software without 21 specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 32 OF SUCH DAMAGE. 33 */ 34 35 #ifndef GD32L23X_SLCD_H 36 #define GD32L23X_SLCD_H 37 38 #include "gd32l23x.h" 39 40 /* SLCD definitions */ 41 #define SLCD SLCD_BASE 42 43 /* registers definitions */ 44 #define SLCD_CTL REG32(SLCD + 0x00000000U) /*!< SLCD control register */ 45 #define SLCD_CFG REG32(SLCD + 0x00000004U) /*!< SLCD configuration register */ 46 #define SLCD_STAT REG32(SLCD + 0x00000008U) /*!< SLCD status flag register */ 47 #define SLCD_STATC REG32(SLCD + 0x0000000CU) /*!< SLCD status flag clear register */ 48 #define SLCD_DATA0 REG32(SLCD + 0x00000014U) /*!< SLCD display data registers 0 */ 49 #define SLCD_DATA1 REG32(SLCD + 0x0000001CU) /*!< SLCD display data registers 1 */ 50 #define SLCD_DATA2 REG32(SLCD + 0x00000024U) /*!< SLCD display data registers 2 */ 51 #define SLCD_DATA3 REG32(SLCD + 0x0000002CU) /*!< SLCD display data registers 3 */ 52 #define SLCD_DATA4 REG32(SLCD + 0x00000034U) /*!< SLCD display data registers 4 */ 53 #define SLCD_DATA5 REG32(SLCD + 0x0000003CU) /*!< SLCD display data registers 5 */ 54 #define SLCD_DATA6 REG32(SLCD + 0x00000044U) /*!< SLCD display data registers 6 */ 55 #define SLCD_DATA7 REG32(SLCD + 0x0000004CU) /*!< SLCD display data registers 7 */ 56 57 /* bits definitions */ 58 /* SLCD_CTL */ 59 #define SLCD_CTL_SLCDON BIT(0) /*!< controller start */ 60 #define SLCD_CTL_VSRC BIT(1) /*!< voltage source */ 61 #define SLCD_CTL_DUTY BITS(2,4) /*!< duty select */ 62 #define SLCD_CTL_BIAS BITS(5,6) /*!< bias select */ 63 #define SLCD_CTL_COMS BIT(7) /*!< common segment pad select */ 64 #define SLCD_CTL_VODEN BIT(8) /*!< voltage output driver enable */ 65 66 /* SLCD_CFG */ 67 #define SLCD_CFG_HDEN BIT(0) /*!< high drive enable */ 68 #define SLCD_CFG_SOFIE BIT(1) /*!< start of frame interrupt enable */ 69 #define SLCD_CFG_UPDIE BIT(3) /*!< update done interrupt enable */ 70 #define SLCD_CFG_PULSE BITS(4,6) /*!< pulse on duration */ 71 #define SLCD_CFG_DTD BITS(7,9) /*!< dead time duration */ 72 #define SLCD_CFG_CONR BITS(10,12) /*!< contrast ratio */ 73 #define SLCD_CFG_BLKDIV BITS(13,15) /*!< blink frequency divider */ 74 #define SLCD_CFG_BLKMOD BITS(16,17) /*!< blink mode */ 75 #define SLCD_CFG_DIV BITS(18,21) /*!< clock divider */ 76 #define SLCD_CFG_PSC BITS(22,25) /*!< clock prescaler */ 77 78 /* SLCD_STAT */ 79 #define SLCD_STAT_ONF BIT(0) /*!< controller on flag */ 80 #define SLCD_STAT_SOF BIT(1) /*!< start of frame flag */ 81 #define SLCD_STAT_UPRF BIT(2) /*!< update data request flag */ 82 #define SLCD_STAT_UPDF BIT(3) /*!< update data done flag */ 83 #define SLCD_STAT_VRDYF BIT(4) /*!< voltage ready flag */ 84 #define SLCD_STAT_SYNF BIT(5) /*!< SLCD_CFG register synchronization flag */ 85 86 /* SLCD_STATC */ 87 #define SLCD_STATC_SOFC BIT(1) /*!< start of frame flag clear */ 88 #define SLCD_STATC_UPDC BIT(3) /*!< update data done flag clear */ 89 90 /* constants definitions */ 91 /* SLCD voltage source definitions */ 92 #define CTL_VSRC(regval) (BIT(1)&((uint32_t)(regval)<<1)) 93 #define SLCD_VOLTAGE_INTERNAL CTL_VSRC(0) /*!< internal source */ 94 #define SLCD_VOLTAGE_EXTERNAL CTL_VSRC(1) /*!< external source (VSLCD pin) */ 95 96 /* SLCD duty select definitions */ 97 #define CTL_DUTY(regval) (BITS(2,4)&((uint32_t)(regval)<<2)) 98 #define SLCD_DUTY_STATIC CTL_DUTY(0) /*!< static duty */ 99 #define SLCD_DUTY_1_2 CTL_DUTY(1) /*!< 1/2 duty */ 100 #define SLCD_DUTY_1_3 CTL_DUTY(2) /*!< 1/3 duty */ 101 #define SLCD_DUTY_1_4 CTL_DUTY(3) /*!< 1/4 duty */ 102 #define SLCD_DUTY_1_8 CTL_DUTY(4) /*!< 1/8 duty */ 103 #define SLCD_DUTY_1_6 CTL_DUTY(5) /*!< 1/6 duty */ 104 105 /* SLCD bias select definitions */ 106 #define CTL_BIAS(regval) (BITS(5,6)&((uint32_t)(regval)<<5)) 107 #define SLCD_BIAS_1_4 CTL_BIAS(0) /*!< 1/4 bias */ 108 #define SLCD_BIAS_1_2 CTL_BIAS(1) /*!< 1/2 bias */ 109 #define SLCD_BIAS_1_3 CTL_BIAS(2) /*!< 1/3 bias */ 110 111 /* SLCD pulse on duration definitions */ 112 #define CFG_PULSE(regval) (BITS(4,6)&((uint32_t)(regval)<<4)) 113 #define SLCD_PULSEON_DURATION_0 CFG_PULSE(0) /*!< pulse on duration = 0 */ 114 #define SLCD_PULSEON_DURATION_1 CFG_PULSE(1) /*!< pulse on duration = 1*1/fPRE */ 115 #define SLCD_PULSEON_DURATION_2 CFG_PULSE(2) /*!< pulse on duration = 2*1/fPRE */ 116 #define SLCD_PULSEON_DURATION_3 CFG_PULSE(3) /*!< pulse on duration = 3*1/fPRE */ 117 #define SLCD_PULSEON_DURATION_4 CFG_PULSE(4) /*!< pulse on duration = 4*1/fPRE */ 118 #define SLCD_PULSEON_DURATION_5 CFG_PULSE(5) /*!< pulse on duration = 5*1/fPRE */ 119 #define SLCD_PULSEON_DURATION_6 CFG_PULSE(6) /*!< pulse on duration = 6*1/fPRE */ 120 #define SLCD_PULSEON_DURATION_7 CFG_PULSE(7) /*!< pulse on duration = 7*1/fPRE */ 121 122 /* SLCD dead time definitions */ 123 #define CFG_DTD(regval) (BITS(7,9)&((uint32_t)(regval)<<7)) 124 #define SLCD_DEADTIME_PERIOD_0 CFG_DTD(0) /*!< no dead time */ 125 #define SLCD_DEADTIME_PERIOD_1 CFG_DTD(1) /*!< 1 phase inserted between couple of frame */ 126 #define SLCD_DEADTIME_PERIOD_2 CFG_DTD(2) /*!< 2 phase inserted between couple of frame */ 127 #define SLCD_DEADTIME_PERIOD_3 CFG_DTD(3) /*!< 3 phase inserted between couple of frame */ 128 #define SLCD_DEADTIME_PERIOD_4 CFG_DTD(4) /*!< 4 phase inserted between couple of frame */ 129 #define SLCD_DEADTIME_PERIOD_5 CFG_DTD(5) /*!< 5 phase inserted between couple of frame */ 130 #define SLCD_DEADTIME_PERIOD_6 CFG_DTD(6) /*!< 6 phase inserted between couple of frame */ 131 #define SLCD_DEADTIME_PERIOD_7 CFG_DTD(7) /*!< 7 phase inserted between couple of frame */ 132 133 /* SLCD contrast definitions */ 134 #define CFG_CONR(regval) (BITS(10,12)&((uint32_t)(regval)<<10)) 135 #define SLCD_CONTRAST_LEVEL_0 CFG_CONR(0) /* contrast ratio level0:Maximum Voltage = 2.65V */ 136 #define SLCD_CONTRAST_LEVEL_1 CFG_CONR(1) /* contrast ratio level1:Maximum Voltage = 2.80V */ 137 #define SLCD_CONTRAST_LEVEL_2 CFG_CONR(2) /* contrast ratio level2:Maximum Voltage = 2.92V */ 138 #define SLCD_CONTRAST_LEVEL_3 CFG_CONR(3) /* contrast ratio level3:Maximum Voltage = 3.08V */ 139 #define SLCD_CONTRAST_LEVEL_4 CFG_CONR(4) /* contrast ratio level4:Maximum Voltage = 3.23V */ 140 #define SLCD_CONTRAST_LEVEL_5 CFG_CONR(5) /* contrast ratio level5:Maximum Voltage = 3.37V */ 141 #define SLCD_CONTRAST_LEVEL_6 CFG_CONR(6) /* contrast ratio level6:Maximum Voltage = 3.52V */ 142 #define SLCD_CONTRAST_LEVEL_7 CFG_CONR(7) /* contrast ratio level7:Maximum Voltage = 3.67V */ 143 144 /* SLCD blink frequency definitions */ 145 #define CFG_BLKDIV(regval) (BITS(13,15)&((uint32_t)(regval)<<13)) 146 #define SLCD_BLINK_FREQUENCY_DIV8 CFG_BLKDIV(0) /*!< blink frequency = fSLCD/8 */ 147 #define SLCD_BLINK_FREQUENCY_DIV16 CFG_BLKDIV(1) /*!< blink frequency = fSLCD/16 */ 148 #define SLCD_BLINK_FREQUENCY_DIV32 CFG_BLKDIV(2) /*!< blink frequency = fSLCD/32 */ 149 #define SLCD_BLINK_FREQUENCY_DIV64 CFG_BLKDIV(3) /*!< blink frequency = fSLCD/64 */ 150 #define SLCD_BLINK_FREQUENCY_DIV128 CFG_BLKDIV(4) /*!< blink frequency = fSLCD/128 */ 151 #define SLCD_BLINK_FREQUENCY_DIV256 CFG_BLKDIV(5) /*!< blink frequency = fSLCD/256 */ 152 #define SLCD_BLINK_FREQUENCY_DIV512 CFG_BLKDIV(6) /*!< blink frequency = fSLCD/512 */ 153 #define SLCD_BLINK_FREQUENCY_DIV1024 CFG_BLKDIV(7) /*!< blink frequency = fSLCD/1024 */ 154 155 156 /* SLCD blink mode definitions */ 157 #define CFG_BLKMOD(regval) (BITS(16,17)&((uint32_t)(regval)<<16)) 158 #define SLCD_BLINK_OFF CFG_BLKMOD(0) /* blink disabled */ 159 #define SLCD_BLINK_SEG0_COM0 CFG_BLKMOD(1) /* blink enabled on SEG[0], COM[0] */ 160 #define SLCD_BLINK_SEG0_ALLCOM CFG_BLKMOD(2) /* blink enabled on SEG[0], all COM */ 161 #define SLCD_BLINK_ALLSEG_ALLCOM CFG_BLKMOD(3) /* blink enabled on all SEG and all COM */ 162 163 /* SLCD divider definitions */ 164 #define CFG_DIV(regval) (BITS(18,21)&((uint32_t)(regval)<<18)) 165 #define SLCD_DIVIDER_16 CFG_DIV(0) /*!< DIV = 16 */ 166 #define SLCD_DIVIDER_17 CFG_DIV(1) /*!< DIV = 17 */ 167 #define SLCD_DIVIDER_18 CFG_DIV(2) /*!< DIV = 18 */ 168 #define SLCD_DIVIDER_19 CFG_DIV(3) /*!< DIV = 19 */ 169 #define SLCD_DIVIDER_20 CFG_DIV(4) /*!< DIV = 20 */ 170 #define SLCD_DIVIDER_21 CFG_DIV(5) /*!< DIV = 21 */ 171 #define SLCD_DIVIDER_22 CFG_DIV(6) /*!< DIV = 22 */ 172 #define SLCD_DIVIDER_23 CFG_DIV(7) /*!< DIV = 23 */ 173 #define SLCD_DIVIDER_24 CFG_DIV(8) /*!< DIV = 24 */ 174 #define SLCD_DIVIDER_25 CFG_DIV(9) /*!< DIV = 25 */ 175 #define SLCD_DIVIDER_26 CFG_DIV(10) /*!< DIV = 26 */ 176 #define SLCD_DIVIDER_27 CFG_DIV(11) /*!< DIV = 27 */ 177 #define SLCD_DIVIDER_28 CFG_DIV(12) /*!< DIV = 28 */ 178 #define SLCD_DIVIDER_29 CFG_DIV(13) /*!< DIV = 29 */ 179 #define SLCD_DIVIDER_30 CFG_DIV(14) /*!< DIV = 30 */ 180 #define SLCD_DIVIDER_31 CFG_DIV(15) /*!< DIV = 31 */ 181 182 183 /* SLCD prescaler definitions */ 184 #define CFG_PRE(regval) (BITS(22,25)&((uint32_t)(regval)<<22)) 185 #define SLCD_PRESCALER_1 CFG_PRE(0) /*!< PRE = 0 */ 186 #define SLCD_PRESCALER_2 CFG_PRE(1) /*!< PRE = 1 */ 187 #define SLCD_PRESCALER_4 CFG_PRE(2) /*!< PRE = 2 */ 188 #define SLCD_PRESCALER_8 CFG_PRE(3) /*!< PRE = 3 */ 189 #define SLCD_PRESCALER_16 CFG_PRE(4) /*!< PRE = 4 */ 190 #define SLCD_PRESCALER_32 CFG_PRE(5) /*!< PRE = 5 */ 191 #define SLCD_PRESCALER_64 CFG_PRE(6) /*!< PRE = 6 */ 192 #define SLCD_PRESCALER_128 CFG_PRE(7) /*!< PRE = 7 */ 193 #define SLCD_PRESCALER_256 CFG_PRE(8) /*!< PRE = 8 */ 194 #define SLCD_PRESCALER_512 CFG_PRE(9) /*!< PRE = 9 */ 195 #define SLCD_PRESCALER_1024 CFG_PRE(10) /*!< PRE = 10 */ 196 #define SLCD_PRESCALER_2048 CFG_PRE(11) /*!< PRE = 11 */ 197 #define SLCD_PRESCALER_4096 CFG_PRE(12) /*!< PRE = 12 */ 198 #define SLCD_PRESCALER_8192 CFG_PRE(13) /*!< PRE = 13 */ 199 #define SLCD_PRESCALER_16384 CFG_PRE(14) /*!< PRE = 14 */ 200 #define SLCD_PRESCALER_32768 CFG_PRE(15) /*!< PRE = 15 */ 201 202 /* SLCD data register */ 203 #define SLCD_DATA0_7(number) REG32((SLCD) + (uint32_t)0x14U + (number) * (uint32_t)0x08U) 204 205 /* SCLD interrupt enable or disable */ 206 #define SLCD_INT_SOF SLCD_CFG_SOFIE /*!< start of frame interrupt enable */ 207 #define SLCD_INT_UPD SLCD_CFG_UPDIE /*!< update done interrupt enable */ 208 209 /* SCLD flag */ 210 #define SLCD_FLAG_ON SLCD_STAT_ONF /*!< controller on flag */ 211 #define SLCD_FLAG_SO SLCD_STAT_SOF /*!< start of frame flag */ 212 #define SLCD_FLAG_UPR SLCD_STAT_UPRF /*!< update data request flag */ 213 #define SLCD_FLAG_UPD SLCD_STAT_UPDF /*!< update data done flag */ 214 #define SLCD_FLAG_VRDY SLCD_STAT_VRDYF /*!< voltage ready flag */ 215 #define SLCD_FLAG_SYN SLCD_STAT_SYNF /*!< SLCD_CFG register synchronization flag */ 216 217 /* SLCD interrupt flag */ 218 #define SLCD_INT_FLAG_SO SLCD_STAT_SOF /*!< start of frame flag */ 219 #define SLCD_INT_FLAG_UPD SLCD_STAT_UPDF /*!< update data done flag */ 220 221 /*data register number */ 222 typedef enum { 223 SLCD_DATA_REG0, /*!< SLCD display data register 0 */ 224 SLCD_DATA_REG1, /*!< SLCD display data register 1 */ 225 SLCD_DATA_REG2, /*!< SLCD display data register 2 */ 226 SLCD_DATA_REG3, /*!< SLCD display data register 3 */ 227 SLCD_DATA_REG4, /*!< SLCD display data register 4 */ 228 SLCD_DATA_REG5, /*!< SLCD display data register 5 */ 229 SLCD_DATA_REG6, /*!< SLCD display data register 6 */ 230 SLCD_DATA_REG7, /*!< SLCD display data register 7 */ 231 } slcd_data_register_enum; 232 233 /* function declarations */ 234 /* initialization functions */ 235 /* reset SLCD interface */ 236 void slcd_deinit(void); 237 /* enable SLCD interface */ 238 void slcd_enable(void); 239 /* disable SLCD interface */ 240 void slcd_disable(void); 241 242 /* configure SLCD functions */ 243 /* initialize SLCD interface */ 244 void slcd_init(uint32_t prescaler, uint32_t divider, uint32_t duty, uint32_t bias); 245 /* enable SLCD enhance mode */ 246 void slcd_enhance_mode_enable(void); 247 /* disable SLCD enhance mode */ 248 void slcd_enhance_mode_disable(void); 249 /* select SLCD bias voltage */ 250 void slcd_bias_voltage_select(uint32_t bias_voltage); 251 /* select SLCD duty */ 252 void slcd_duty_select(uint32_t duty); 253 /* configure SLCD input clock */ 254 void slcd_clock_config(uint32_t prescaler, uint32_t divider); 255 /* configure SLCD blink mode */ 256 void slcd_blink_mode_config(uint32_t mode, uint32_t blink_divider); 257 /* configure SLCD contrast ratio */ 258 void slcd_contrast_ratio_config(uint32_t contrast_ratio); 259 /* configure SLCD dead time duration */ 260 void slcd_dead_time_config(uint32_t dead_time); 261 /* configure SLCD pulse on duration */ 262 void slcd_pulse_on_duration_config(uint32_t duration); 263 /* select SLCD common/segment pad */ 264 void slcd_com_seg_remap(ControlStatus newvalue); 265 /* select SLCD voltage source */ 266 void slcd_voltage_source_select(uint8_t voltage_source); 267 /* enable or disable permanent high drive */ 268 void slcd_high_drive_config(ControlStatus newvalue); 269 /* write SLCD data register */ 270 void slcd_data_register_write(slcd_data_register_enum register_number, uint32_t data); 271 /* update SLCD data request */ 272 void slcd_data_update_request(void); 273 274 /* SLCD interrupt and flag */ 275 /* get SLCD flags */ 276 FlagStatus slcd_flag_get(uint32_t flag); 277 /* clear SLCD flags */ 278 void slcd_flag_clear(uint32_t flag); 279 /* enable SLCD interrupt */ 280 void slcd_interrupt_enable(uint32_t interrupt); 281 /* disable SLCD interrupt */ 282 void slcd_interrupt_disable(uint32_t interrupt); 283 /* get SLCD interrupt flag */ 284 FlagStatus slcd_interrupt_flag_get(uint32_t int_flag); 285 /* clear SLCD interrupt flag */ 286 void slcd_interrupt_flag_clear(uint32_t int_flag); 287 288 #endif /* GD32L23X_SLCD_H */ 289
