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Searched refs:SHRTIMER_MTCTL0_CNTCKDIV2_0 (Results 1 – 2 of 2) sorted by relevance

/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/source/
Dgd32e50x_shrtimer.c2760 SHRTIMER_MTCTL0(shrtimer_periph) &= (uint32_t) ~(SHRTIMER_MTCTL0_CNTCKDIV2_0); in master_timer_base_config()
2848 SHRTIMER_STXCTL0(shrtimer_periph, slave_id) &= (uint32_t) ~(SHRTIMER_MTCTL0_CNTCKDIV2_0); in slave_timer_base_config()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/include/
Dgd32e50x_shrtimer.h124 #define SHRTIMER_MTCTL0_CNTCKDIV2_0 BITS(0,2) /*!< counter clock div… macro