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Searched refs:SHRTIMER_MTCTL0 (Results 1 – 2 of 2) sorted by relevance

/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/source/
Dgd32e50x_shrtimer.c167 SHRTIMER_MTCTL0(shrtimer_periph) |= cntid; in shrtimer_timers_counter_enable()
186 SHRTIMER_MTCTL0(shrtimer_periph) &= ~(cntid); in shrtimer_timers_counter_disable()
1110 if(RESET == (SHRTIMER_MTCTL0(shrtimer_periph) & SHRTIMER_MTCTL0_MTCEN)){ in shrtimer_timers_counter_value_config()
1118 if(RESET == (SHRTIMER_MTCTL0(shrtimer_periph) & SHRTIMER_MTCTL0_ST0CEN)){ in shrtimer_timers_counter_value_config()
1126 if(RESET == (SHRTIMER_MTCTL0(shrtimer_periph) & SHRTIMER_MTCTL0_ST1CEN)){ in shrtimer_timers_counter_value_config()
1134 if(RESET == (SHRTIMER_MTCTL0(shrtimer_periph) & SHRTIMER_MTCTL0_ST2CEN)){ in shrtimer_timers_counter_value_config()
1142 if(RESET == (SHRTIMER_MTCTL0(shrtimer_periph) & SHRTIMER_MTCTL0_ST3CEN)){ in shrtimer_timers_counter_value_config()
1150 if(RESET == (SHRTIMER_MTCTL0(shrtimer_periph) & SHRTIMER_MTCTL0_ST4CEN)){ in shrtimer_timers_counter_value_config()
1547 mtctl0_reg = SHRTIMER_MTCTL0(shrtimer_periph); in shrtimer_synchronization_config()
1561 SHRTIMER_MTCTL0(shrtimer_periph) = mtctl0_reg; in shrtimer_synchronization_config()
[all …]
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/include/
Dgd32e50x_shrtimer.h47 #define SHRTIMER_MTCTL0(shrtimery) REG32((shrtimery) + 0x00000000U) … macro