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Searched refs:RESET (Results 1 – 25 of 173) sorted by relevance

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/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32l23x/standard_peripheral/source/
Dgd32l23x_fwdgt.c94 uint32_t flag_status = RESET; in fwdgt_prescaler_value_config()
102 } while((--timeout > (uint32_t)0) && (RESET != flag_status)); in fwdgt_prescaler_value_config()
104 if(RESET != flag_status) { in fwdgt_prescaler_value_config()
123 uint32_t flag_status = RESET; in fwdgt_reload_value_config()
131 } while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); in fwdgt_reload_value_config()
133 if((uint32_t)RESET != flag_status) { in fwdgt_reload_value_config()
151 uint32_t flag_status = RESET; in fwdgt_window_value_config()
159 } while((--time_index > 0U) && ((uint32_t)RESET != flag_status)); in fwdgt_window_value_config()
161 if((uint32_t)RESET != flag_status) { in fwdgt_window_value_config()
199 uint32_t flag_status = RESET; in fwdgt_config()
[all …]
Dgd32l23x_adc.c81 if(RESET == (ADC_CTL1 & ADC_CTL1_ADCON)) { in adc_enable()
195 if(RESET != (function & ADC_SCAN_MODE)) { in adc_special_function_config()
199 if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO)) { in adc_special_function_config()
203 if(RESET != (function & ADC_CONTINUOUS_MODE)) { in adc_special_function_config()
208 if(RESET != (function & ADC_SCAN_MODE)) { in adc_special_function_config()
212 if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO)) { in adc_special_function_config()
216 if(RESET != (function & ADC_CONTINUOUS_MODE)) { in adc_special_function_config()
237 if(RESET != (function & ADC_TEMP_CHANNEL_SWITCH)) { in adc_channel_16_to_19()
241 if(RESET != (function & ADC_INTERNAL_CHANNEL_SWITCH)) { in adc_channel_16_to_19()
245 if(RESET != (function & ADC_VBAT_CHANNEL_SWITCH)) { in adc_channel_16_to_19()
[all …]
Dgd32l23x_rtc.c57 uint32_t flag_status = RESET; in rtc_deinit()
80 } while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); in rtc_deinit()
82 if((uint32_t)RESET == flag_status) { in rtc_deinit()
203 uint32_t flag_status = RESET; in rtc_init_mode_enter()
207 if((uint32_t)RESET == (RTC_STAT & RTC_STAT_INITF)) { in rtc_init_mode_enter()
213 } while((--time_index > 0x00U) && ((uint32_t)RESET == flag_status)); in rtc_init_mode_enter()
215 if((uint32_t)RESET != flag_status) { in rtc_init_mode_enter()
245 uint32_t flag_status = RESET; in rtc_register_sync_wait()
248 if((uint32_t)RESET == (RTC_CTL & RTC_CTL_BPSHAD)) { in rtc_register_sync_wait()
259 } while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); in rtc_register_sync_wait()
[all …]
Dgd32l23x_ctc.c222 if(RESET != (CTC_STAT & CTC_STAT_REFDIR)) { in ctc_counter_direction_read()
225 return RESET; in ctc_counter_direction_read()
306 if(RESET != (int_flag & CTC_FLAG_MASK)) { in ctc_interrupt_flag_get()
318 return RESET; in ctc_interrupt_flag_get()
338 if(RESET != (int_flag & CTC_FLAG_MASK)) { in ctc_interrupt_flag_clear()
361 if(RESET != (CTC_STAT & flag)) { in ctc_flag_get()
364 return RESET; in ctc_flag_get()
384 if(RESET != (flag & CTC_FLAG_MASK)) { in ctc_flag_clear()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/source/
Dgd32e50x_fwdgt.c94 uint32_t flag_status = RESET; in fwdgt_prescaler_value_config()
102 } while((--timeout > 0U) && (RESET != flag_status)); in fwdgt_prescaler_value_config()
104 if(RESET != flag_status){ in fwdgt_prescaler_value_config()
123 uint32_t flag_status = RESET; in fwdgt_reload_value_config()
131 }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); in fwdgt_reload_value_config()
133 if ((uint32_t)RESET != flag_status){ in fwdgt_reload_value_config()
160 uint32_t flag_status = RESET; in fwdgt_config()
168 }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); in fwdgt_config()
170 if ((uint32_t)RESET != flag_status){ in fwdgt_config()
181 }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); in fwdgt_config()
[all …]
Dgd32e50x_enet.c363 }while((RESET == phy_value) && (timeout < PHY_READ_TO)); in enet_init()
384 }while((RESET == phy_value) && (timeout < (uint32_t)PHY_READ_TO)); in enet_init()
395 if((uint16_t)RESET != (phy_value & PHY_DUPLEX_STATUS)){ in enet_init()
401 if((uint16_t)RESET !=(phy_value & PHY_SPEED_STATUS)){ in enet_init()
425 if(RESET != ((uint32_t)checksum & ENET_CHECKSUMOFFLOAD_ENABLE)){ in enet_init()
440 if(RESET != (enet_initpara.option_enable & (uint32_t)FORWARD_OPTION)){ in enet_init()
461 if(RESET != (enet_initpara.option_enable & (uint32_t)DMABUS_OPTION)){ in enet_init()
473 if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_MAXBURST_OPTION)){ in enet_init()
484 if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_ARBITRATION_OPTION)){ in enet_init()
495 if(RESET != (enet_initpara.option_enable & (uint32_t)STORE_OPTION)){ in enet_init()
[all …]
Dgd32e50x_ctc.c225 if(RESET != (CTC_STAT & CTC_STAT_REFDIR)){ in ctc_counter_direction_read()
228 return RESET; in ctc_counter_direction_read()
274 if(RESET != (CTC_STAT & flag)){ in ctc_flag_get()
277 return RESET; in ctc_flag_get()
297 if(RESET != (flag & CTC_FLAG_MASK)){ in ctc_flag_clear()
355 if(RESET != (int_flag & CTC_FLAG_MASK)){ in ctc_interrupt_flag_get()
367 return RESET; in ctc_interrupt_flag_get()
387 if(RESET != (int_flag & CTC_FLAG_MASK)){ in ctc_interrupt_flag_clear()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/standard_peripheral/source/
Dgd32e10x_fwdgt.c90 uint32_t flag_status = RESET; in fwdgt_prescaler_value_config()
98 } while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); in fwdgt_prescaler_value_config()
100 if((uint32_t)RESET != flag_status) { in fwdgt_prescaler_value_config()
119 uint32_t flag_status = RESET; in fwdgt_reload_value_config()
127 } while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); in fwdgt_reload_value_config()
129 if((uint32_t)RESET != flag_status) { in fwdgt_reload_value_config()
167 uint32_t flag_status = RESET; in fwdgt_config()
175 } while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); in fwdgt_config()
177 if((uint32_t)RESET != flag_status) { in fwdgt_config()
188 } while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); in fwdgt_config()
[all …]
Dgd32e10x_ctc.c224 if(RESET != (CTC_STAT & CTC_STAT_REFDIR)){ in ctc_counter_direction_read()
227 return RESET; in ctc_counter_direction_read()
308 if(RESET != (interrupt & CTC_FLAG_MASK)){ in ctc_interrupt_flag_get()
320 return RESET; in ctc_interrupt_flag_get()
340 if(RESET != (interrupt & CTC_FLAG_MASK)){ in ctc_interrupt_flag_clear()
363 if(RESET != (CTC_STAT & flag)){ in ctc_flag_get()
366 return RESET; in ctc_flag_get()
386 if(RESET != (flag & CTC_FLAG_MASK)){ in ctc_flag_clear()
Dgd32e10x_rcu.c696 if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))){ in rcu_flag_get()
699 return RESET; in rcu_flag_get()
733 if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))){ in rcu_interrupt_flag_get()
736 return RESET; in rcu_interrupt_flag_get()
842 FlagStatus osci_stat = RESET; in rcu_osci_stab_wait()
847 while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)){ in rcu_osci_stab_wait()
853 if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)){ in rcu_osci_stab_wait()
860 while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)){ in rcu_osci_stab_wait()
866 if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)){ in rcu_osci_stab_wait()
873 while((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)){ in rcu_osci_stab_wait()
[all …]
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f3x0/standard_peripheral/source/
Dgd32f3x0_fwdgt.c81 uint32_t flag_status = RESET; in fwdgt_window_value_config()
89 }while((--time_index > 0U) && (RESET != flag_status)); in fwdgt_window_value_config()
91 if (RESET != flag_status){ in fwdgt_window_value_config()
130 uint32_t flag_status = RESET; in fwdgt_config()
138 }while((--timeout > 0U) && (RESET != flag_status)); in fwdgt_config()
140 if (RESET != flag_status){ in fwdgt_config()
151 }while((--timeout > 0U) && (RESET != flag_status)); in fwdgt_config()
153 if (RESET != flag_status){ in fwdgt_config()
180 return RESET; in fwdgt_flag_get()
Dgd32f3x0_adc.c59 if(RESET == (ADC_CTL1 & ADC_CTL1_ADCON)){ in adc_enable()
213 if(RESET != (function & ADC_SCAN_MODE)){ in adc_special_function_config()
217 if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO)){ in adc_special_function_config()
221 if(RESET != (function & ADC_CONTINUOUS_MODE)){ in adc_special_function_config()
226 if(RESET != (function & ADC_SCAN_MODE)){ in adc_special_function_config()
230 if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO)){ in adc_special_function_config()
234 if(RESET != (function & ADC_CONTINUOUS_MODE)){ in adc_special_function_config()
435 if(RESET != (channel_group & ADC_REGULAR_CHANNEL)){ in adc_external_trigger_config()
439 if(RESET != (channel_group & ADC_INSERTED_CHANNEL)){ in adc_external_trigger_config()
444 if(RESET != (channel_group & ADC_REGULAR_CHANNEL)){ in adc_external_trigger_config()
[all …]
Dgd32f3x0_rtc.c166 uint32_t flag_status = RESET; in rtc_init_mode_enter()
170 if(RESET == (RTC_STAT & RTC_STAT_INITF)){ in rtc_init_mode_enter()
176 }while((--time_index > 0x00U) && (RESET == flag_status)); in rtc_init_mode_enter()
178 if(RESET != flag_status){ in rtc_init_mode_enter()
208 uint32_t flag_status = RESET; in rtc_register_sync_wait()
211 if(RESET == (RTC_CTL & RTC_CTL_BPSHAD)){ in rtc_register_sync_wait()
222 }while((--time_index > 0x00U) && (RESET == flag_status)); in rtc_register_sync_wait()
224 if(RESET != flag_status){ in rtc_register_sync_wait()
448 uint32_t flag_status = RESET; in rtc_alarm_disable()
460 }while((--time_index > 0x00U) && (RESET == flag_status)); in rtc_alarm_disable()
[all …]
Dgd32f3x0_tsi.c92 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){ in tsi_init()
154 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){ in tsi_sample_pin_enable()
169 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){ in tsi_sample_pin_disable()
208 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){ in tsi_sofeware_mode_config()
246 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){ in tsi_hardware_mode_config()
269 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){ in tsi_pin_mode_config()
301 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){ in tsi_extend_charge_config()
373 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){ in tsi_plus_config()
419 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){ in tsi_max_number_config()
540 return RESET; in tsi_interrupt_flag_get()
[all …]
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f4xx/standard_peripheral/source/
Dgd32f4xx_enet.c364 } while((RESET == phy_value) && (timeout < PHY_READ_TO)); in enet_init()
385 } while((RESET == phy_value) && (timeout < (uint32_t)PHY_READ_TO)); in enet_init()
396 if((uint16_t)RESET != (phy_value & PHY_DUPLEX_STATUS)) { in enet_init()
402 if((uint16_t)RESET != (phy_value & PHY_SPEED_STATUS)) { in enet_init()
427 if(RESET != ((uint32_t)checksum & ENET_CHECKSUMOFFLOAD_ENABLE)) { in enet_init()
442 if(RESET != (enet_initpara.option_enable & (uint32_t)FORWARD_OPTION)) { in enet_init()
463 if(RESET != (enet_initpara.option_enable & (uint32_t)DMABUS_OPTION)) { in enet_init()
475 if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_MAXBURST_OPTION)) { in enet_init()
486 if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_ARBITRATION_OPTION)) { in enet_init()
497 if(RESET != (enet_initpara.option_enable & (uint32_t)STORE_OPTION)) { in enet_init()
[all …]
Dgd32f4xx_fwdgt.c107 uint32_t flag_status = RESET; in fwdgt_config()
115 }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); in fwdgt_config()
117 if ((uint32_t)RESET != flag_status){ in fwdgt_config()
128 }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); in fwdgt_config()
130 if ((uint32_t)RESET != flag_status){ in fwdgt_config()
153 if(RESET != (FWDGT_STAT & flag)){ in fwdgt_flag_get()
157 return RESET; in fwdgt_flag_get()
Dgd32f4xx_rtc.c59 uint32_t flag_status = RESET; in rtc_deinit()
83 } while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); in rtc_deinit()
85 if((uint32_t)RESET == flag_status) { in rtc_deinit()
187 uint32_t flag_status = RESET; in rtc_init_mode_enter()
191 if((uint32_t)RESET == (RTC_STAT & RTC_STAT_INITF)) { in rtc_init_mode_enter()
197 } while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); in rtc_init_mode_enter()
199 if((uint32_t)RESET != flag_status) { in rtc_init_mode_enter()
229 uint32_t flag_status = RESET; in rtc_register_sync_wait()
232 if((uint32_t)RESET == (RTC_CTL & RTC_CTL_BPSHAD)) { in rtc_register_sync_wait()
243 } while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); in rtc_register_sync_wait()
[all …]
Dgd32f4xx_rcu.c766 if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))) { in rcu_flag_get()
769 return RESET; in rcu_flag_get()
803 if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))) { in rcu_interrupt_flag_get()
806 return RESET; in rcu_interrupt_flag_get()
911 FlagStatus osci_stat = RESET; in rcu_osci_stab_wait()
916 while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)) { in rcu_osci_stab_wait()
922 if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)) { in rcu_osci_stab_wait()
928 while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)) { in rcu_osci_stab_wait()
934 if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)) { in rcu_osci_stab_wait()
940 while((RESET == osci_stat) && (IRC16M_STARTUP_TIMEOUT != stb_cnt)) { in rcu_osci_stab_wait()
[all …]
Dgd32f4xx_ctc.c239 if(RESET != (CTC_STAT & CTC_STAT_REFDIR)) { in ctc_counter_direction_read()
242 return RESET; in ctc_counter_direction_read()
323 if(RESET != (int_flag & CTC_FLAG_MASK)) { in ctc_interrupt_flag_get()
335 return RESET; in ctc_interrupt_flag_get()
355 if(RESET != (int_flag & CTC_FLAG_MASK)) { in ctc_interrupt_flag_clear()
378 if(RESET != (CTC_STAT & flag)) { in ctc_flag_get()
381 return RESET; in ctc_flag_get()
401 if(RESET != (flag & CTC_FLAG_MASK)) { in ctc_flag_clear()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/standard_peripheral/source/
Dgd32f403_fwdgt.c106 uint32_t flag_status = RESET; in fwdgt_config()
114 }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); in fwdgt_config()
116 if ((uint32_t)RESET != flag_status){ in fwdgt_config()
127 }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); in fwdgt_config()
129 if ((uint32_t)RESET != flag_status){ in fwdgt_config()
152 if(RESET != (FWDGT_STAT & flag)){ in fwdgt_flag_get()
156 return RESET; in fwdgt_flag_get()
Dgd32f403_ctc.c224 if(RESET != (CTC_STAT & CTC_STAT_REFDIR)){ in ctc_counter_direction_read()
227 return RESET; in ctc_counter_direction_read()
308 if(RESET != (int_flag & CTC_FLAG_MASK)){ in ctc_interrupt_flag_get()
320 return RESET; in ctc_interrupt_flag_get()
340 if(RESET != (int_flag & CTC_FLAG_MASK)){ in ctc_interrupt_flag_clear()
363 if(RESET != (CTC_STAT & flag)){ in ctc_flag_get()
366 return RESET; in ctc_flag_get()
386 if(RESET != (flag & CTC_FLAG_MASK)){ in ctc_flag_clear()
Dgd32f403_rcu.c693 if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))){ in rcu_flag_get()
696 return RESET; in rcu_flag_get()
730 if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))){ in rcu_interrupt_flag_get()
733 return RESET; in rcu_interrupt_flag_get()
839 FlagStatus osci_stat = RESET; in rcu_osci_stab_wait()
844 while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)){ in rcu_osci_stab_wait()
850 if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)){ in rcu_osci_stab_wait()
857 while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)){ in rcu_osci_stab_wait()
863 if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)){ in rcu_osci_stab_wait()
870 while((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)){ in rcu_osci_stab_wait()
[all …]
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32vf103/standard_peripheral/source/
Dgd32vf103_fwdgt.c105 uint32_t flag_status = RESET; in fwdgt_config()
112 }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); in fwdgt_config()
114 if((uint32_t)RESET != flag_status){ in fwdgt_config()
124 }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); in fwdgt_config()
126 if((uint32_t)RESET != flag_status){ in fwdgt_config()
151 return RESET; in fwdgt_flag_get()
Dgd32vf103_rcu.c607 if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))){ in rcu_flag_get()
610 return RESET; in rcu_flag_get()
643 if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))){ in rcu_interrupt_flag_get()
646 return RESET; in rcu_interrupt_flag_get()
726 FlagStatus osci_stat = RESET; in rcu_osci_stab_wait()
731 while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)){ in rcu_osci_stab_wait()
737 if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)){ in rcu_osci_stab_wait()
744 while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)){ in rcu_osci_stab_wait()
750 if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)){ in rcu_osci_stab_wait()
757 while((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)){ in rcu_osci_stab_wait()
[all …]
Dgd32vf103_rtc.c108 while(RESET == (RTC_CTL & RTC_CTL_LWOFF)){ in rtc_lwoff_wait()
123 while(RESET == (RTC_CTL & RTC_CTL_RSYNF)){ in rtc_register_sync_wait()
187 if(RESET != (RTC_CTL & flag)){ in rtc_flag_get()
190 return RESET; in rtc_flag_get()
223 if(RESET != (RTC_CTL & flag)){ in rtc_interrupt_flag_get()
226 return RESET; in rtc_interrupt_flag_get()

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