RCU_CTL_PLL2EN (reference) in projects: hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0

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Searched refs:RCU_CTL_PLL2EN (Results 1 – 12 of 12) sorted by relevance

/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32vf103/riscv/source/
D	system_gd32vf103.c	`173 RCU_CTL &= ~(RCU_CTL_PLLEN \| RCU_CTL_PLL1EN \| RCU_CTL_PLL2EN \| RCU_CTL_CKMEN \| RCU_CTL_HXTALEN); in SystemInit() 795 RCU_CTL \|= RCU_CTL_PLL2EN; in system_clock_108m_hxtal() 810 RCU_CTL \|= RCU_CTL_PLL2EN; in system_clock_108m_hxtal()`
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32vf103/standard_peripheral/source/
D	gd32vf103_rcu.c	`61 RCU_CTL &= ~(RCU_CTL_PLL1EN \| RCU_CTL_PLL2EN); in rcu_deinit()`
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/cmsis/gd/gd32e10x/source/
D	system_gd32e10x.c	`134 RCU_CTL &= ~(RCU_CTL_PLLEN \|RCU_CTL_PLL1EN \| RCU_CTL_PLL2EN \| RCU_CTL_CKMEN \| RCU_CTL_HXTALEN); in SystemInit()`
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/standard_peripheral/source/
D	gd32e10x_rcu.c	`89 RCU_CTL &= ~(RCU_CTL_PLL1EN \| RCU_CTL_PLL2EN); in rcu_deinit()`
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/standard_peripheral/source/
D	gd32f403_rcu.c	`79 RCU_CTL &= ~(RCU_CTL_PLL1EN \| RCU_CTL_PLL2EN \| RCU_CTL_HXTALBPS); in rcu_deinit()`
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/source/
D	gd32e50x_rcu.c	`80 RCU_CTL &= ~(RCU_CTL_PLL1EN \| RCU_CTL_PLL2EN); in rcu_deinit()`
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/cmsis/gd/gd32e50x/source/
D	system_gd32e50x.c	`126 RCU_CTL &= ~(RCU_CTL_PLLEN \|RCU_CTL_PLL1EN \| RCU_CTL_PLL2EN \| RCU_CTL_CKMEN \| RCU_CTL_HXTALEN); in SystemInit()`
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/cmsis/gd/gd32f403/source/
D	system_gd32f403.c	`141 RCU_CTL &= ~(RCU_CTL_PLLEN \|RCU_CTL_PLL1EN \| RCU_CTL_PLL2EN \| RCU_CTL_CKMEN \| RCU_CTL_HXTALEN); in SystemInit()`
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32vf103/standard_peripheral/include/
D	gd32vf103_rcu.h	`75 #define RCU_CTL_PLL2EN BIT(28) /!< PLL2 enable / macro`
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/standard_peripheral/include/
D	gd32e10x_rcu.h	`79 #define RCU_CTL_PLL2EN BIT(28) /!< PLL2 enable / macro`
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/standard_peripheral/include/
D	gd32f403_rcu.h	`78 #define RCU_CTL_PLL2EN BIT(28) /!< PLL2 enable / macro`
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/include/
D	gd32e50x_rcu.h	`136 #define RCU_CTL_PLL2EN BIT(28) /!< PLL2 enable / macro`

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