RCU_CTL_PLL1STB (reference) in projects: hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0

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Searched refs:RCU_CTL_PLL1STB (Results 1 – 8 of 8) sorted by relevance

/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32vf103/riscv/source/
D	system_gd32vf103.c	354 while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ in system_clock_24m_hxtal() 425 while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ in system_clock_36m_hxtal() 497 while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ in system_clock_48m_hxtal() 571 while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ in system_clock_56m_hxtal() 644 while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ in system_clock_72m_hxtal() 715 while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ in system_clock_96m_hxtal() 791 while(0U == (RCU_CTL & RCU_CTL_PLL1STB)){ in system_clock_108m_hxtal() 806 while(0U == (RCU_CTL & RCU_CTL_PLL1STB)){ in system_clock_108m_hxtal()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/cmsis/gd/gd32e50x/source/
D	system_gd32e50x.c	601 while((RCU_CTL & RCU_CTL_PLL1STB) == 0U){ in system_clock_72m_hxtal() 616 while((RCU_CTL & RCU_CTL_PLL1STB) == 0U){ in system_clock_72m_hxtal() 705 while((RCU_CTL & RCU_CTL_PLL1STB) == 0U){ in system_clock_120m_hxtal() 720 while((RCU_CTL & RCU_CTL_PLL1STB) == 0U){ in system_clock_120m_hxtal() 810 while((RCU_CTL & RCU_CTL_PLL1STB) == 0U){ in system_clock_168m_hxtal() 825 while((RCU_CTL & RCU_CTL_PLL1STB) == 0U){ in system_clock_168m_hxtal() 915 while((RCU_CTL & RCU_CTL_PLL1STB) == 0U){ in system_clock_180m_hxtal() 930 while((RCU_CTL & RCU_CTL_PLL1STB) == 0U){ in system_clock_180m_hxtal()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/cmsis/gd/gd32e10x/source/
D	system_gd32e10x.c	`552 while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ in system_clock_48m_hxtal() 623 while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ in system_clock_72m_hxtal() 694 while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ in system_clock_108m_hxtal() 766 while((RCU_CTL & RCU_CTL_PLL1STB) == 0U){ in system_clock_120m_hxtal()`
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/cmsis/gd/gd32f403/source/
D	system_gd32f403.c	`748 while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ in system_clock_48m_hxtal() 825 while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ in system_clock_72m_hxtal() 903 while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ in system_clock_108m_hxtal() 981 while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ in system_clock_120m_hxtal() 1059 while(0U == (RCU_CTL & RCU_CTL_PLL1STB)){ in system_clock_168m_hxtal()`
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32vf103/standard_peripheral/include/
D	gd32vf103_rcu.h	`74 #define RCU_CTL_PLL1STB BIT(27) /*!< PLL1 clock stabilization fla… macro`
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/standard_peripheral/include/
D	gd32e10x_rcu.h	`78 #define RCU_CTL_PLL1STB BIT(27) /*!< PLL1 clock stabilization fla… macro`
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/standard_peripheral/include/
D	gd32f403_rcu.h	`77 #define RCU_CTL_PLL1STB BIT(27) /*!< PLL1 clock stabilization fla… macro`
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/include/
D	gd32e50x_rcu.h	`135 #define RCU_CTL_PLL1STB BIT(27) /*!< PLL1 clock stabilization fla… macro`

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