Searched refs:RCU_ADC1RST (Results 1 – 10 of 10) sorted by relevance
| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/standard_peripheral/source/ |
| D | gd32f403_adc.c | 54 rcu_periph_reset_enable(RCU_ADC1RST); in adc_deinit()
55 rcu_periph_reset_disable(RCU_ADC1RST); in adc_deinit()
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32a50x/standard_peripheral/source/ |
| D | gd32a50x_adc.c | 51 rcu_periph_reset_enable(RCU_ADC1RST); in adc_deinit()
52 rcu_periph_reset_disable(RCU_ADC1RST); in adc_deinit()
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/standard_peripheral/source/ |
| D | gd32e10x_adc.c | 78 rcu_periph_reset_enable(RCU_ADC1RST); in adc_deinit()
79 rcu_periph_reset_disable(RCU_ADC1RST); in adc_deinit()
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32vf103/standard_peripheral/source/ |
| D | gd32vf103_adc.c | 76 rcu_periph_reset_enable(RCU_ADC1RST); in adc_deinit()
77 rcu_periph_reset_disable(RCU_ADC1RST); in adc_deinit()
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/source/ |
| D | gd32e50x_adc.c | 53 rcu_periph_reset_enable(RCU_ADC1RST); in adc_deinit()
54 rcu_periph_reset_disable(RCU_ADC1RST); in adc_deinit()
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32a50x/standard_peripheral/include/ |
| D | gd32a50x_rcu.h | 342 … RCU_ADC1RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 10U), /*!< ADC1 clock reset */ enumerator
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32vf103/standard_peripheral/include/ |
| D | gd32vf103_rcu.h | 345 RCU_ADC1RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 10U), /*!< ADC1 clock reset */ enumerator
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/standard_peripheral/include/ |
| D | gd32e10x_rcu.h | 406 RCU_ADC1RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 10U), /*!< ADC1 clock reset */ enumerator
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/standard_peripheral/include/ |
| D | gd32f403_rcu.h | 413 RCU_ADC1RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 10U), /*!< ADC1 clock reset */ enumerator
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/include/ |
| D | gd32e50x_rcu.h | 689 RCU_ADC1RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 10U), /*!< ADC1 clock reset */ enumerator
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