1 /*! 2 \file gd32l23x_pmu.h 3 \brief definitions for the PMU 4 5 \version 2021-08-04, V1.0.0, firmware for GD32L23x 6 */ 7 8 /* 9 Copyright (c) 2021, GigaDevice Semiconductor Inc. 10 11 Redistribution and use in source and binary forms, with or without modification, 12 are permitted provided that the following conditions are met: 13 14 1. Redistributions of source code must retain the above copyright notice, this 15 list of conditions and the following disclaimer. 16 2. Redistributions in binary form must reproduce the above copyright notice, 17 this list of conditions and the following disclaimer in the documentation 18 and/or other materials provided with the distribution. 19 3. Neither the name of the copyright holder nor the names of its contributors 20 may be used to endorse or promote products derived from this software without 21 specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 32 OF SUCH DAMAGE. 33 */ 34 35 #ifndef GD32L23X_PMU_H 36 #define GD32L23X_PMU_H 37 38 #include "gd32l23x.h" 39 40 /* PMU definitions */ 41 #define PMU PMU_BASE /*!< PMU base address */ 42 43 /* registers definitions */ 44 #define PMU_CTL0 REG32((PMU) + 0x00000000U) /*!< PMU control register 0 */ 45 #define PMU_CS REG32((PMU) + 0x00000004U) /*!< PMU control and status register */ 46 #define PMU_CTL1 REG32((PMU) + 0x00000008U) /*!< PMU control register 1 */ 47 #define PMU_STAT REG32((PMU) + 0x0000000CU) /*!< PMU status register */ 48 #define PMU_PAR REG32((PMU) + 0x00000010U) /*!< PMU parameter register */ 49 50 /* bits definitions */ 51 /* PMU_CTL0 */ 52 #define PMU_CTL0_LPMOD BITS(0,1) /*!< select the low-power mode to enter */ 53 #define PMU_CTL0_WURST BIT(2) /*!< wakeup flag reset */ 54 #define PMU_CTL0_STBRST BIT(3) /*!< standby flag reset */ 55 #define PMU_CTL0_LVDEN BIT(4) /*!< low voltage detector enable */ 56 #define PMU_CTL0_LVDT BITS(5,7) /*!< low voltage detector threshold */ 57 #define PMU_CTL0_BKPWEN BIT(8) /*!< backup domain write enable */ 58 #define PMU_CTL0_LDNPDSP BIT(10) /*!< low-driver mode when use normal power LDO in Deep-sleep mode */ 59 #define PMU_CTL0_LDNP BIT(11) /*!< low-driver mode when use normal power LDO in Run/Sleep mode */ 60 #define PMU_CTL0_VCEN BIT(12) /*!< VBAT battery charging enable */ 61 #define PMU_CTL0_VCRSEL BIT(13) /*!< VBAT battery charging resistor selection */ 62 #define PMU_CTL0_LDOVS BITS(14,15) /*!< LDO output voltage select */ 63 64 /* PMU_CS */ 65 #define PMU_CS_WUF BIT(0) /*!< wakeup flag */ 66 #define PMU_CS_STBF BIT(1) /*!< standby flag */ 67 #define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */ 68 #define PMU_CS_WUPEN0 BIT(8) /*!< wakeup pin0 enable */ 69 #define PMU_CS_WUPEN1 BIT(9) /*!< wakeup pin1 enable */ 70 #define PMU_CS_WUPEN2 BIT(10) /*!< wakeup pin2 enable */ 71 #define PMU_CS_WUPEN3 BIT(11) /*!< wakeup pin3 enable */ 72 #define PMU_CS_WUPEN4 BIT(12) /*!< wakeup pin4 enable */ 73 #define PMU_CS_LDOVSRF BIT(14) /*!< LDO voltage select ready flag */ 74 #define PMU_CS_NPRDY BIT(16) /*!< normal-power LDO ready flag */ 75 #define PMU_CS_LPRDY BIT(17) /*!< low-power LDO ready flag */ 76 77 /* PMU_CTL1 */ 78 #define PMU_CTL1_SRAM1PSLEEP BIT(0) /*!< SRAM1 go to power-off */ 79 #define PMU_CTL1_SRAM1PWAKE BIT(1) /*!< SRAM1 wakeup */ 80 #define PMU_CTL1_CORE1SLEEP BIT(4) /*!< COREOFF1 domain go to power-off */ 81 #define PMU_CTL1_CORE1WAKE BIT(5) /*!< COREOFF1 domain wakeup */ 82 #define PMU_CTL1_NRRD2 BIT(16) /*!< no retention register in Deep-sleep 2 mode */ 83 #define PMU_CTL1_SRAM1PD2 BIT(17) /*!< power state of SRAM1 when enters Deep-sleep 2 mode */ 84 85 /* PMU_STAT */ 86 #define PMU_STAT_DPF2 BIT(1) /*!< Deep-sleep 2 mode status, set by hardware when enter Deep-sleep 2 mode. */ 87 #define PMU_STAT_SRAM1PS_SLEEP BIT(2) /*!< SRAM1 is in sleep state */ 88 #define PMU_STAT_SRAM1PS_ACTIVE BIT(3) /*!< SRAM1 is in active state */ 89 #define PMU_STAT_CORE1PS_SLEEP BIT(4) /*!< COREOFF1 domain is in sleep state */ 90 #define PMU_STAT_CORE1PS_ACTIVE BIT(5) /*!< COREOFF1 domain is in active state */ 91 92 /* PMU_PAR */ 93 #define PMU_PAR_TWK_CORE0 BITS(0,7) /*!< wakeup time of power switch of COREOFF0 domain */ 94 #define PMU_PAR_TWK_SRAM1 BITS(8,15) /*!< wakeup time of power switch of SRAM1 domain */ 95 #define PMU_PAR_TSW_IRC16MCNT BITS(16,20) /*!< wait the IRC16M COUNTER and then set Deep-sleep signal */ 96 #define PMU_PAR_TWK_CORE1 BITS(21,28) /*!< wakeup time of power switch of COREOFF1 domain */ 97 #define PMU_PAR_TWKCORE1EN BIT(29) /*!< use software value when wake up COREOFF1 or not */ 98 #define PMU_PAR_TWKSRAM1EN BIT(30) /*!< use software value when wake up SRAM1 power domain or not */ 99 #define PMU_PAR_TWKEN BIT(31) /*!< use software value when wake up Deep-sleep or not */ 100 101 /* constants definitions */ 102 /* PMU low voltage detector threshold definitions */ 103 #define CTL0_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5)) 104 #define PMU_LVDT_0 CTL0_LVDT(0) /*!< voltage threshold is 2.1V */ 105 #define PMU_LVDT_1 CTL0_LVDT(1) /*!< voltage threshold is 2.3V */ 106 #define PMU_LVDT_2 CTL0_LVDT(2) /*!< voltage threshold is 2.4V */ 107 #define PMU_LVDT_3 CTL0_LVDT(3) /*!< voltage threshold is 2.6V */ 108 #define PMU_LVDT_4 CTL0_LVDT(4) /*!< voltage threshold is 2.7V */ 109 #define PMU_LVDT_5 CTL0_LVDT(5) /*!< voltage threshold is 2.9V */ 110 #define PMU_LVDT_6 CTL0_LVDT(6) /*!< voltage threshold is 3.0V */ 111 #define PMU_LVDT_7 CTL0_LVDT(7) /*!< input analog voltage on PB7 (compared with 0.8V) */ 112 113 /* PMU LDO output voltage select definitions */ 114 #define CTL0_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14)) 115 #define PMU_LDOVS_LOW CTL0_LDOVS(0) /*!< LDO output voltage low mode */ 116 #define PMU_LDOVS_HIGH CTL0_LDOVS(2) /*!< LDO output voltage high mode */ 117 118 /* PMU low-driver mode when use normal power LDO in Deep-sleep mode */ 119 #define CTL0_LDNPDSP(regval) (BIT(10)&((uint32_t)(regval)<<10)) 120 #define PMU_LDNPDSP_NORMALDRIVE CTL0_LDNPDSP(0) /*!< normal driver when use normal power LDO in Deep-sleep mode */ 121 #define PMU_LDNPDSP_LOWDRIVE CTL0_LDNPDSP(1) /*!< low-driver mode enabled when use normal power LDO in Deep-sleep mode */ 122 123 /* PMU low-driver mode when use normal power LDO in Run/Sleep mode */ 124 #define CTL0_LDNP(regval) (BIT(11)&((uint32_t)(regval)<<11)) 125 #define PMU_LDNP_NORMALDRIVE CTL0_LDNP(0) /*!< normal driver when use normal power LDO in run/sleep mode */ 126 #define PMU_LDNP_LOWDRIVE CTL0_LDNP(1) /*!< low-driver mode enabled when use normal power LDO in run/sleep mode */ 127 128 /* PMU VBAT battery charging resistor selection */ 129 #define CTL0_VCRSEL(regval) (BIT(13)&((uint32_t)(regval)<<13)) 130 #define PMU_VCRSEL_5K CTL0_VCRSEL(0) /*!< 5 kOhms resistor is selected for charing VBAT battery */ 131 #define PMU_VCRSEL_1P5K CTL0_VCRSEL(1) /*!< 1.5 kOhms resistor is selected for charing VBAT battery */ 132 133 /* select the low-power mode to enter */ 134 #define CTL0_LPMOD(regval) (BITS(0,1)&((uint32_t)(regval)<<0)) 135 #define PMU_DEEPSLEEP CTL0_LPMOD(0) /*!< Deep-sleep mode */ 136 #define PMU_DEEPSLEEP1 CTL0_LPMOD(1) /*!< Deep-sleep mode 1 */ 137 #define PMU_DEEPSLEEP2 CTL0_LPMOD(2) /*!< Deep-sleep mode 2 */ 138 #define PMU_STANDBY CTL0_LPMOD(3) /*!< standby mode */ 139 140 /* power state of SRAM1 when enters Deep-sleep2 mode */ 141 #define CTL1_SRAM1PD2(regval) (BIT(17)&((uint32_t)(regval)<<17)) 142 #define PMU_SRAM1_POWER_OFF CTL1_SRAM1PD2(0) /*!< SRAM1 power-off */ 143 #define PMU_SRAM1_POWER_REMAIN CTL1_SRAM1PD2(1) /*!< SRAM1 power same as Run/Run1/Run2 mode */ 144 145 /* PMU flag definitions */ 146 #define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */ 147 #define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */ 148 #define PMU_FLAG_LVD PMU_CS_LVDF /*!< lvd flag status */ 149 #define PMU_FLAG_LDOVSRF PMU_CS_LDOVSRF /*!< LDO voltage select ready flag */ 150 #define PMU_FLAG_NPRDY PMU_CS_NPRDY /*!< normal-power LDO ready flag */ 151 #define PMU_FLAG_LPRDY PMU_CS_LPRDY /*!< low-power LDO ready flag */ 152 #define PMU_FLAG_SRAM1_SLEEP (BIT(31) | PMU_STAT_SRAM1PS_SLEEP) /*!< SRAM1 is in sleep state flag */ 153 #define PMU_FLAG_SRAM1_ACTIVE (BIT(31) | PMU_STAT_SRAM1PS_ACTIVE) /*!< SRAM1 is in active state flag */ 154 #define PMU_FLAG_CORE1_SLEEP (BIT(31) | PMU_STAT_CORE1PS_SLEEP) /*!< COREOFF1 domain is in sleep state flag */ 155 #define PMU_FLAG_CORE1_ACTIVE (BIT(31) | PMU_STAT_CORE1PS_ACTIVE) /*!< COREOFF1 domain is in active state flag */ 156 #define PMU_FLAG_DEEPSLEEP_2 (BIT(31) | PMU_STAT_DPF2) /*!< Deep-sleep 2 mode status flag */ 157 158 /* PMU wakeup pin definitions */ 159 #define PMU_WAKEUP_PIN0 PMU_CS_WUPEN0 /*!< WKUP Pin 0 (PA0) */ 160 #define PMU_WAKEUP_PIN1 PMU_CS_WUPEN1 /*!< WKUP Pin 1 (PC13) */ 161 #define PMU_WAKEUP_PIN2 PMU_CS_WUPEN2 /*!< WKUP Pin 2 (PA2) */ 162 #define PMU_WAKEUP_PIN3 PMU_CS_WUPEN3 /*!< WKUP Pin 3 (PB2) */ 163 #define PMU_WAKEUP_PIN4 PMU_CS_WUPEN4 /*!< WKUP Pin 4 (PC6) */ 164 165 /* PMU SRAM1 and COREOFF1 power control */ 166 #define PMU_SRAM1_SLEEP PMU_CTL1_SRAM1PSLEEP /*!< SRAM1 go to power-off */ 167 #define PMU_SRAM1_WAKE PMU_CTL1_SRAM1PWAKE /*!< SRAM1 wakeup */ 168 #define PMU_CORE1_SLEEP PMU_CTL1_CORE1SLEEP /*!< COREOFF1 domain go to power-off */ 169 #define PMU_CORE1_WAKE PMU_CTL1_CORE1WAKE /*!< COREOFF1 domain wakeup */ 170 171 /* PMU command constants definitions */ 172 #define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */ 173 #define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */ 174 175 /* function declarations */ 176 /* reset PMU */ 177 void pmu_deinit(void); 178 /* select low voltage detector threshold */ 179 void pmu_lvd_select(uint32_t lvdt_n); 180 /* disable PMU lvd */ 181 void pmu_lvd_disable(void); 182 /* select LDO output voltage */ 183 void pmu_ldo_output_select(uint32_t ldo_output); 184 /* enable VBAT battery charging */ 185 void pmu_vc_enable(void); 186 /* disable VBAT battery charging */ 187 void pmu_vc_disable(void); 188 /* select PMU VBAT battery charging resistor */ 189 void pmu_vcr_select(uint32_t resistor); 190 191 /* configure PMU mode */ 192 /* enable low power in Run/Sleep mode */ 193 void pmu_low_power_enable(void); 194 /* disable low power in Run/Sleep mode */ 195 void pmu_low_power_disable(void); 196 /* PMU work at sleep mode */ 197 void pmu_to_sleepmode(uint32_t lowdrive, uint8_t sleepmodecmd); 198 /* PMU work at Deep-sleep mode */ 199 void pmu_to_deepsleepmode(uint32_t lowdrive, uint8_t deepsleepmodecmd, uint8_t deepsleepmode); 200 /* PMU work at standby mode */ 201 void pmu_to_standbymode(uint8_t standbymodecmd); 202 /* enable wakeup pin */ 203 void pmu_wakeup_pin_enable(uint32_t wakeup_pin); 204 /* disable wakeup pin */ 205 void pmu_wakeup_pin_disable(uint32_t wakeup_pin); 206 /* enable backup domain write */ 207 void pmu_backup_write_enable(void); 208 /* disable backup domain write */ 209 void pmu_backup_write_disable(void); 210 /* configure power state of SRAM1 */ 211 void pmu_sram_power_config(uint32_t state); 212 /* configure power state of COREOFF1 domain */ 213 void pmu_core1_power_config(uint32_t state); 214 /* have retention register in Deep-sleep 2 */ 215 void pmu_deepsleep2_retention_enable(void); 216 /* no retention register in Deep-sleep 2 */ 217 void pmu_deepsleep2_retention_disable(void); 218 /* configure SRAM1 power state when enter Deep-sleep 2 */ 219 void pmu_deepsleep2_sram_power_config(uint32_t state); 220 /* configure IRC16M counter before enter Deep-sleep mode */ 221 void pmu_deepsleep_wait_time_config(uint32_t wait_time); 222 /* use software value signal when wake up COREOFF1 domain */ 223 void pmu_wakeuptime_core1_software_enable(uint32_t wakeup_time); 224 /* use hardware ack signal when wake up COREOFF1 domain */ 225 void pmu_wakeuptime_core1_software_disable(void); 226 /* use software value signal when wake up SRAM1 */ 227 void pmu_wakeuptime_sram_software_enable(uint32_t wakeup_time); 228 /* use hardware ack signal when wake up SRAM1 */ 229 void pmu_wakeuptime_sram_software_disable(void); 230 /* use software value signal when wake up Deep-sleep2 */ 231 void pmu_wakeuptime_deepsleep2_software_enable(uint32_t wakeup_time); 232 /* use hardware ack signal when wake up Deep-sleep2 */ 233 void pmu_wakeuptime_deepsleep2_software_disable(void); 234 235 /* flag functions */ 236 /* get PMU flag status */ 237 FlagStatus pmu_flag_get(uint32_t flag); 238 /* clear PMU flag status */ 239 void pmu_flag_clear(uint32_t flag); 240 241 #endif /* GD32L23X_PMU_H */ 242
