1 /* 2 * Copyright (c) 2021 Teslabs Engineering S.L. 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6 #ifndef DT_BINDINGS_PINCTRL_GD32_AFIO_H_ 7 #define DT_BINDINGS_PINCTRL_GD32_AFIO_H_ 8 9 /** 10 * @name GD32 pin modes 11 * @{ 12 */ 13 14 /** Analog mode */ 15 #define GD32_MODE_ANALOG 0U 16 /** GPIO input */ 17 #define GD32_MODE_GPIO_IN 1U 18 /** Alternate function */ 19 #define GD32_MODE_ALTERNATE 2U 20 21 /** @} */ 22 23 /** 24 * @name GD32 pinmux bit field mask and positions. 25 * @{ 26 */ 27 28 /** Port field mask. */ 29 #define GD32_PORT_MSK 0xFU 30 /** Port field position. */ 31 #define GD32_PORT_POS 0U 32 /** Pin field mask. */ 33 #define GD32_PIN_MSK 0xFU 34 /** Pin field position. */ 35 #define GD32_PIN_POS 4U 36 /** Mode field mask. */ 37 #define GD32_MODE_MSK 0x3U 38 /** Mode field position. */ 39 #define GD32_MODE_POS 8U 40 /** Remap field mask. */ 41 #define GD32_REMAP_MSK 0x3FFU 42 /** Remap field position. */ 43 #define GD32_REMAP_POS 10U 44 45 /** @} */ 46 47 /** No remap available */ 48 #define GD32_NORMP 0U 49 50 /** 51 * Obtain port field from pinmux configuration. 52 * 53 * @param pinmux Pinmux bit field value. 54 */ 55 #define GD32_PORT_GET(pinmux) \ 56 (((pinmux) >> GD32_PORT_POS) & GD32_PORT_MSK) 57 58 /** 59 * Obtain pin field from pinmux configuration. 60 * 61 * @param pinmux Pinmux bit field value. 62 */ 63 #define GD32_PIN_GET(pinmux) \ 64 (((pinmux) >> GD32_PIN_POS) & GD32_PIN_MSK) 65 66 /** 67 * Obtain mode field from pinmux configuration. 68 * 69 * @param pinmux Pinmux bit field value. 70 */ 71 #define GD32_MODE_GET(pinmux) \ 72 (((pinmux) >> GD32_MODE_POS) & GD32_MODE_MSK) 73 74 /** 75 * Obtain pinmux field from pinmux configuration. 76 * 77 * @param pinmux Pinmux bit field value. 78 */ 79 #define GD32_REMAP_GET(pinmux) \ 80 (((pinmux) >> GD32_REMAP_POS) & GD32_REMAP_MSK) 81 82 /** 83 * @brief Remap configuration bit field. 84 * 85 * Fields: 86 * 87 * - 0..3: port 88 * - 4..7: pin 89 * - 8..9: mode 90 * - 10..19: remap 91 * 92 * @param port Port ('A'..'P') 93 * @param pin Pin (0..15) 94 * @param mode Mode (ANALOG, GPIO_IN, ALTERNATE). 95 * @param remap Remap value, see #GD32_REMAP. 96 */ 97 #define GD32_PINMUX_AFIO(port, pin, mode, remap) \ 98 (((((port) - 'A') & GD32_PORT_MSK) << GD32_PORT_POS) | \ 99 (((pin) & GD32_PIN_MSK) << GD32_PIN_POS) | \ 100 (((GD32_MODE_ ## mode) & GD32_MODE_MSK) << GD32_MODE_POS) | \ 101 (((GD32_ ## remap) & GD32_REMAP_MSK) << GD32_REMAP_POS)) 102 103 /** 104 * @name Remap bit field mask and positions. 105 * @{ 106 */ 107 108 /** Register field mask. */ 109 #define GD32_REMAP_REG_MSK 0x1U 110 /** Register field position. */ 111 #define GD32_REMAP_REG_POS 0U 112 /** Position field mask. */ 113 #define GD32_REMAP_POS_MSK 0x1FU 114 /** Position field position. */ 115 #define GD32_REMAP_POS_POS 1U 116 /** Mask field mask. */ 117 #define GD32_REMAP_MSK_MSK 0x3U 118 /** Mask field position. */ 119 #define GD32_REMAP_MSK_POS 6U 120 /** Value field mask. */ 121 #define GD32_REMAP_VAL_MSK 0x3U 122 /** Value field position. */ 123 #define GD32_REMAP_VAL_POS 8U 124 125 /** @} */ 126 127 /** 128 * Obtain register field from remap configuration. 129 * 130 * @param remap Remap bit field value. 131 */ 132 #define GD32_REMAP_REG_GET(remap) \ 133 (((remap) >> GD32_REMAP_REG_POS) & GD32_REMAP_REG_MSK) 134 135 /** 136 * Obtain position field from remap configuration. 137 * 138 * @param remap Remap bit field value. 139 */ 140 #define GD32_REMAP_POS_GET(remap) \ 141 (((remap) >> GD32_REMAP_POS_POS) & GD32_REMAP_POS_MSK) 142 143 /** 144 * Obtain mask field from remap configuration. 145 * 146 * @param remap Remap bit field value. 147 */ 148 #define GD32_REMAP_MSK_GET(remap) \ 149 (((remap) >> GD32_REMAP_MSK_POS) & GD32_REMAP_MSK_MSK) 150 151 /** 152 * Obtain value field from remap configuration. 153 * 154 * @param remap Remap bit field value. 155 */ 156 #define GD32_REMAP_VAL_GET(remap) \ 157 (((remap) >> GD32_REMAP_VAL_POS) & GD32_REMAP_VAL_MSK) 158 159 /** 160 * @brief Remap configuration bit field. 161 * 162 * - 0: reg (0 or 1). 163 * - 1..5: pos (0..31). 164 * - 6..7: msk (0x1, 0x3). 165 * - 8..9: val (0..3). 166 * 167 * @param reg AFIO_PCFx register (0, 1). 168 * @param pos Position within AFIO_PCx. 169 * @param msk Mask for the AFIO_PCx field. 170 * @param val Remap value (0, 1, 2 or 3). 171 */ 172 #define GD32_REMAP(reg, pos, msk, val) \ 173 ((((reg) & GD32_REMAP_REG_MSK) << GD32_REMAP_REG_POS) | \ 174 (((pos) & GD32_REMAP_POS_MSK) << GD32_REMAP_POS_POS) | \ 175 (((msk) & GD32_REMAP_MSK_MSK) << GD32_REMAP_MSK_POS) | \ 176 (((val) & GD32_REMAP_VAL_MSK) << GD32_REMAP_VAL_POS)) 177 178 #endif /* DT_BINDINGS_PINCTRL_GD32_AFIO_H_ */ 179
