1 /*! 2 \file gd32l23x_fmc.h 3 \brief definitions for the FMC 4 5 \version 2021-08-04, V1.0.0, firmware for GD32L23x 6 */ 7 8 /* 9 Copyright (c) 2021, GigaDevice Semiconductor Inc. 10 11 Redistribution and use in source and binary forms, with or without modification, 12 are permitted provided that the following conditions are met: 13 14 1. Redistributions of source code must retain the above copyright notice, this 15 list of conditions and the following disclaimer. 16 2. Redistributions in binary form must reproduce the above copyright notice, 17 this list of conditions and the following disclaimer in the documentation 18 and/or other materials provided with the distribution. 19 3. Neither the name of the copyright holder nor the names of its contributors 20 may be used to endorse or promote products derived from this software without 21 specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 32 OF SUCH DAMAGE. 33 */ 34 35 #ifndef GD32L23X_FMC_H 36 #define GD32L23X_FMC_H 37 38 #include "gd32l23x.h" 39 40 /* FMC and option bytes definition */ 41 #define FMC FMC_BASE /*!< FMC base address */ 42 #define OB OB_BASE /*!< option bytes base address */ 43 44 /* registers definitions */ 45 #define FMC_WS REG32(FMC + 0x00000000U) /*!< FMC wait state register */ 46 #define FMC_KEY REG32(FMC + 0x00000004U) /*!< FMC unlock key register */ 47 #define FMC_OBKEY REG32(FMC + 0x00000008U) /*!< FMC option bytes unlock key register */ 48 #define FMC_STAT REG32(FMC + 0x0000000CU) /*!< FMC status register */ 49 #define FMC_CTL REG32(FMC + 0x00000010U) /*!< FMC control register */ 50 #define FMC_ADDR REG32(FMC + 0x00000014U) /*!< FMC address register */ 51 #define FMC_OBSTAT REG32(FMC + 0x0000001CU) /*!< FMC option bytes status register */ 52 #define FMC_WP REG32(FMC + 0x00000020U) /*!< FMC erase/program protection register */ 53 #define FMC_SLPKEY REG32(FMC + 0x00000024U) /*!< FMC unlock flash sleep/power-down mode key register */ 54 #define FMC_PID REG32(FMC + 0x00000100U) /*!< FMC product ID register */ 55 56 #define OP_BYTE(x) REG32(OB + ((uint32_t)((uint32_t)0x04U * (x)))) /*!< option bytes value */ 57 #define OB_SPC_USER REG32(OB + 0x00000000U) /*!< option bytes security protection value and user value */ 58 #define OB_DATA REG32(OB + 0x00000004U) /*!< option bytes data value */ 59 #define OB_WP0 REG32(OB + 0x00000008U) /*!< option bytes write protection value 0 */ 60 #define OB_WP1 REG32(OB + 0x0000000CU) /*!< option bytes write protection value 1 */ 61 62 /* bits definitions */ 63 /* FMC_WS */ 64 #define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */ 65 #define FMC_WS_PFEN BIT(4) /*!< pre-fetch enable */ 66 #define FMC_WS_LVE BIT(7) /*!< low power enable */ 67 #define FMC_WS_RUN_SLP BIT(13) /*!< flash enter sleep/power-down mode or IDLE mode during MCU run/low-power run mode */ 68 #define FMC_WS_SLEEP_SLP BIT(14) /*!< flash enter sleep mode or power-down mode when MCU enter stop or RUN_SLP bit is set */ 69 70 /* FMC_KEY */ 71 #define FMC_KEY_KEY BITS(0,31) /*!< FMC_CTL unlock key */ 72 73 /* FMC_OBKEY */ 74 #define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key */ 75 76 /* FMC_STAT */ 77 #define FMC_STAT_BUSY BIT(0) /*!< flash busy flag */ 78 #define FMC_STAT_PGERR BIT(2) /*!< flash program error flag */ 79 #define FMC_STAT_PGAERR BIT(3) /*!< flash program alignment error flag */ 80 #define FMC_STAT_WPERR BIT(4) /*!< erase/program protection error flag */ 81 #define FMC_STAT_ENDF BIT(5) /*!< end of operation flag */ 82 #define FMC_STAT_FSTAT BIT(15) /*!< flash status */ 83 84 /* FMC_CTL */ 85 #define FMC_CTL_PG BIT(0) /*!< main flash program command */ 86 #define FMC_CTL_PER BIT(1) /*!< main flash page erase command */ 87 #define FMC_CTL_MER BIT(2) /*!< main flash mass erase command */ 88 #define FMC_CTL_OBPG BIT(4) /*!< option bytes program command */ 89 #define FMC_CTL_OBER BIT(5) /*!< option bytes erase command */ 90 #define FMC_CTL_START BIT(6) /*!< send erase command to FMC */ 91 #define FMC_CTL_LK BIT(7) /*!< FMC_CTL lock */ 92 #define FMC_CTL_FSTPG BIT(8) /*!< main flash fast program command */ 93 #define FMC_CTL_OBWEN BIT(9) /*!< option bytes erase/program enable */ 94 #define FMC_CTL_ERRIE BIT(10) /*!< error interrupt enable */ 95 #define FMC_CTL_ENDIE BIT(12) /*!< end of operation interrupt enable */ 96 97 /* FMC_ADDR */ 98 #define FMC_ADDR_ADDR BITS(0,31) /*!< address of flash to be erased/programmed */ 99 100 /* FMC_OBSTAT */ 101 #define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error */ 102 #define FMC_OBSTAT_SPC BIT(1) /*!< option bytes security protection code */ 103 #define FMC_OBSTAT_USER BITS(2,9) /*!< store USER of option bytes block after system reset */ 104 #define FMC_OBSTAT_DATA BITS(10,25) /*!< store DATA of option bytes block after system reset */ 105 106 /* FMC_WP */ 107 #define FMC_WP_WP BITS(0,31) /*!< store WP of option bytes block after system reset */ 108 109 /* FMC_SLPKEY */ 110 #define FMC_SLPKEY_KEY BITS(0,31) /*!< unlock flash sleep/power-down mode key */ 111 112 /* FMC_PID */ 113 #define FMC_PID_PID BITS(0,31) /*!< product ID */ 114 115 /* constants definitions */ 116 /* fmc state */ 117 typedef enum { 118 FMC_READY, /*!< the operation has been completed */ 119 FMC_BUSY, /*!< the operation is in progress */ 120 FMC_PGERR, /*!< program error */ 121 FMC_PGAERR, /*!< program alignment error */ 122 FMC_WPERR, /*!< erase/program protection error */ 123 FMC_TOERR, /*!< timeout error */ 124 FMC_OB_HSPC, /*!< high security protection */ 125 FMC_SLP, /*!< flash sleep or power-down */ 126 } fmc_state_enum; 127 128 /* FMC/OB unlock key */ 129 #define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< FMC/OB unlock key 0 */ 130 #define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< FMC/OB unlock key 1 */ 131 132 /* SLP unlock key */ 133 #define SLP_UNLOCK_KEY0 ((uint32_t)0x04152637U) /*!< SLP unlock key 0 */ 134 #define SLP_UNLOCK_KEY1 ((uint32_t)0xBCAD9E8FU) /*!< SLP unlock key 1 */ 135 136 /* FMC wait state added */ 137 #define WS_WSCNT(regval) (BITS(0,2) & ((uint32_t)(regval))) 138 #define FMC_WAIT_STATE_0 WS_WSCNT(0) /*!< 0 wait state added */ 139 #define FMC_WAIT_STATE_1 WS_WSCNT(1) /*!< 1 wait state added */ 140 #define FMC_WAIT_STATE_2 WS_WSCNT(2) /*!< 2 wait state added */ 141 #define FMC_WAIT_STATE_3 WS_WSCNT(3) /*!< 3 wait state added */ 142 143 /* FMC power mode state */ 144 #define FMC_FSTAT_IDLE_MODE ((uint32_t)0x00000000U) /*!< flash is in IDLE mode */ 145 #define FMC_FSTAT_SLP_PD_MODE ((uint32_t)0x00000001U) /*!< flash is in sleep mode or power-down mode */ 146 147 /* read protection configuration */ 148 #define FMC_NSPC ((uint8_t)0xA5U) /*!< no security protection */ 149 #define FMC_LSPC ((uint8_t)0xBBU) /*!< low security protection */ 150 #define FMC_HSPC ((uint8_t)0xCCU) /*!< high security protection */ 151 152 /* brownout threshold configuration */ 153 #define OB_BOR_TH_VALUE0 ((uint8_t)0x00U) /*!< brownout threshold level 0 */ 154 #define OB_BOR_TH_VALUE1 ((uint8_t)0x20U) /*!< brownout threshold level 1 */ 155 #define OB_BOR_TH_VALUE2 ((uint8_t)0x40U) /*!< brownout threshold level 2 */ 156 #define OB_BOR_TH_VALUE3 ((uint8_t)0x60U) /*!< brownout threshold level 3 */ 157 #define OB_BOR_TH_VALUE4 ((uint8_t)0x80U) /*!< brownout threshold level 4 */ 158 159 /* option bytes software/hardware free watch dog timer */ 160 #define OB_FWDGT_HW ((uint8_t)0x00U) /*!< hardware free watchdog */ 161 #define OB_FWDGT_SW ((uint8_t)0x01U) /*!< software free watchdog */ 162 163 /* option bytes reset or not entering deep sleep mode */ 164 #define OB_DEEPSLEEP_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering deepsleep mode */ 165 #define OB_DEEPSLEEP_NRST ((uint8_t)0x02U) /*!< no reset when entering deepsleep mode */ 166 167 /* option bytes reset or not entering standby mode */ 168 #define OB_STDBY_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering standby mode */ 169 #define OB_STDBY_NRST ((uint8_t)0x04U) /*!< no reset when entering standby mode */ 170 171 /* option bytes write protection */ 172 #define OB_WP_NONE ((uint32_t)0x00000000U) /*!< disable all erase/program protection */ 173 #define OB_WP_0 ((uint32_t)0x00000001U) /*!< erase/program protection of sector 0 */ 174 #define OB_WP_1 ((uint32_t)0x00000002U) /*!< erase/program protection of sector 1 */ 175 #define OB_WP_2 ((uint32_t)0x00000004U) /*!< erase/program protection of sector 2 */ 176 #define OB_WP_3 ((uint32_t)0x00000008U) /*!< erase/program protection of sector 3 */ 177 #define OB_WP_4 ((uint32_t)0x00000010U) /*!< erase/program protection of sector 4 */ 178 #define OB_WP_5 ((uint32_t)0x00000020U) /*!< erase/program protection of sector 5 */ 179 #define OB_WP_6 ((uint32_t)0x00000040U) /*!< erase/program protection of sector 6 */ 180 #define OB_WP_7 ((uint32_t)0x00000080U) /*!< erase/program protection of sector 7 */ 181 #define OB_WP_8 ((uint32_t)0x00000100U) /*!< erase/program protection of sector 8 */ 182 #define OB_WP_9 ((uint32_t)0x00000200U) /*!< erase/program protection of sector 9 */ 183 #define OB_WP_10 ((uint32_t)0x00000400U) /*!< erase/program protection of sector 10 */ 184 #define OB_WP_11 ((uint32_t)0x00000800U) /*!< erase/program protection of sector 11 */ 185 #define OB_WP_12 ((uint32_t)0x00001000U) /*!< erase/program protection of sector 12 */ 186 #define OB_WP_13 ((uint32_t)0x00002000U) /*!< erase/program protection of sector 13 */ 187 #define OB_WP_14 ((uint32_t)0x00004000U) /*!< erase/program protection of sector 14 */ 188 #define OB_WP_15 ((uint32_t)0x00008000U) /*!< erase/program protection of sector 15 */ 189 #define OB_WP_16 ((uint32_t)0x00010000U) /*!< erase/program protection of sector 16 */ 190 #define OB_WP_17 ((uint32_t)0x00020000U) /*!< erase/program protection of sector 17 */ 191 #define OB_WP_18 ((uint32_t)0x00040000U) /*!< erase/program protection of sector 18 */ 192 #define OB_WP_19 ((uint32_t)0x00080000U) /*!< erase/program protection of sector 19 */ 193 #define OB_WP_20 ((uint32_t)0x00100000U) /*!< erase/program protection of sector 20 */ 194 #define OB_WP_21 ((uint32_t)0x00200000U) /*!< erase/program protection of sector 21 */ 195 #define OB_WP_22 ((uint32_t)0x00400000U) /*!< erase/program protection of sector 22 */ 196 #define OB_WP_23 ((uint32_t)0x00800000U) /*!< erase/program protection of sector 23 */ 197 #define OB_WP_24 ((uint32_t)0x01000000U) /*!< erase/program protection of sector 24 */ 198 #define OB_WP_25 ((uint32_t)0x02000000U) /*!< erase/program protection of sector 25 */ 199 #define OB_WP_26 ((uint32_t)0x04000000U) /*!< erase/program protection of sector 26 */ 200 #define OB_WP_27 ((uint32_t)0x08000000U) /*!< erase/program protection of sector 27 */ 201 #define OB_WP_28 ((uint32_t)0x10000000U) /*!< erase/program protection of sector 28 */ 202 #define OB_WP_29 ((uint32_t)0x20000000U) /*!< erase/program protection of sector 29 */ 203 #define OB_WP_30 ((uint32_t)0x40000000U) /*!< erase/program protection of sector 30 */ 204 #define OB_WP_31 ((uint32_t)0x80000000U) /*!< erase/program protection of rest sectors */ 205 #define OB_WP_ALL ((uint32_t)0xFFFFFFFFU) /*!< erase/program protection of all sectors */ 206 207 /* FMC interrupt enable */ 208 #define FMC_INT_ERR FMC_CTL_ERRIE /*!< FMC error interrupt enable */ 209 #define FMC_INT_END FMC_CTL_ENDIE /*!< FMC end of operation interrupt enable */ 210 211 /* FMC flags */ 212 #define FMC_FLAG_BUSY FMC_STAT_BUSY /*!< FMC busy flag */ 213 #define FMC_FLAG_PGERR FMC_STAT_PGERR /*!< FMC program operation error flag */ 214 #define FMC_FLAG_PGAERR FMC_STAT_PGAERR /*!< FMC program alignment error flag */ 215 #define FMC_FLAG_WPERR FMC_STAT_WPERR /*!< FMC erase/program protection error flag */ 216 #define FMC_FLAG_END FMC_STAT_ENDF /*!< FMC end of operation flag */ 217 #define FMC_FLAG_SLP FMC_STAT_FSTAT /*!< FMC sleep or power down flag */ 218 219 /* FMC interrupt flags */ 220 #define FMC_INT_FLAG_PGERR FMC_STAT_PGERR /*!< FMC program operation error interrupt flag */ 221 #define FMC_INT_FLAG_PGAERR FMC_STAT_PGAERR /*!< FMC program alignment error interrupt flag */ 222 #define FMC_INT_FLAG_WPERR FMC_STAT_WPERR /*!< FMC erase/program protection error interrupt flag */ 223 #define FMC_INT_FLAG_END FMC_STAT_ENDF /*!< FMC end of operation interrupt flag */ 224 225 /* FMC timeout */ 226 #define FMC_TIMEOUT_COUNT ((uint32_t)0x00100000U) /*!< FMC timeout count value */ 227 228 /* double-word number in one row data */ 229 #define DOUBLE_WORDS_CNT_IN_ROW 32U /*!< the number of fast program words */ 230 231 /* function declarations */ 232 /* FMC main memory programming functions */ 233 /* unlock the main FMC operation */ 234 void fmc_unlock(void); 235 /* lock the main FMC operation */ 236 void fmc_lock(void); 237 /* unlock operation of RUN_SLP bit in FMC_WS register */ 238 void fmc_slp_unlock(void); 239 /* set the wait state */ 240 void fmc_wscnt_set(uint32_t wscnt); 241 /* enable pre-fetch */ 242 void fmc_prefetch_enable(void); 243 /* disable pre-fetch */ 244 void fmc_prefetch_disable(void); 245 /* enable low power */ 246 void fmc_low_power_enable(void); 247 /* disable low power */ 248 void fmc_low_power_disable(void); 249 /* flash enter sleep/power-down mode during MCU run/low-power run mode */ 250 void fmc_enter_slp_enable(void); 251 /* flash enter IDLE mode during MCU run/low-power run mode */ 252 void fmc_enter_slp_disable(void); 253 /* flash enter sleep mode when MCU enter deep-sleep mode or RUN_SLP bit is set */ 254 void fmc_enter_sleep_enable(void); 255 /* flash enter power-down mode when MCU enter deep-sleep mode or RUN_SLP bit is set */ 256 void fmc_enter_sleep_disable(void); 257 /* FMC erase page */ 258 fmc_state_enum fmc_page_erase(uint32_t page_address); 259 /* FMC erase whole chip */ 260 fmc_state_enum fmc_mass_erase(void); 261 /* FMC program a word at the corresponding address */ 262 fmc_state_enum fmc_word_program(uint32_t address, uint32_t data); 263 /* FMC fast program a row words at the corresponding address */ 264 fmc_state_enum fmc_fast_program(uint32_t address, uint64_t data[]); 265 266 /* FMC option bytes programming functions */ 267 /* unlock the option bytes operation */ 268 void ob_unlock(void); 269 /* lock the option bytes operation */ 270 void ob_lock(void); 271 /* erase the option bytes */ 272 fmc_state_enum ob_erase(void); 273 /* enable write protection */ 274 fmc_state_enum ob_write_protection_enable(uint32_t ob_wp); 275 /* configure the option bytes security protection */ 276 fmc_state_enum ob_security_protection_config(uint8_t ob_spc); 277 /* program option bytes USER */ 278 fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_bor_th); 279 /* program option bytes DATA */ 280 fmc_state_enum ob_data_program(uint16_t ob_data); 281 /* get the value of option bytes USER */ 282 uint8_t ob_user_get(void); 283 /* get the value of option bytes DATA */ 284 uint16_t ob_data_get(void); 285 /* get the value of option bytes write protection */ 286 uint32_t ob_write_protection_get(void); 287 /* get option bytes security protection state */ 288 FlagStatus ob_security_protection_flag_get(void); 289 290 /* FMC interrupts and flags management functions */ 291 /* get FMC flag status */ 292 FlagStatus fmc_flag_get(uint32_t flag); 293 /* clear the FMC flag */ 294 void fmc_flag_clear(uint32_t flag); 295 /* enable FMC interrupt */ 296 void fmc_interrupt_enable(uint32_t interrupt); 297 /* disable FMC interrupt */ 298 void fmc_interrupt_disable(uint32_t interrupt); 299 /* get FMC interrupt flag */ 300 FlagStatus fmc_interrupt_flag_get(uint32_t flag); 301 /* clear FMC interrupt flag */ 302 void fmc_interrupt_flag_clear(uint32_t flag); 303 304 #endif /* GD32L23X_FMC_H */ 305
