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Searched refs:FMC_CTL1_REG_OFFSET (Results 1 – 2 of 2) sorted by relevance

/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32a50x/standard_peripheral/include/
Dgd32a50x_fmc.h236 #define FMC_CTL1_REG_OFFSET ((uint32_t)0x00000050U) /*!< CTL1 r… macro
288 …FMC_BANK1_INT_FLAG_PGSERR = FMC_REGIDX_BIT2(FMC_CTL1_REG_OFFSET, 10U, FMC_STAT0_REG_OFFSET, 1U), …
289 …FMC_BANK1_INT_FLAG_PGERR = FMC_REGIDX_BIT2(FMC_CTL1_REG_OFFSET, 10U, FMC_STAT0_REG_OFFSET, 2U), …
290 …FMC_BANK1_INT_FLAG_PGAERR = FMC_REGIDX_BIT2(FMC_CTL1_REG_OFFSET, 10U, FMC_STAT0_REG_OFFSET, 3U), …
291 …FMC_BANK1_INT_FLAG_WPERR = FMC_REGIDX_BIT2(FMC_CTL1_REG_OFFSET, 10U, FMC_STAT0_REG_OFFSET, 4U), …
292 …FMC_BANK1_INT_FLAG_END = FMC_REGIDX_BIT2(FMC_CTL1_REG_OFFSET, 12U, FMC_STAT0_REG_OFFSET, 5U), …
293 …FMC_BANK1_INT_FLAG_CBCMDERR = FMC_REGIDX_BIT2(FMC_CTL1_REG_OFFSET, 10U, FMC_STAT0_REG_OFFSET, 6U),…
294 …FMC_BANK1_INT_FLAG_RSTERR = FMC_REGIDX_BIT2(FMC_CTL1_REG_OFFSET, 10U, FMC_STAT0_REG_OFFSET, 15U), …
309 …FMC_BANK1_INT_ERR = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 10U), /*!< FMC bank1…
310 …FMC_BANK1_INT_END = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 12U), /*!< FMC bank1…
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/standard_peripheral/include/
Dgd32f403_fmc.h152 #define FMC_CTL1_REG_OFFSET 0x50U /*!< control register 1 offset */ macro
170 …FMC_INT_BANK1_END = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 12U), /*!< enable FMC bank1…
171 …FMC_INT_BANK1_ERR = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 10U), /*!< enable FMC bank1…