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Searched refs:FMC (Results 1 – 8 of 8) sorted by relevance

/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/standard_peripheral/include/
Dgd32f403_fmc.h43 #define FMC FMC_BASE /*!< FMC register base address */ macro
47 #define FMC_WS REG32((FMC) + 0x00U) /*!< FMC wait state register */
48 #define FMC_KEY0 REG32((FMC) + 0x04U) /*!< FMC unlock key register 0 */
49 #define FMC_OBKEY REG32((FMC) + 0x08U) /*!< FMC option bytes unlock key …
50 #define FMC_STAT0 REG32((FMC) + 0x0CU) /*!< FMC status register 0 */
51 #define FMC_CTL0 REG32((FMC) + 0x10U) /*!< FMC control register 0 */
52 #define FMC_ADDR0 REG32((FMC) + 0x14U) /*!< FMC address register 0 */
53 #define FMC_OBSTAT REG32((FMC) + 0x1CU) /*!< FMC option bytes status regi…
54 #define FMC_WP REG32((FMC) + 0x20U) /*!< FMC erase/program protection…
55 #define FMC_KEY1 REG32((FMC) + 0x44U) /*!< FMC unlock key register 1 */
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/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f3x0/standard_peripheral/include/
Dgd32f3x0_fmc.h44 #define FMC FMC_BASE /*!< FMC register base address */ macro
48 #define FMC_WS REG32(FMC + 0x00000000U) /*!< FMC wait state register */
49 #define FMC_KEY REG32(FMC + 0x00000004U) /*!< FMC unlock key register */
50 #define FMC_OBKEY REG32(FMC + 0x00000008U) /*!< FMC option bytes unlock key regist…
51 #define FMC_STAT REG32(FMC + 0x0000000CU) /*!< FMC status register */
52 #define FMC_CTL REG32(FMC + 0x00000010U) /*!< FMC control register */
53 #define FMC_ADDR REG32(FMC + 0x00000014U) /*!< FMC address register */
54 #define FMC_OBSTAT REG32(FMC + 0x0000001CU) /*!< FMC option bytes status register */
55 #define FMC_WP REG32(FMC + 0x00000020U) /*!< FMC write protection register */
56 #define FMC_WSEN REG32(FMC + 0x000000FCU) /*!< FMC wait state enable register */
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/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32vf103/standard_peripheral/include/
Dgd32vf103_fmc.h44 #define FMC FMC_BASE /*!< FMC register base address */ macro
48 #define FMC_WS REG32((FMC) + 0x00U) /*!< FMC wait state register */
49 #define FMC_KEY REG32((FMC) + 0x04U) /*!< FMC unlock key register */
50 #define FMC_OBKEY REG32((FMC) + 0x08U) /*!< FMC option bytes unlock key…
51 #define FMC_STAT REG32((FMC) + 0x0CU) /*!< FMC status register */
52 #define FMC_CTL REG32((FMC) + 0x10U) /*!< FMC control register */
53 #define FMC_ADDR REG32((FMC) + 0x14U) /*!< FMC address register */
54 #define FMC_OBSTAT REG32((FMC) + 0x1CU) /*!< FMC option bytes status reg…
55 #define FMC_WP REG32((FMC) + 0x20U) /*!< FMC erase/program protectio…
56 #define FMC_PID REG32((FMC) + 0x100U) /*!< FMC product ID register */
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/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32l23x/standard_peripheral/include/
Dgd32l23x_fmc.h41 #define FMC FMC_BASE /*!< FMC base a… macro
45 #define FMC_WS REG32(FMC + 0x00000000U) /*!< FMC wait s…
46 #define FMC_KEY REG32(FMC + 0x00000004U) /*!< FMC unlock…
47 #define FMC_OBKEY REG32(FMC + 0x00000008U) /*!< FMC option…
48 #define FMC_STAT REG32(FMC + 0x0000000CU) /*!< FMC status…
49 #define FMC_CTL REG32(FMC + 0x00000010U) /*!< FMC contro…
50 #define FMC_ADDR REG32(FMC + 0x00000014U) /*!< FMC addres…
51 #define FMC_OBSTAT REG32(FMC + 0x0000001CU) /*!< FMC option…
52 #define FMC_WP REG32(FMC + 0x00000020U) /*!< FMC erase/…
53 #define FMC_SLPKEY REG32(FMC + 0x00000024U) /*!< FMC unlock…
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/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32a50x/standard_peripheral/include/
Dgd32a50x_fmc.h41 #define FMC FMC_BASE /*!< FMC re… macro
45 #define FMC_WS REG32((FMC) + 0x00000000U) /*!< FMC wa…
46 #define FMC_ECCCS REG32((FMC) + 0x00000004U) /*!< FMC EC…
47 #define FMC_KEY0 REG32((FMC) + 0x00000008U) /*!< FMC un…
48 #define FMC_STAT0 REG32((FMC) + 0x0000000CU) /*!< FMC st…
49 #define FMC_CTL0 REG32((FMC) + 0x00000010U) /*!< FMC co…
50 #define FMC_ADDR0 REG32((FMC) + 0x00000014U) /*!< FMC ad…
51 #define FMC_OBKEY REG32((FMC) + 0x00000044U) /*!< FMC op…
52 #define FMC_KEY1 REG32((FMC) + 0x00000048U) /*!< FMC un…
53 #define FMC_STAT1 REG32((FMC) + 0x0000004CU) /*!< FMC st…
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/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/include/
Dgd32e50x_fmc.h44 #define FMC FMC_BASE /*!< FMC base a… macro
48 #define FMC_WS REG32(FMC + 0x00000000U) /*!< FMC wait s…
49 #define FMC_KEY REG32(FMC + 0x00000004U) /*!< FMC unlock…
50 #define FMC_OBKEY REG32(FMC + 0x00000008U) /*!< FMC option…
51 #define FMC_STAT REG32(FMC + 0x0000000CU) /*!< FMC status…
52 #define FMC_CTL REG32(FMC + 0x00000010U) /*!< FMC contro…
53 #define FMC_ADDR REG32(FMC + 0x00000014U) /*!< FMC addres…
54 #define FMC_OBSTAT REG32(FMC + 0x0000001CU) /*!< FMC option…
55 #define FMC_WP REG32(FMC + 0x00000020U) /*!< FMC erase/…
56 #define FMC_PID REG32(FMC + 0x00000100U) /*!< FMC produc…
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/standard_peripheral/include/
Dgd32e10x_fmc.h45 #define FMC FMC_BASE /*!< FMC register base address */ macro
49 #define FMC_WS REG32((FMC) + 0x00000000U) /*!< FMC wait state register */
50 #define FMC_KEY REG32((FMC) + 0x00000004U) /*!< FMC unlock key register */
51 #define FMC_OBKEY REG32((FMC) + 0x00000008U) /*!< FMC option bytes unlock key …
52 #define FMC_STAT REG32((FMC) + 0x0000000CU) /*!< FMC status register */
53 #define FMC_CTL REG32((FMC) + 0x00000010U) /*!< FMC control register */
54 #define FMC_ADDR REG32((FMC) + 0x00000014U) /*!< FMC address register */
55 #define FMC_OBSTAT REG32((FMC) + 0x0000001CU) /*!< FMC option bytes status regi…
56 #define FMC_WP REG32((FMC) + 0x00000020U) /*!< FMC erase/program protection…
57 #define FMC_PID REG32((FMC) + 0x00000100U) /*!< FMC product ID register */
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f4xx/standard_peripheral/include/
Dgd32f4xx_fmc.h46 #define FMC FMC_BASE /*!< FMC register base address */ macro
50 #define FMC_WS REG32((FMC) + 0x00000000U) /*!< FMC wait state register */
51 #define FMC_KEY REG32((FMC) + 0x00000004U) /*!< FMC unlock key register */
52 #define FMC_OBKEY REG32((FMC) + 0x00000008U) /*!< FMC option byte unlock key r…
53 #define FMC_STAT REG32((FMC) + 0x0000000CU) /*!< FMC status register */
54 #define FMC_CTL REG32((FMC) + 0x00000010U) /*!< FMC control register */
55 #define FMC_OBCTL0 REG32((FMC) + 0x00000014U) /*!< FMC option byte control regi…
56 #define FMC_OBCTL1 REG32((FMC) + 0x00000018U) /*!< FMC option byte control regi…
57 #define FMC_PECFG REG32((FMC) + 0x00000020U) /*!< FMC page erase configuration…
58 #define FMC_PEKEY REG32((FMC) + 0x00000024U) /*!< FMC unlock page erase key re…
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