1 /*! 2 \file gd32f4xx_dma.h 3 \brief definitions for the DMA 4 \version 2016-08-15, V1.0.0, firmware for GD32F4xx 5 \version 2018-12-12, V2.0.0, firmware for GD32F4xx 6 \version 2020-09-30, V2.1.0, firmware for GD32F4xx 7 \version 2022-03-09, V3.0.0, firmware for GD32F4xx 8 */ 9 10 /* 11 Copyright (c) 2022, GigaDevice Semiconductor Inc. 12 13 Redistribution and use in source and binary forms, with or without modification, 14 are permitted provided that the following conditions are met: 15 16 1. Redistributions of source code must retain the above copyright notice, this 17 list of conditions and the following disclaimer. 18 2. Redistributions in binary form must reproduce the above copyright notice, 19 this list of conditions and the following disclaimer in the documentation 20 and/or other materials provided with the distribution. 21 3. Neither the name of the copyright holder nor the names of its contributors 22 may be used to endorse or promote products derived from this software without 23 specific prior written permission. 24 25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 34 OF SUCH DAMAGE. 35 */ 36 37 #ifndef GD32F4XX_DMA_H 38 #define GD32F4XX_DMA_H 39 40 #include "gd32f4xx.h" 41 42 /* DMA definitions */ 43 #define DMA0 (DMA_BASE) /*!< DMA0 base address */ 44 #define DMA1 (DMA_BASE + 0x00000400U) /*!< DMA1 base address */ 45 46 /* registers definitions */ 47 #define DMA_INTF0(dmax) REG32((dmax) + 0x00000000U) /*!< DMA interrupt flag register 0 */ 48 #define DMA_INTF1(dmax) REG32((dmax) + 0x00000004U) /*!< DMA interrupt flag register 1 */ 49 #define DMA_INTC0(dmax) REG32((dmax) + 0x00000008U) /*!< DMA interrupt flag clear register 0 */ 50 #define DMA_INTC1(dmax) REG32((dmax) + 0x0000000CU) /*!< DMA interrupt flag clear register 1 */ 51 52 #define DMA_CH0CTL(dmax) REG32((dmax) + 0x00000010U) /*!< DMA channel 0 control register */ 53 #define DMA_CH0CNT(dmax) REG32((dmax) + 0x00000014U) /*!< DMA channel 0 counter register */ 54 #define DMA_CH0PADDR(dmax) REG32((dmax) + 0x00000018U) /*!< DMA channel 0 peripheral base address register */ 55 #define DMA_CH0M0ADDR(dmax) REG32((dmax) + 0x0000001CU) /*!< DMA channel 0 memory 0 base address register */ 56 #define DMA_CH0M1ADDR(dmax) REG32((dmax) + 0x00000020U) /*!< DMA channel 0 memory 1 base address register */ 57 #define DMA_CH0FCTL(dmax) REG32((dmax) + 0x00000024U) /*!< DMA channel 0 FIFO control register */ 58 59 #define DMA_CH1CTL(dmax) REG32((dmax) + 0x00000028U) /*!< DMA channel 1 control register */ 60 #define DMA_CH1CNT(dmax) REG32((dmax) + 0x0000002CU) /*!< DMA channel 1 counter register */ 61 #define DMA_CH1PADDR(dmax) REG32((dmax) + 0x00000030U) /*!< DMA channel 1 peripheral base address register */ 62 #define DMA_CH1M0ADDR(dmax) REG32((dmax) + 0x00000034U) /*!< DMA channel 1 memory 0 base address register */ 63 #define DMA_CH1M1ADDR(dmax) REG32((dmax) + 0x00000038U) /*!< DMA channel 1 memory 1 base address register */ 64 #define DMA_CH1FCTL(dmax) REG32((dmax) + 0x0000003CU) /*!< DMA channel 1 FIFO control register */ 65 66 #define DMA_CH2CTL(dmax) REG32((dmax) + 0x00000040U) /*!< DMA channel 2 control register */ 67 #define DMA_CH2CNT(dmax) REG32((dmax) + 0x00000044U) /*!< DMA channel 2 counter register */ 68 #define DMA_CH2PADDR(dmax) REG32((dmax) + 0x00000048U) /*!< DMA channel 2 peripheral base address register */ 69 #define DMA_CH2M0ADDR(dmax) REG32((dmax) + 0x0000004CU) /*!< DMA channel 2 memory 0 base address register */ 70 #define DMA_CH2M1ADDR(dmax) REG32((dmax) + 0x00000050U) /*!< DMA channel 2 memory 1 base address register */ 71 #define DMA_CH2FCTL(dmax) REG32((dmax) + 0x00000054U) /*!< DMA channel 2 FIFO control register */ 72 73 #define DMA_CH3CTL(dmax) REG32((dmax) + 0x00000058U) /*!< DMA channel 3 control register */ 74 #define DMA_CH3CNT(dmax) REG32((dmax) + 0x0000005CU) /*!< DMA channel 3 counter register */ 75 #define DMA_CH3PADDR(dmax) REG32((dmax) + 0x00000060U) /*!< DMA channel 3 peripheral base address register */ 76 #define DMA_CH3M0ADDR(dmax) REG32((dmax) + 0x00000064U) /*!< DMA channel 3 memory 0 base address register */ 77 #define DMA_CH3M1ADDR(dmax) REG32((dmax) + 0x00000068U) /*!< DMA channel 3 memory 1 base address register */ 78 #define DMA_CH3FCTL(dmax) REG32((dmax) + 0x0000006CU) /*!< DMA channel 3 FIFO control register */ 79 80 #define DMA_CH4CTL(dmax) REG32((dmax) + 0x00000070U) /*!< DMA channel 4 control register */ 81 #define DMA_CH4CNT(dmax) REG32((dmax) + 0x00000074U) /*!< DMA channel 4 counter register */ 82 #define DMA_CH4PADDR(dmax) REG32((dmax) + 0x00000078U) /*!< DMA channel 4 peripheral base address register */ 83 #define DMA_CH4M0ADDR(dmax) REG32((dmax) + 0x0000007CU) /*!< DMA channel 4 memory 0 base address register */ 84 #define DMA_CH4M1ADDR(dmax) REG32((dmax) + 0x00000080U) /*!< DMA channel 4 memory 1 base address register */ 85 #define DMA_CH4FCTL(dmax) REG32((dmax) + 0x00000084U) /*!< DMA channel 4 FIFO control register */ 86 87 #define DMA_CH5CTL(dmax) REG32((dmax) + 0x00000088U) /*!< DMA channel 5 control register */ 88 #define DMA_CH5CNT(dmax) REG32((dmax) + 0x0000008CU) /*!< DMA channel 5 counter register */ 89 #define DMA_CH5PADDR(dmax) REG32((dmax) + 0x00000090U) /*!< DMA channel 5 peripheral base address register */ 90 #define DMA_CH5M0ADDR(dmax) REG32((dmax) + 0x00000094U) /*!< DMA channel 5 memory 0 base address register */ 91 #define DMA_CH5M1ADDR(dmax) REG32((dmax) + 0x00000098U) /*!< DMA channel 5 memory 1 base address register */ 92 #define DMA_CH5FCTL(dmax) REG32((dmax) + 0x0000009CU) /*!< DMA channel 5 FIFO control register */ 93 94 #define DMA_CH6CTL(dmax) REG32((dmax) + 0x000000A0U) /*!< DMA channel 6 control register */ 95 #define DMA_CH6CNT(dmax) REG32((dmax) + 0x000000A4U) /*!< DMA channel 6 counter register */ 96 #define DMA_CH6PADDR(dmax) REG32((dmax) + 0x000000A8U) /*!< DMA channel 6 peripheral base address register */ 97 #define DMA_CH6M0ADDR(dmax) REG32((dmax) + 0x000000ACU) /*!< DMA channel 6 memory 0 base address register */ 98 #define DMA_CH6M1ADDR(dmax) REG32((dmax) + 0x000000B0U) /*!< DMA channel 6 memory 1 base address register */ 99 #define DMA_CH6FCTL(dmax) REG32((dmax) + 0x000000B4U) /*!< DMA channel 6 FIFO control register */ 100 101 #define DMA_CH7CTL(dmax) REG32((dmax) + 0x000000B8U) /*!< DMA channel 7 control register */ 102 #define DMA_CH7CNT(dmax) REG32((dmax) + 0x000000BCU) /*!< DMA channel 7 counter register */ 103 #define DMA_CH7PADDR(dmax) REG32((dmax) + 0x000000C0U) /*!< DMA channel 7 peripheral base address register */ 104 #define DMA_CH7M0ADDR(dmax) REG32((dmax) + 0x000000C4U) /*!< DMA channel 7 memory 0 base address register */ 105 #define DMA_CH7M1ADDR(dmax) REG32((dmax) + 0x000000C8U) /*!< DMA channel 7 memory 1 base address register */ 106 #define DMA_CH7FCTL(dmax) REG32((dmax) + 0x000000CCU) /*!< DMA channel 7 FIFO control register */ 107 108 /* bits definitions */ 109 /* DMA_INTF */ 110 #define DMA_INTF_FEEIF BIT(0) /*!< FIFO error and exception flag */ 111 #define DMA_INTF_SDEIF BIT(2) /*!< single data mode exception flag */ 112 #define DMA_INTF_TAEIF BIT(3) /*!< transfer access error flag */ 113 #define DMA_INTF_HTFIF BIT(4) /*!< half transfer finish flag */ 114 #define DMA_INTF_FTFIF BIT(5) /*!< full transger finish flag */ 115 116 /* DMA_INTC */ 117 #define DMA_INTC_FEEIFC BIT(0) /*!< clear FIFO error and exception flag */ 118 #define DMA_INTC_SDEIFC BIT(2) /*!< clear single data mode exception flag */ 119 #define DMA_INTC_TAEIFC BIT(3) /*!< clear single data mode exception flag */ 120 #define DMA_INTC_HTFIFC BIT(4) /*!< clear half transfer finish flag */ 121 #define DMA_INTC_FTFIFC BIT(5) /*!< clear full transger finish flag */ 122 123 /* DMA_CHxCTL,x=0..7 */ 124 #define DMA_CHXCTL_CHEN BIT(0) /*!< channel x enable */ 125 #define DMA_CHXCTL_SDEIE BIT(1) /*!< enable bit for channel x single data mode exception interrupt */ 126 #define DMA_CHXCTL_TAEIE BIT(2) /*!< enable bit for channel x tranfer access error interrupt */ 127 #define DMA_CHXCTL_HTFIE BIT(3) /*!< enable bit for channel x half transfer finish interrupt */ 128 #define DMA_CHXCTL_FTFIE BIT(4) /*!< enable bit for channel x full transfer finish interrupt */ 129 #define DMA_CHXCTL_TFCS BIT(5) /*!< transfer flow controller select */ 130 #define DMA_CHXCTL_TM BITS(6,7) /*!< transfer mode */ 131 #define DMA_CHXCTL_CMEN BIT(8) /*!< circulation mode */ 132 #define DMA_CHXCTL_PNAGA BIT(9) /*!< next address generation algorithm of peripheral */ 133 #define DMA_CHXCTL_MNAGA BIT(10) /*!< next address generation algorithm of memory */ 134 #define DMA_CHXCTL_PWIDTH BITS(11,12) /*!< transfer width of peipheral */ 135 #define DMA_CHXCTL_MWIDTH BITS(13,14) /*!< transfer width of memory */ 136 #define DMA_CHXCTL_PAIF BIT(15) /*!< peripheral address increment fixed */ 137 #define DMA_CHXCTL_PRIO BITS(16,17) /*!< priority level */ 138 #define DMA_CHXCTL_SBMEN BIT(18) /*!< switch-buffer mode enable */ 139 #define DMA_CHXCTL_MBS BIT(19) /*!< memory buffer select */ 140 #define DMA_CHXCTL_PBURST BITS(21,22) /*!< transfer burst type of peripheral */ 141 #define DMA_CHXCTL_MBURST BITS(23,24) /*!< transfer burst type of memory */ 142 #define DMA_CHXCTL_PERIEN BITS(25,27) /*!< peripheral enable */ 143 144 /* DMA_CHxCNT,x=0..7 */ 145 #define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */ 146 147 /* DMA_CHxPADDR,x=0..7 */ 148 #define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */ 149 150 /* DMA_CHxM0ADDR,x=0..7 */ 151 #define DMA_CHXM0ADDR_M0ADDR BITS(0,31) /*!< memory 0 base address */ 152 153 /* DMA_CHxM1ADDR,x=0..7 */ 154 #define DMA_CHXM1ADDR_M0ADDR BITS(0,31) /*!< memory 1 base address */ 155 156 /* DMA_CHxFCTL,x=0..7 */ 157 #define DMA_CHXFCTL_FCCV BITS(0,1) /*!< FIFO counter critical value */ 158 #define DMA_CHXFCTL_MDMEN BIT(2) /*!< multi-data mode enable */ 159 #define DMA_CHXFCTL_FCNT BITS(3,5) /*!< FIFO counter */ 160 #define DMA_CHXFCTL_FEEIE BIT(7) /*!< FIFO exception interrupt enable */ 161 162 /* constants definitions */ 163 /* DMA channel select */ 164 typedef enum 165 { 166 DMA_CH0 = 0, /*!< DMA Channel 0 */ 167 DMA_CH1, /*!< DMA Channel 1 */ 168 DMA_CH2, /*!< DMA Channel 2 */ 169 DMA_CH3, /*!< DMA Channel 3 */ 170 DMA_CH4, /*!< DMA Channel 4 */ 171 DMA_CH5, /*!< DMA Channel 5 */ 172 DMA_CH6, /*!< DMA Channel 6 */ 173 DMA_CH7 /*!< DMA Channel 7 */ 174 } dma_channel_enum; 175 176 /* DMA peripheral select */ 177 typedef enum 178 { 179 DMA_SUBPERI0 = 0, /*!< DMA Peripheral 0 */ 180 DMA_SUBPERI1, /*!< DMA Peripheral 1 */ 181 DMA_SUBPERI2, /*!< DMA Peripheral 2 */ 182 DMA_SUBPERI3, /*!< DMA Peripheral 3 */ 183 DMA_SUBPERI4, /*!< DMA Peripheral 4 */ 184 DMA_SUBPERI5, /*!< DMA Peripheral 5 */ 185 DMA_SUBPERI6, /*!< DMA Peripheral 6 */ 186 DMA_SUBPERI7 /*!< DMA Peripheral 7 */ 187 } dma_subperipheral_enum; 188 189 /* DMA multidata mode initialize struct */ 190 typedef struct 191 { 192 uint32_t periph_addr; /*!< peripheral base address */ 193 uint32_t periph_width; /*!< transfer data size of peripheral */ 194 uint32_t periph_inc; /*!< peripheral increasing mode */ 195 196 uint32_t memory0_addr; /*!< memory 0 base address */ 197 uint32_t memory_width; /*!< transfer data size of memory */ 198 uint32_t memory_inc; /*!< memory increasing mode */ 199 200 uint32_t memory_burst_width; /*!< multi data mode enable */ 201 uint32_t periph_burst_width; /*!< multi data mode enable */ 202 uint32_t critical_value; /*!< FIFO critical */ 203 204 uint32_t circular_mode; /*!< DMA circular mode */ 205 uint32_t direction; /*!< channel data transfer direction */ 206 uint32_t number; /*!< channel transfer number */ 207 uint32_t priority; /*!< channel priority level */ 208 }dma_multi_data_parameter_struct; 209 210 /* DMA singledata mode initialize struct */ 211 typedef struct 212 { 213 uint32_t periph_addr; /*!< peripheral base address */ 214 uint32_t periph_inc; /*!< peripheral increasing mode */ 215 216 uint32_t memory0_addr; /*!< memory 0 base address */ 217 uint32_t memory_inc; /*!< memory increasing mode */ 218 219 uint32_t periph_memory_width; /*!< transfer data size of peripheral */ 220 221 uint32_t circular_mode; /*!< DMA circular mode */ 222 uint32_t direction; /*!< channel data transfer direction */ 223 uint32_t number; /*!< channel transfer number */ 224 uint32_t priority; /*!< channel priority level */ 225 } dma_single_data_parameter_struct; 226 227 #define DMA_FLAG_ADD(flag,channel) ((uint32_t)((flag)<<((((uint32_t)(channel)*6U))+((uint32_t)(((uint32_t)(channel)) >> 1U)&0x01U)*4U))) /*!< DMA channel flag shift */ 228 229 /* DMA_register address */ 230 #define DMA_CHCTL(dma,channel) REG32(((dma) + 0x10U) + 0x18U*(channel)) /*!< the address of DMA channel CHXCTL register */ 231 #define DMA_CHCNT(dma,channel) REG32(((dma) + 0x14U) + 0x18U*(channel)) /*!< the address of DMA channel CHXCNT register */ 232 #define DMA_CHPADDR(dma,channel) REG32(((dma) + 0x18U) + 0x18U*(channel)) /*!< the address of DMA channel CHXPADDR register */ 233 #define DMA_CHM0ADDR(dma,channel) REG32(((dma) + 0x1CU) + 0x18U*(channel)) /*!< the address of DMA channel CHXM0ADDR register */ 234 #define DMA_CHM1ADDR(dma,channel) REG32(((dma) + 0x20U) + 0x18U*(channel)) /*!< the address of DMA channel CHXM1ADDR register */ 235 #define DMA_CHFCTL(dma,channel) REG32(((dma) + 0x24U) + 0x18U*(channel)) /*!< the address of DMA channel CHXMADDR register */ 236 237 /* peripheral select */ 238 #define CHCTL_PERIEN(regval) (BITS(25,27) & ((uint32_t)(regval) << 25)) 239 #define DMA_PERIPH_0_SELECT CHCTL_PERIEN(0) /*!< peripheral 0 select */ 240 #define DMA_PERIPH_1_SELECT CHCTL_PERIEN(1) /*!< peripheral 1 select */ 241 #define DMA_PERIPH_2_SELECT CHCTL_PERIEN(2) /*!< peripheral 2 select */ 242 #define DMA_PERIPH_3_SELECT CHCTL_PERIEN(3) /*!< peripheral 3 select */ 243 #define DMA_PERIPH_4_SELECT CHCTL_PERIEN(4) /*!< peripheral 4 select */ 244 #define DMA_PERIPH_5_SELECT CHCTL_PERIEN(5) /*!< peripheral 5 select */ 245 #define DMA_PERIPH_6_SELECT CHCTL_PERIEN(6) /*!< peripheral 6 select */ 246 #define DMA_PERIPH_7_SELECT CHCTL_PERIEN(7) /*!< peripheral 7 select */ 247 248 /* burst type of memory */ 249 #define CHCTL_MBURST(regval) (BITS(23,24) & ((uint32_t)(regval) << 23)) 250 #define DMA_MEMORY_BURST_SINGLE CHCTL_MBURST(0) /*!< single burst */ 251 #define DMA_MEMORY_BURST_4_BEAT CHCTL_MBURST(1) /*!< 4-beat burst */ 252 #define DMA_MEMORY_BURST_8_BEAT CHCTL_MBURST(2) /*!< 8-beat burst */ 253 #define DMA_MEMORY_BURST_16_BEAT CHCTL_MBURST(3) /*!< 16-beat burst */ 254 255 /* burst type of peripheral */ 256 #define CHCTL_PBURST(regval) (BITS(21,22) & ((uint32_t)(regval) << 21)) 257 #define DMA_PERIPH_BURST_SINGLE CHCTL_PBURST(0) /*!< single burst */ 258 #define DMA_PERIPH_BURST_4_BEAT CHCTL_PBURST(1) /*!< 4-beat burst */ 259 #define DMA_PERIPH_BURST_8_BEAT CHCTL_PBURST(2) /*!< 8-beat burst */ 260 #define DMA_PERIPH_BURST_16_BEAT CHCTL_PBURST(3) /*!< 16-beat burst */ 261 262 /* channel priority level */ 263 #define CHCTL_PRIO(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) 264 #define DMA_PRIORITY_LOW CHCTL_PRIO(0) /*!< low priority */ 265 #define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1) /*!< medium priority */ 266 #define DMA_PRIORITY_HIGH CHCTL_PRIO(2) /*!< high priority */ 267 #define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3) /*!< ultra high priority */ 268 269 /* transfer data width of memory */ 270 #define CHCTL_MWIDTH(regval) (BITS(13,14) & ((uint32_t)(regval) << 13)) 271 #define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0) /*!< transfer data width of memory is 8-bit */ 272 #define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1) /*!< transfer data width of memory is 16-bit */ 273 #define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2) /*!< transfer data width of memory is 32-bit */ 274 275 /* transfer data width of peripheral */ 276 #define CHCTL_PWIDTH(regval) (BITS(11,12) & ((uint32_t)(regval) << 11)) 277 #define DMA_PERIPH_WIDTH_8BIT CHCTL_PWIDTH(0) /*!< transfer data width of peripheral is 8-bit */ 278 #define DMA_PERIPH_WIDTH_16BIT CHCTL_PWIDTH(1) /*!< transfer data width of peripheral is 16-bit */ 279 #define DMA_PERIPH_WIDTH_32BIT CHCTL_PWIDTH(2) /*!< transfer data width of peripheral is 32-bit */ 280 281 /* channel transfer mode */ 282 #define CHCTL_TM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) 283 #define DMA_PERIPH_TO_MEMORY CHCTL_TM(0) /*!< read from peripheral and write to memory */ 284 #define DMA_MEMORY_TO_PERIPH CHCTL_TM(1) /*!< read from memory and write to peripheral */ 285 #define DMA_MEMORY_TO_MEMORY CHCTL_TM(2) /*!< read from memory and write to memory */ 286 287 /* FIFO counter critical value */ 288 #define CHFCTL_FCCV(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) 289 #define DMA_FIFO_1_WORD CHFCTL_FCCV(0) /*!< critical value 1 word */ 290 #define DMA_FIFO_2_WORD CHFCTL_FCCV(1) /*!< critical value 2 word */ 291 #define DMA_FIFO_3_WORD CHFCTL_FCCV(2) /*!< critical value 3 word */ 292 #define DMA_FIFO_4_WORD CHFCTL_FCCV(3) /*!< critical value 4 word */ 293 294 /* memory select */ 295 #define DMA_MEMORY_0 ((uint32_t)0x00000000U) /*!< select memory 0 */ 296 #define DMA_MEMORY_1 ((uint32_t)0x00000001U) /*!< select memory 1 */ 297 298 /* DMA circular mode */ 299 #define DMA_CIRCULAR_MODE_ENABLE ((uint32_t)0x00000000U) /*!< circular mode enable */ 300 #define DMA_CIRCULAR_MODE_DISABLE ((uint32_t)0x00000001U) /*!< circular mode disable */ 301 302 /* DMA flow controller select */ 303 #define DMA_FLOW_CONTROLLER_DMA ((uint32_t)0x00000000U) /*!< DMA is the flow controler */ 304 #define DMA_FLOW_CONTROLLER_PERI ((uint32_t)0x00000001U) /*!< peripheral is the flow controler */ 305 306 /* peripheral increasing mode */ 307 #define DMA_PERIPH_INCREASE_ENABLE ((uint32_t)0x00000000U) /*!< next address of peripheral is increasing address mode */ 308 #define DMA_PERIPH_INCREASE_DISABLE ((uint32_t)0x00000001U) /*!< next address of peripheral is fixed address mode */ 309 #define DMA_PERIPH_INCREASE_FIX ((uint32_t)0x00000002U) /*!< next address of peripheral is increasing fixed */ 310 311 /* memory increasing mode */ 312 #define DMA_MEMORY_INCREASE_ENABLE ((uint32_t)0x00000000U) /*!< next address of memory is increasing address mode */ 313 #define DMA_MEMORY_INCREASE_DISABLE ((uint32_t)0x00000001U) /*!< next address of memory is fixed address mode */ 314 315 /* FIFO status */ 316 #define DMA_FIFO_STATUS_NODATA ((uint32_t)0x00000000U) /*!< the data in the FIFO less than 1 word */ 317 #define DMA_FIFO_STATUS_1_WORD ((uint32_t)0x00000001U) /*!< the data in the FIFO more than 1 word, less than 2 words */ 318 #define DMA_FIFO_STATUS_2_WORD ((uint32_t)0x00000002U) /*!< the data in the FIFO more than 2 word, less than 3 words */ 319 #define DMA_FIFO_STATUS_3_WORD ((uint32_t)0x00000003U) /*!< the data in the FIFO more than 3 word, less than 4 words */ 320 #define DMA_FIFO_STATUS_EMPTY ((uint32_t)0x00000004U) /*!< the data in the FIFO is empty */ 321 #define DMA_FIFO_STATUS_FULL ((uint32_t)0x00000005U) /*!< the data in the FIFO is full */ 322 323 /* DMA reset value */ 324 #define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */ 325 #define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */ 326 #define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */ 327 #define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */ 328 #define DMA_CHINTF_RESET_VALUE ((uint32_t)0x0000003DU) /*!< clear DMA channel CHXINTFS register */ 329 #define DMA_CHFCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXFCTL register */ 330 331 /* DMA_INTF register */ 332 /* interrupt flag bits */ 333 #define DMA_INT_FLAG_FEE DMA_INTF_FEEIF /*!< FIFO error and exception flag */ 334 #define DMA_INT_FLAG_SDE DMA_INTF_SDEIF /*!< single data mode exception flag */ 335 #define DMA_INT_FLAG_TAE DMA_INTF_TAEIF /*!< transfer access error flag */ 336 #define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag */ 337 #define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag */ 338 339 /* flag bits */ 340 #define DMA_FLAG_FEE DMA_INTF_FEEIF /*!< FIFO error and exception flag */ 341 #define DMA_FLAG_SDE DMA_INTF_SDEIF /*!< single data mode exception flag */ 342 #define DMA_FLAG_TAE DMA_INTF_TAEIF /*!< transfer access error flag */ 343 #define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag */ 344 #define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag */ 345 346 347 /* function declarations */ 348 /* DMA deinitialization and initialization functions */ 349 /* deinitialize DMA a channel registers */ 350 void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx); 351 /* initialize the DMA single data mode parameters struct with the default values */ 352 void dma_single_data_para_struct_init(dma_single_data_parameter_struct* init_struct); 353 /* initialize the DMA multi data mode parameters struct with the default values */ 354 void dma_multi_data_para_struct_init(dma_multi_data_parameter_struct* init_struct); 355 /* DMA single data mode initialize */ 356 void dma_single_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_single_data_parameter_struct* init_struct); 357 /* DMA multi data mode initialize */ 358 void dma_multi_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_multi_data_parameter_struct* init_struct); 359 360 /* DMA configuration functions */ 361 /* set DMA peripheral base address */ 362 void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address); 363 /* set DMA Memory base address */ 364 void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t memory_flag, uint32_t address); 365 366 /* set the number of remaining data to be transferred by the DMA */ 367 void dma_transfer_number_config(uint32_t dma_periph,dma_channel_enum channelx, uint32_t number); 368 /* get the number of remaining data to be transferred by the DMA */ 369 uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx); 370 371 /* configure priority level of DMA channel */ 372 void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority); 373 374 /* configure transfer burst beats of memory */ 375 void dma_memory_burst_beats_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t mbeat); 376 /* configure transfer burst beats of peripheral */ 377 void dma_periph_burst_beats_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t pbeat); 378 /* configure transfer data size of memory */ 379 void dma_memory_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t msize); 380 /* configure transfer data size of peripheral */ 381 void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t psize); 382 383 /* configure next address increasement algorithm of memory */ 384 void dma_memory_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm); 385 /* configure next address increasement algorithm of peripheral */ 386 void dma_peripheral_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm); 387 388 /* enable DMA circulation mode */ 389 void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx); 390 /* disable DMA circulation mode */ 391 void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx); 392 /* enable DMA channel */ 393 void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx); 394 /* disable DMA channel */ 395 void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx); 396 397 /* configure the direction of data transfer on the channel */ 398 void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t direction); 399 400 /* DMA switch buffer mode config */ 401 void dma_switch_buffer_mode_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t memory1_addr, uint32_t memory_select); 402 /* DMA using memory get */ 403 uint32_t dma_using_memory_get(uint32_t dma_periph, dma_channel_enum channelx); 404 405 /* DMA channel peripheral select */ 406 void dma_channel_subperipheral_select(uint32_t dma_periph, dma_channel_enum channelx, dma_subperipheral_enum sub_periph); 407 /* DMA flow controller configure */ 408 void dma_flow_controller_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t controller); 409 /* DMA flow controller enable */ 410 void dma_switch_buffer_mode_enable(uint32_t dma_periph, dma_channel_enum channelx, ControlStatus newvalue); 411 /* DMA FIFO status get */ 412 uint32_t dma_fifo_status_get(uint32_t dma_periph, dma_channel_enum channelx); 413 414 /* flag and interrupt functions */ 415 /* check DMA flag is set or not */ 416 FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); 417 /* clear DMA a channel flag */ 418 void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); 419 /* enable DMA interrupt */ 420 void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); 421 /* disable DMA interrupt */ 422 void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); 423 /* check DMA flag is set or not */ 424 FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt); 425 /* clear DMA a channel flag */ 426 void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt); 427 428 #endif /* GD32F4XX_DMA_H */ 429
