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Searched refs:DMA_CHXCTL_M2M (Results 1 – 14 of 14) sorted by relevance

/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f3x0/standard_peripheral/source/
Dgd32f3x0_dma.c176 DMA_CHCTL(channelx) |= DMA_CHXCTL_M2M; in dma_memory_to_memory_enable()
189 DMA_CHCTL(channelx) &= ~DMA_CHXCTL_M2M; in dma_memory_to_memory_disable()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/source/
Dgd32e50x_dma.c218 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_M2M; in dma_memory_to_memory_enable()
237 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_M2M; in dma_memory_to_memory_disable()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/standard_peripheral/source/
Dgd32f403_dma.c214 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_M2M; in dma_memory_to_memory_enable()
233 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_M2M; in dma_memory_to_memory_disable()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/standard_peripheral/source/
Dgd32e10x_dma.c215 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_M2M; in dma_memory_to_memory_enable()
234 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_M2M; in dma_memory_to_memory_disable()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32vf103/standard_peripheral/source/
Dgd32vf103_dma.c209 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_M2M; in dma_memory_to_memory_enable()
228 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_M2M; in dma_memory_to_memory_disable()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32l23x/standard_peripheral/source/
Dgd32l23x_dma.c200 DMA_CHCTL(channelx) |= DMA_CHXCTL_M2M; in dma_memory_to_memory_enable()
213 DMA_CHCTL(channelx) &= ~DMA_CHXCTL_M2M; in dma_memory_to_memory_disable()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32a50x/standard_peripheral/source/
Dgd32a50x_dma.c220 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_M2M; in dma_memory_to_memory_enable()
234 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_M2M; in dma_memory_to_memory_disable()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f3x0/standard_peripheral/include/
Dgd32f3x0_dma.h102 #define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */ macro
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/standard_peripheral/include/
Dgd32f403_dma.h110 #define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */ macro
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32vf103/standard_peripheral/include/
Dgd32vf103_dma.h110 #define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */ macro
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/standard_peripheral/include/
Dgd32e10x_dma.h104 #define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */ macro
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/include/
Dgd32e50x_dma.h110 #define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */ macro
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32l23x/standard_peripheral/include/
Dgd32l23x_dma.h117 #define DMA_CHXCTL_M2M BIT(14) … macro
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32a50x/standard_peripheral/include/
Dgd32a50x_dma.h127 #define DMA_CHXCTL_M2M BIT(14) /*!< memory to memor… macro