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Searched refs:DMA_CHCTL_RESET_VALUE (Results 1 – 16 of 16) sorted by relevance

/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f3x0/standard_peripheral/include/
Dgd32f3x0_dma.h141 #define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the … macro
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f3x0/standard_peripheral/source/
Dgd32f3x0_dma.c52 DMA_CHCTL(channelx) = DMA_CHCTL_RESET_VALUE; in dma_deinit()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/standard_peripheral/include/
Dgd32f403_dma.h157 #define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< th… macro
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32vf103/standard_peripheral/include/
Dgd32vf103_dma.h158 #define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< th… macro
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/standard_peripheral/include/
Dgd32e10x_dma.h151 #define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< th… macro
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/include/
Dgd32e50x_dma.h158 #define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< th… macro
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/source/
Dgd32e50x_dma.c64 DMA_CHCTL(dma_periph, channelx) = DMA_CHCTL_RESET_VALUE; in dma_deinit()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/standard_peripheral/source/
Dgd32f403_dma.c64 DMA_CHCTL(dma_periph, channelx) = DMA_CHCTL_RESET_VALUE; in dma_deinit()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/standard_peripheral/source/
Dgd32e10x_dma.c65 DMA_CHCTL(dma_periph, channelx) = DMA_CHCTL_RESET_VALUE; in dma_deinit()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32vf103/standard_peripheral/source/
Dgd32vf103_dma.c63 DMA_CHCTL(dma_periph, channelx) = DMA_CHCTL_RESET_VALUE; in dma_deinit()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32l23x/standard_peripheral/source/
Dgd32l23x_dma.c53 DMA_CHCTL(channelx) = DMA_CHCTL_RESET_VALUE; in dma_deinit()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f4xx/standard_peripheral/include/
Dgd32f4xx_dma.h324 #define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset … macro
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32a50x/standard_peripheral/source/
Dgd32a50x_dma.c55 DMA_CHCTL(dma_periph, channelx) = DMA_CHCTL_RESET_VALUE; in dma_deinit()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f4xx/standard_peripheral/source/
Dgd32f4xx_dma.c56 DMA_CHCTL(dma_periph, channelx) = DMA_CHCTL_RESET_VALUE; in dma_deinit()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32l23x/standard_peripheral/include/
Dgd32l23x_dma.h307 #define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) … macro
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32a50x/standard_peripheral/include/
Dgd32a50x_dma.h364 #define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the… macro