| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f3x0/standard_peripheral/source/ |
| D | gd32f3x0_dma.c | 53 DMA_CHCNT(channelx) = DMA_CHCNT_RESET_VALUE; in dma_deinit()
110 DMA_CHCNT(channelx) = (init_struct->number & DMA_CHANNEL_CNT_MASK); in dma_init()
257 DMA_CHCNT(channelx) = (number & DMA_CHANNEL_CNT_MASK); in dma_transfer_number_config()
270 return (uint32_t)DMA_CHCNT(channelx); in dma_transfer_number_get()
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/source/ |
| D | gd32e50x_dma.c | 65 DMA_CHCNT(dma_periph, channelx) = DMA_CHCNT_RESET_VALUE; in dma_deinit()
134 DMA_CHCNT(dma_periph, channelx) = (init_struct->number & DMA_CHANNEL_CNT_MASK); in dma_init()
335 DMA_CHCNT(dma_periph, channelx) = (number & DMA_CHANNEL_CNT_MASK); in dma_transfer_number_config()
354 return (uint32_t)DMA_CHCNT(dma_periph, channelx); in dma_transfer_number_get()
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/standard_peripheral/source/ |
| D | gd32f403_dma.c | 65 DMA_CHCNT(dma_periph, channelx) = DMA_CHCNT_RESET_VALUE; in dma_deinit()
130 DMA_CHCNT(dma_periph, channelx) = (init_struct->number & DMA_CHANNEL_CNT_MASK); in dma_init()
331 DMA_CHCNT(dma_periph, channelx) = (number & DMA_CHANNEL_CNT_MASK); in dma_transfer_number_config()
350 return (uint32_t)DMA_CHCNT(dma_periph, channelx); in dma_transfer_number_get()
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/standard_peripheral/source/ |
| D | gd32e10x_dma.c | 66 DMA_CHCNT(dma_periph, channelx) = DMA_CHCNT_RESET_VALUE; in dma_deinit()
131 DMA_CHCNT(dma_periph, channelx) = (init_struct->number & DMA_CHANNEL_CNT_MASK); in dma_init()
333 DMA_CHCNT(dma_periph, channelx) = (number & DMA_CHANNEL_CNT_MASK); in dma_transfer_number_config()
352 return (uint32_t)DMA_CHCNT(dma_periph, channelx); in dma_transfer_number_get()
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32vf103/standard_peripheral/source/ |
| D | gd32vf103_dma.c | 64 DMA_CHCNT(dma_periph, channelx) = DMA_CHCNT_RESET_VALUE; in dma_deinit()
125 DMA_CHCNT(dma_periph, channelx) = (init_struct->number & DMA_CHANNEL_CNT_MASK); in dma_init()
326 DMA_CHCNT(dma_periph, channelx) = (number & DMA_CHANNEL_CNT_MASK); in dma_transfer_number_config()
345 return (uint32_t)DMA_CHCNT(dma_periph, channelx); in dma_transfer_number_get()
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f4xx/standard_peripheral/source/ |
| D | gd32f4xx_dma.c | 57 DMA_CHCNT(dma_periph, channelx) = DMA_CHCNT_RESET_VALUE; in dma_deinit()
146 DMA_CHCNT(dma_periph, channelx) = init_struct->number; in dma_single_data_mode_init()
215 DMA_CHCNT(dma_periph, channelx) = init_struct->number; in dma_multi_data_mode_init()
295 DMA_CHCNT(dma_periph, channelx) = number; in dma_transfer_number_config()
309 return (uint32_t)DMA_CHCNT(dma_periph, channelx); in dma_transfer_number_get()
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32l23x/standard_peripheral/source/ |
| D | gd32l23x_dma.c | 54 DMA_CHCNT(channelx) = DMA_CHCNT_RESET_VALUE; in dma_deinit()
131 DMA_CHCNT(channelx) = (init_struct->number & DMA_CHANNEL_CNT_MASK); in dma_init()
282 DMA_CHCNT(channelx) = (number & DMA_CHANNEL_CNT_MASK); in dma_transfer_number_config()
295 return (uint32_t)DMA_CHCNT(channelx); in dma_transfer_number_get()
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32a50x/standard_peripheral/source/ |
| D | gd32a50x_dma.c | 56 DMA_CHCNT(dma_periph, channelx) = DMA_CHCNT_RESET_VALUE; in dma_deinit()
143 DMA_CHCNT(dma_periph, channelx) = (init_struct->number & DMA_CHANNEL_CNT_MASK); in dma_init()
307 DMA_CHCNT(dma_periph, channelx) = (number & DMA_CHANNEL_CNT_MASK); in dma_transfer_number_config()
321 return (uint32_t)DMA_CHCNT(dma_periph, channelx); in dma_transfer_number_get()
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f3x0/standard_peripheral/include/ |
| D | gd32f3x0_dma.h | 158 #define DMA_CHCNT(channel) REG32(DMA_CHXCNT_BASE + (uint32_t)0x0000014U * (uint32_t)… macro
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/standard_peripheral/include/ |
| D | gd32f403_dma.h | 152 #define DMA_CHCNT(dma, channel) REG32(((dma) + 0x0CU) + 0x14U * (uint32_t)(channel)) … macro
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32vf103/standard_peripheral/include/ |
| D | gd32vf103_dma.h | 153 #define DMA_CHCNT(dma, channel) REG32(((dma) + 0x0CU) + 0x14U * (uint32_t)(channel)) … macro
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/standard_peripheral/include/ |
| D | gd32e10x_dma.h | 146 #define DMA_CHCNT(dma, channel) REG32(((dma) + 0x0CU) + 0x14U * (uint32_t)(channel)) … macro
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/include/ |
| D | gd32e50x_dma.h | 153 #define DMA_CHCNT(dma, channel) REG32(((dma) + 0x0000000CU) + 0x00000014U * (uint32_t)(… macro
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f4xx/standard_peripheral/include/ |
| D | gd32f4xx_dma.h | 231 #define DMA_CHCNT(dma,channel) REG32(((dma) + 0x14U) + 0x18U*(channel)) /*!< the addres… macro
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32l23x/standard_peripheral/include/ |
| D | gd32l23x_dma.h | 324 #define DMA_CHCNT(channel) REG32(DMA_CHXCNT_BASE + 0x14U * (uint32_t)(channel)) … macro
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32a50x/standard_peripheral/include/ |
| D | gd32a50x_dma.h | 375 #define DMA_CHCNT(dma, channel) REG32(((dma) + 0x0000000CU) + 0x14U * (uint32_t)(ch… macro
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