1 /*! 2 \file gd32f4xx_dci.h 3 \brief definitions for the DCI 4 5 \version 2016-08-15, V1.0.0, firmware for GD32F4xx 6 \version 2018-12-12, V2.0.0, firmware for GD32F4xx 7 \version 2020-09-30, V2.1.0, firmware for GD32F4xx 8 \version 2022-03-09, V3.0.0, firmware for GD32F4xx 9 */ 10 11 /* 12 Copyright (c) 2022, GigaDevice Semiconductor Inc. 13 14 Redistribution and use in source and binary forms, with or without modification, 15 are permitted provided that the following conditions are met: 16 17 1. Redistributions of source code must retain the above copyright notice, this 18 list of conditions and the following disclaimer. 19 2. Redistributions in binary form must reproduce the above copyright notice, 20 this list of conditions and the following disclaimer in the documentation 21 and/or other materials provided with the distribution. 22 3. Neither the name of the copyright holder nor the names of its contributors 23 may be used to endorse or promote products derived from this software without 24 specific prior written permission. 25 26 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 28 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 33 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 35 OF SUCH DAMAGE. 36 */ 37 38 #ifndef GD32F4XX_DCI_H 39 #define GD32F4XX_DCI_H 40 41 #include "gd32f4xx.h" 42 43 /* DCI definitions */ 44 #define DCI DCI_BASE 45 46 /* registers definitions */ 47 #define DCI_CTL REG32(DCI + 0x00U) /*!< DCI control register */ 48 #define DCI_STAT0 REG32(DCI + 0x04U) /*!< DCI status register 0 */ 49 #define DCI_STAT1 REG32(DCI + 0x08U) /*!< DCI status register 1 */ 50 #define DCI_INTEN REG32(DCI + 0x0CU) /*!< DCI interrupt enable register */ 51 #define DCI_INTF REG32(DCI + 0x10U) /*!< DCI interrupt flag register */ 52 #define DCI_INTC REG32(DCI + 0x14U) /*!< DCI interrupt clear register */ 53 #define DCI_SC REG32(DCI + 0x18U) /*!< DCI synchronization codes register */ 54 #define DCI_SCUMSK REG32(DCI + 0x1CU) /*!< DCI synchronization codes unmask register */ 55 #define DCI_CWSPOS REG32(DCI + 0x20U) /*!< DCI cropping window start position register */ 56 #define DCI_CWSZ REG32(DCI + 0x24U) /*!< DCI cropping window size register */ 57 #define DCI_DATA REG32(DCI + 0x28U) /*!< DCI data register */ 58 59 /* bits definitions */ 60 /* DCI_CTL */ 61 #define DCI_CTL_CAP BIT(0) /*!< capture enable */ 62 #define DCI_CTL_SNAP BIT(1) /*!< snapshot mode */ 63 #define DCI_CTL_WDEN BIT(2) /*!< window enable */ 64 #define DCI_CTL_JM BIT(3) /*!< JPEG mode */ 65 #define DCI_CTL_ESM BIT(4) /*!< embedded synchronous mode */ 66 #define DCI_CTL_CKS BIT(5) /*!< clock polarity selection */ 67 #define DCI_CTL_HPS BIT(6) /*!< horizontal polarity selection */ 68 #define DCI_CTL_VPS BIT(7) /*!< vertical polarity selection */ 69 #define DCI_CTL_FR BITS(8,9) /*!< frame rate */ 70 #define DCI_CTL_DCIF BITS(10,11) /*!< digital camera interface format */ 71 #define DCI_CTL_DCIEN BIT(14) /*!< DCI enable */ 72 73 /* DCI_STAT0 */ 74 #define DCI_STAT0_HS BIT(0) /*!< HS line status */ 75 #define DCI_STAT0_VS BIT(1) /*!< VS line status */ 76 #define DCI_STAT0_FV BIT(2) /*!< FIFO valid */ 77 78 /* DCI_STAT1 */ 79 #define DCI_STAT1_EFF BIT(0) /*!< end of frame flag */ 80 #define DCI_STAT1_OVRF BIT(1) /*!< FIFO overrun flag */ 81 #define DCI_STAT1_ESEF BIT(2) /*!< embedded synchronous error flag */ 82 #define DCI_STAT1_VSF BIT(3) /*!< vsync flag */ 83 #define DCI_STAT1_ELF BIT(4) /*!< end of line flag */ 84 85 /* DCI_INTEN */ 86 #define DCI_INTEN_EFIE BIT(0) /*!< end of frame interrupt enable */ 87 #define DCI_INTEN_OVRIE BIT(1) /*!< FIFO overrun interrupt enable */ 88 #define DCI_INTEN_ESEIE BIT(2) /*!< embedded synchronous error interrupt enable */ 89 #define DCI_INTEN_VSIE BIT(3) /*!< vsync interrupt enable */ 90 #define DCI_INTEN_ELIE BIT(4) /*!< end of line interrupt enable */ 91 92 /* DCI_INTF */ 93 #define DCI_INTF_EFIF BIT(0) /*!< end of frame interrupt flag */ 94 #define DCI_INTF_OVRIF BIT(1) /*!< FIFO overrun interrupt flag */ 95 #define DCI_INTF_ESEIF BIT(2) /*!< embedded synchronous error interrupt flag */ 96 #define DCI_INTF_VSIF BIT(3) /*!< vsync interrupt flag */ 97 #define DCI_INTF_ELIF BIT(4) /*!< end of line interrupt flag */ 98 99 /* DCI_INTC */ 100 #define DCI_INTC_EFFC BIT(0) /*!< clear end of frame flag */ 101 #define DCI_INTC_OVRFC BIT(1) /*!< clear FIFO overrun flag */ 102 #define DCI_INTC_ESEFC BIT(2) /*!< clear embedded synchronous error flag */ 103 #define DCI_INTC_VSFC BIT(3) /*!< vsync flag clear */ 104 #define DCI_INTC_ELFC BIT(4) /*!< end of line flag clear */ 105 106 /* DCI_SC */ 107 #define DCI_SC_FS BITS(0,7) /*!< frame start code in embedded synchronous mode */ 108 #define DCI_SC_LS BITS(8,15) /*!< line start code in embedded synchronous mode */ 109 #define DCI_SC_LE BITS(16,23) /*!< line end code in embedded synchronous mode */ 110 #define DCI_SC_FE BITS(24,31) /*!< frame end code in embedded synchronous mode */ 111 112 /* DCI_SCUNMSK */ 113 #define DCI_SCUMSK_FSM BITS(0,7) /*!< frame start code unmask bits in embedded synchronous mode */ 114 #define DCI_SCUMSK_LSM BITS(8,15) /*!< line start code unmask bits in embedded synchronous mode */ 115 #define DCI_SCUMSK_LEM BITS(16,23) /*!< line end code unmask bits in embedded synchronous mode */ 116 #define DCI_SCUMSK_FEM BITS(24,31) /*!< frame end code unmask bits in embedded synchronous mode */ 117 118 /* DCI_CWSPOS */ 119 #define DCI_CWSPOS_WHSP BITS(0,13) /*!< window horizontal start position */ 120 #define DCI_CWSPOS_WVSP BITS(16,28) /*!< window vertical start position */ 121 122 /* DCI_CWSZ */ 123 #define DCI_CWSZ_WHSZ BITS(0,13) /*!< window horizontal size */ 124 #define DCI_CWSZ_WVSZ BITS(16,29) /*!< window vertical size */ 125 126 /* constants definitions */ 127 /* DCI parameter structure definitions */ 128 typedef struct 129 { 130 uint32_t capture_mode; /*!< DCI capture mode: continuous or snapshot */ 131 uint32_t clock_polarity; /*!< clock polarity selection */ 132 uint32_t hsync_polarity; /*!< horizontal polarity selection */ 133 uint32_t vsync_polarity; /*!< vertical polarity selection */ 134 uint32_t frame_rate; /*!< frame capture rate */ 135 uint32_t interface_format; /*!< digital camera interface format */ 136 }dci_parameter_struct; 137 138 #define DCI_CAPTURE_MODE_CONTINUOUS ((uint32_t)0x00000000U) /*!< continuous capture mode */ 139 #define DCI_CAPTURE_MODE_SNAPSHOT DCI_CTL_SNAP /*!< snapshot capture mode */ 140 141 #define DCI_CK_POLARITY_FALLING ((uint32_t)0x00000000U) /*!< capture at falling edge */ 142 #define DCI_CK_POLARITY_RISING DCI_CTL_CKS /*!< capture at rising edge */ 143 144 #define DCI_HSYNC_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level during blanking period */ 145 #define DCI_HSYNC_POLARITY_HIGH DCI_CTL_HPS /*!< high level during blanking period */ 146 147 #define DCI_VSYNC_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level during blanking period */ 148 #define DCI_VSYNC_POLARITY_HIGH DCI_CTL_VPS /*!< high level during blanking period*/ 149 150 #define CTL_FR(regval) (BITS(8,9)&((uint32_t)(regval) << 8U)) 151 #define DCI_FRAME_RATE_ALL CTL_FR(0) /*!< capture all frames */ 152 #define DCI_FRAME_RATE_1_2 CTL_FR(1) /*!< capture one in 2 frames */ 153 #define DCI_FRAME_RATE_1_4 CTL_FR(2) /*!< capture one in 4 frames */ 154 155 #define CTL_DCIF(regval) (BITS(10,11)&((uint32_t)(regval) << 10U)) 156 #define DCI_INTERFACE_FORMAT_8BITS CTL_DCIF(0) /*!< 8-bit data on every pixel clock */ 157 #define DCI_INTERFACE_FORMAT_10BITS CTL_DCIF(1) /*!< 10-bit data on every pixel clock */ 158 #define DCI_INTERFACE_FORMAT_12BITS CTL_DCIF(2) /*!< 12-bit data on every pixel clock */ 159 #define DCI_INTERFACE_FORMAT_14BITS CTL_DCIF(3) /*!< 14-bit data on every pixel clock */ 160 161 /* DCI interrupt constants definitions */ 162 #define DCI_INT_EF BIT(0) /*!< end of frame interrupt */ 163 #define DCI_INT_OVR BIT(1) /*!< FIFO overrun interrupt */ 164 #define DCI_INT_ESE BIT(2) /*!< embedded synchronous error interrupt */ 165 #define DCI_INT_VSYNC BIT(3) /*!< vsync interrupt */ 166 #define DCI_INT_EL BIT(4) /*!< end of line interrupt */ 167 168 /* DCI interrupt flag definitions */ 169 #define DCI_INT_FLAG_EF BIT(0) /*!< end of frame interrupt flag */ 170 #define DCI_INT_FLAG_OVR BIT(1) /*!< FIFO overrun interrupt flag */ 171 #define DCI_INT_FLAG_ESE BIT(2) /*!< embedded synchronous error interrupt flag */ 172 #define DCI_INT_FLAG_VSYNC BIT(3) /*!< vsync interrupt flag */ 173 #define DCI_INT_FLAG_EL BIT(4) /*!< end of line interrupt flag */ 174 175 /* DCI flag definitions */ 176 #define DCI_FLAG_HS DCI_STAT0_HS /*!< HS line status */ 177 #define DCI_FLAG_VS DCI_STAT0_VS /*!< VS line status */ 178 #define DCI_FLAG_FV DCI_STAT0_FV /*!< FIFO valid */ 179 #define DCI_FLAG_EF (DCI_STAT1_EFF | BIT(31)) /*!< end of frame flag */ 180 #define DCI_FLAG_OVR (DCI_STAT1_OVRF | BIT(31)) /*!< FIFO overrun flag */ 181 #define DCI_FLAG_ESE (DCI_STAT1_ESEF | BIT(31)) /*!< embedded synchronous error flag */ 182 #define DCI_FLAG_VSYNC (DCI_STAT1_VSF | BIT(31)) /*!< vsync flag */ 183 #define DCI_FLAG_EL (DCI_STAT1_ELF | BIT(31)) /*!< end of line flag */ 184 185 /* function declarations */ 186 /* initialization functions */ 187 /* DCI deinit */ 188 void dci_deinit(void); 189 /* initialize DCI registers */ 190 void dci_init(dci_parameter_struct* dci_struct); 191 192 /* enable DCI function */ 193 void dci_enable(void); 194 /* disable DCI function */ 195 void dci_disable(void); 196 /* enable DCI capture */ 197 void dci_capture_enable(void); 198 /* disable DCI capture */ 199 void dci_capture_disable(void); 200 /* enable DCI jpeg mode */ 201 void dci_jpeg_enable(void); 202 /* disable DCI jpeg mode */ 203 void dci_jpeg_disable(void); 204 205 /* function configuration */ 206 /* enable cropping window function */ 207 void dci_crop_window_enable(void); 208 /* disable cropping window function */ 209 void dci_crop_window_disable(void); 210 /* configure DCI cropping window */ 211 void dci_crop_window_config(uint16_t start_x, uint16_t start_y, uint16_t size_width, uint16_t size_height); 212 213 /* enable embedded synchronous mode */ 214 void dci_embedded_sync_enable(void); 215 /* disable embedded synchronous mode */ 216 void dci_embedded_sync_disable(void); 217 /* configure synchronous codes in embedded synchronous mode */ 218 void dci_sync_codes_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end); 219 /* configure synchronous codes unmask in embedded synchronous mode */ 220 void dci_sync_codes_unmask_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end); 221 222 /* read DCI data register */ 223 uint32_t dci_data_read(void); 224 225 /* interrupt & flag functions */ 226 /* get specified flag */ 227 FlagStatus dci_flag_get(uint32_t flag); 228 /* enable specified DCI interrupt */ 229 void dci_interrupt_enable(uint32_t interrupt); 230 /* disable specified DCI interrupt */ 231 void dci_interrupt_disable(uint32_t interrupt); 232 233 234 /* get specified interrupt flag */ 235 FlagStatus dci_interrupt_flag_get(uint32_t int_flag); 236 /* clear specified interrupt flag */ 237 void dci_interrupt_flag_clear(uint32_t int_flag); 238 239 #endif /* GD32F4XX_DCI_H */ 240
