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/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f4xx/standard_peripheral/include/
Dgd32f4xx_dci.h44 #define DCI DCI_BASE macro
47 #define DCI_CTL REG32(DCI + 0x00U) /*!< DCI control register */
48 #define DCI_STAT0 REG32(DCI + 0x04U) /*!< DCI status register 0 */
49 #define DCI_STAT1 REG32(DCI + 0x08U) /*!< DCI status register 1 */
50 #define DCI_INTEN REG32(DCI + 0x0CU) /*!< DCI interrupt enable register */
51 #define DCI_INTF REG32(DCI + 0x10U) /*!< DCI interrupt flag register */
52 #define DCI_INTC REG32(DCI + 0x14U) /*!< DCI interrupt clear register */
53 #define DCI_SC REG32(DCI + 0x18U) /*!< DCI synchronization codes register */
54 #define DCI_SCUMSK REG32(DCI + 0x1CU) /*!< DCI synchronization codes unmask register…
55 #define DCI_CWSPOS REG32(DCI + 0x20U) /*!< DCI cropping window start position regist…
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