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Searched refs:CTL1_CPH (Results 1 – 8 of 8) sorted by relevance

/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32vf103/standard_peripheral/include/
Dgd32vf103_usart.h233 #define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9)) macro
234 #define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition…
235 #define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transitio…
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/standard_peripheral/include/
Dgd32f403_usart.h281 #define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9)) macro
282 #define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition …
283 #define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition…
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/standard_peripheral/include/
Dgd32e10x_usart.h290 #define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9)) macro
291 #define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition …
292 #define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition…
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f4xx/standard_peripheral/include/
Dgd32f4xx_usart.h298 #define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9)) macro
299 #define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition …
300 #define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition…
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32a50x/standard_peripheral/include/
Dgd32a50x_usart.h355 #define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9)) macro
356 #define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is…
357 #define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition i…
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f3x0/standard_peripheral/include/
Dgd32f3x0_usart.h354 #define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9)) macro
355 #define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is…
356 #define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition i…
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32l23x/standard_peripheral/include/
Dgd32l23x_usart.h360 #define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9)) macro
361 #define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is…
362 #define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition i…
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/include/
Dgd32e50x_usart.h551 #define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9)) macro
552 #define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition …
553 #define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition…