1 /*! 2 \file gd32f4xx_ctc.h 3 \brief definitions for the CTC 4 5 \version 2016-08-15, V1.0.0, firmware for GD32F4xx 6 \version 2018-12-12, V2.0.0, firmware for GD32F4xx 7 \version 2020-09-30, V2.1.0, firmware for GD32F4xx 8 \version 2022-03-09, V3.0.0, firmware for GD32F4xx 9 */ 10 11 /* 12 Copyright (c) 2022, GigaDevice Semiconductor Inc. 13 14 Redistribution and use in source and binary forms, with or without modification, 15 are permitted provided that the following conditions are met: 16 17 1. Redistributions of source code must retain the above copyright notice, this 18 list of conditions and the following disclaimer. 19 2. Redistributions in binary form must reproduce the above copyright notice, 20 this list of conditions and the following disclaimer in the documentation 21 and/or other materials provided with the distribution. 22 3. Neither the name of the copyright holder nor the names of its contributors 23 may be used to endorse or promote products derived from this software without 24 specific prior written permission. 25 26 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 28 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 33 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 35 OF SUCH DAMAGE. 36 */ 37 38 #ifndef GD32F4XX_CTC_H 39 #define GD32F4XX_CTC_H 40 41 #include "gd32f4xx.h" 42 43 /* CTC definitions */ 44 #define CTC CTC_BASE 45 46 /* registers definitions */ 47 #define CTC_CTL0 REG32((CTC) + 0x00U) /*!< CTC control register 0 */ 48 #define CTC_CTL1 REG32((CTC) + 0x04U) /*!< CTC control register 1 */ 49 #define CTC_STAT REG32((CTC) + 0x08U) /*!< CTC status register */ 50 #define CTC_INTC REG32((CTC) + 0x0CU) /*!< CTC interrupt clear register */ 51 52 /* bits definitions */ 53 /* CTC_CTL0 */ 54 #define CTC_CTL0_CKOKIE BIT(0) /*!< clock trim OK(CKOKIF) interrupt enable */ 55 #define CTC_CTL0_CKWARNIE BIT(1) /*!< clock trim warning(CKWARNIF) interrupt enable */ 56 #define CTC_CTL0_ERRIE BIT(2) /*!< error(ERRIF) interrupt enable */ 57 #define CTC_CTL0_EREFIE BIT(3) /*!< EREFIF interrupt enable */ 58 #define CTC_CTL0_CNTEN BIT(5) /*!< CTC counter enable */ 59 #define CTC_CTL0_AUTOTRIM BIT(6) /*!< hardware automatically trim mode */ 60 #define CTC_CTL0_SWREFPUL BIT(7) /*!< software reference source sync pulse */ 61 #define CTC_CTL0_TRIMVALUE BITS(8,13) /*!< IRC48M trim value */ 62 63 /* CTC_CTL1 */ 64 #define CTC_CTL1_RLVALUE BITS(0,15) /*!< CTC counter reload value */ 65 #define CTC_CTL1_CKLIM BITS(16,23) /*!< clock trim base limit value */ 66 #define CTC_CTL1_REFPSC BITS(24,26) /*!< reference signal source prescaler */ 67 #define CTC_CTL1_REFSEL BITS(28,29) /*!< reference signal source selection */ 68 #define CTC_CTL1_USBSOFSEL BIT(30) /*!< USBFS or USBHS SOF signal selection */ 69 #define CTC_CTL1_REFPOL BIT(31) /*!< reference signal source polarity */ 70 71 /* CTC_STAT */ 72 #define CTC_STAT_CKOKIF BIT(0) /*!< clock trim OK interrupt flag */ 73 #define CTC_STAT_CKWARNIF BIT(1) /*!< clock trim warning interrupt flag */ 74 #define CTC_STAT_ERRIF BIT(2) /*!< error interrupt flag */ 75 #define CTC_STAT_EREFIF BIT(3) /*!< expect reference interrupt flag */ 76 #define CTC_STAT_CKERR BIT(8) /*!< clock trim error bit */ 77 #define CTC_STAT_REFMISS BIT(9) /*!< reference sync pulse miss */ 78 #define CTC_STAT_TRIMERR BIT(10) /*!< trim value error bit */ 79 #define CTC_STAT_REFDIR BIT(15) /*!< CTC trim counter direction when reference sync pulse occurred */ 80 #define CTC_STAT_REFCAP BITS(16,31) /*!< CTC counter capture when reference sync pulse occurred */ 81 82 /* CTC_INTC */ 83 #define CTC_INTC_CKOKIC BIT(0) /*!< CKOKIF interrupt clear bit */ 84 #define CTC_INTC_CKWARNIC BIT(1) /*!< CKWARNIF interrupt clear bit */ 85 #define CTC_INTC_ERRIC BIT(2) /*!< ERRIF interrupt clear bit */ 86 #define CTC_INTC_EREFIC BIT(3) /*!< EREFIF interrupt clear bit */ 87 88 /* constants definitions */ 89 /* hardware automatically trim mode definitions */ 90 #define CTC_HARDWARE_TRIM_MODE_ENABLE CTC_CTL0_AUTOTRIM /*!< hardware automatically trim mode enable*/ 91 #define CTC_HARDWARE_TRIM_MODE_DISABLE ((uint32_t)0x00000000U) /*!< hardware automatically trim mode disable*/ 92 93 /* reference signal source polarity definitions */ 94 #define CTC_REFSOURCE_POLARITY_FALLING CTC_CTL1_REFPOL /*!< reference signal source polarity is falling edge*/ 95 #define CTC_REFSOURCE_POLARITY_RISING ((uint32_t)0x00000000U) /*!< reference signal source polarity is rising edge*/ 96 97 /* USBFS or USBHS SOF signal selection definitions */ 98 #define CTC_USBSOFSEL_USBHS CTC_CTL1_USBSOFSEL /*!< USBHS SOF signal is selected*/ 99 #define CTC_USBSOFSEL_USBFS ((uint32_t)0x00000000U) /*!< USBFS SOF signal is selected*/ 100 101 /* reference signal source selection definitions */ 102 #define CTL1_REFSEL(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) 103 #define CTC_REFSOURCE_GPIO CTL1_REFSEL(0) /*!< GPIO is selected */ 104 #define CTC_REFSOURCE_LXTAL CTL1_REFSEL(1) /*!< LXTAL is clock selected */ 105 #define CTC_REFSOURCE_USBSOF CTL1_REFSEL(2) /*!< USBSOF is selected */ 106 107 /* reference signal source prescaler definitions */ 108 #define CTL1_REFPSC(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) 109 #define CTC_REFSOURCE_PSC_OFF CTL1_REFPSC(0) /*!< reference signal not divided */ 110 #define CTC_REFSOURCE_PSC_DIV2 CTL1_REFPSC(1) /*!< reference signal divided by 2 */ 111 #define CTC_REFSOURCE_PSC_DIV4 CTL1_REFPSC(2) /*!< reference signal divided by 4 */ 112 #define CTC_REFSOURCE_PSC_DIV8 CTL1_REFPSC(3) /*!< reference signal divided by 8 */ 113 #define CTC_REFSOURCE_PSC_DIV16 CTL1_REFPSC(4) /*!< reference signal divided by 16 */ 114 #define CTC_REFSOURCE_PSC_DIV32 CTL1_REFPSC(5) /*!< reference signal divided by 32 */ 115 #define CTC_REFSOURCE_PSC_DIV64 CTL1_REFPSC(6) /*!< reference signal divided by 64 */ 116 #define CTC_REFSOURCE_PSC_DIV128 CTL1_REFPSC(7) /*!< reference signal divided by 128 */ 117 118 /* CTC interrupt enable definitions */ 119 #define CTC_INT_CKOK CTC_CTL0_CKOKIE /*!< clock trim OK interrupt enable */ 120 #define CTC_INT_CKWARN CTC_CTL0_CKWARNIE /*!< clock trim warning interrupt enable */ 121 #define CTC_INT_ERR CTC_CTL0_ERRIE /*!< error interrupt enable */ 122 #define CTC_INT_EREF CTC_CTL0_EREFIE /*!< expect reference interrupt enable */ 123 124 /* CTC interrupt source definitions */ 125 #define CTC_INT_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK interrupt flag */ 126 #define CTC_INT_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning interrupt flag */ 127 #define CTC_INT_FLAG_ERR CTC_STAT_ERRIF /*!< error interrupt flag */ 128 #define CTC_INT_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference interrupt flag */ 129 #define CTC_INT_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */ 130 #define CTC_INT_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */ 131 #define CTC_INT_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error */ 132 133 /* CTC flag definitions */ 134 #define CTC_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK flag */ 135 #define CTC_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning flag */ 136 #define CTC_FLAG_ERR CTC_STAT_ERRIF /*!< error flag */ 137 #define CTC_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference flag */ 138 #define CTC_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */ 139 #define CTC_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */ 140 #define CTC_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error bit */ 141 142 /* function declarations */ 143 /* reset ctc clock trim controller */ 144 void ctc_deinit(void); 145 /* enable CTC trim counter */ 146 void ctc_counter_enable(void); 147 /* disable CTC trim counter */ 148 void ctc_counter_disable(void); 149 150 /* configure the IRC48M trim value */ 151 void ctc_irc48m_trim_value_config(uint8_t trim_value); 152 /* generate software reference source sync pulse */ 153 void ctc_software_refsource_pulse_generate(void); 154 /* configure hardware automatically trim mode */ 155 void ctc_hardware_trim_mode_config(uint32_t hardmode); 156 157 /* configure reference signal source polarity */ 158 void ctc_refsource_polarity_config(uint32_t polarity); 159 /* select USBFS or USBHS SOF signal */ 160 void ctc_usbsof_signal_select(uint32_t usbsof); 161 /* select reference signal source */ 162 void ctc_refsource_signal_select(uint32_t refs); 163 /* configure reference signal source prescaler */ 164 void ctc_refsource_prescaler_config(uint32_t prescaler); 165 /* configure clock trim base limit value */ 166 void ctc_clock_limit_value_config(uint8_t limit_value); 167 /* configure CTC counter reload value */ 168 void ctc_counter_reload_value_config(uint16_t reload_value); 169 170 /* read CTC counter capture value when reference sync pulse occurred */ 171 uint16_t ctc_counter_capture_value_read(void); 172 /* read CTC trim counter direction when reference sync pulse occurred */ 173 FlagStatus ctc_counter_direction_read(void); 174 /* read CTC counter reload value */ 175 uint16_t ctc_counter_reload_value_read(void); 176 /* read the IRC48M trim value */ 177 uint8_t ctc_irc48m_trim_value_read(void); 178 179 /* interrupt & flag functions */ 180 /* enable the CTC interrupt */ 181 void ctc_interrupt_enable(uint32_t interrupt); 182 /* disable the CTC interrupt */ 183 void ctc_interrupt_disable(uint32_t interrupt); 184 /* get CTC interrupt flag */ 185 FlagStatus ctc_interrupt_flag_get(uint32_t int_flag); 186 /* clear CTC interrupt flag */ 187 void ctc_interrupt_flag_clear(uint32_t int_flag); 188 /* get CTC flag */ 189 FlagStatus ctc_flag_get(uint32_t flag); 190 /* clear CTC flag */ 191 void ctc_flag_clear(uint32_t flag); 192 193 #endif /* GD32F4XX_CTC_H */ 194
