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Searched refs:CTC_CTL1_CKLIM (Results 1 – 12 of 12) sorted by relevance

/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32l23x/standard_peripheral/source/
Dgd32l23x_ctc.c182 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_CKLIM); in ctc_clock_limit_value_config()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32l23x/standard_peripheral/include/
Dgd32l23x_ctc.h62 #define CTC_CTL1_CKLIM BITS(16,23) /*!< clock trim base limit value */ macro
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/standard_peripheral/include/
Dgd32e10x_ctc.h65 #define CTC_CTL1_CKLIM BITS(16,23) /*!< clock trim base limit value */ macro
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/source/
Dgd32e50x_ctc.c185 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_CKLIM); in ctc_clock_limit_value_config()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/standard_peripheral/source/
Dgd32f403_ctc.c184 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_CKLIM); in ctc_clock_limit_value_config()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f3x0/standard_peripheral/source/
Dgd32f3x0_ctc.c115 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_CKLIM); in ctc_clock_limit_value_config()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/standard_peripheral/include/
Dgd32f403_ctc.h64 #define CTC_CTL1_CKLIM BITS(16,23) /*!< clock trim base limit value */ macro
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/include/
Dgd32e50x_ctc.h64 #define CTC_CTL1_CKLIM BITS(16,23) /*!< clock trim base limit value */ macro
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/standard_peripheral/source/
Dgd32e10x_ctc.c184 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_CKLIM); in ctc_clock_limit_value_config()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f4xx/standard_peripheral/source/
Dgd32f4xx_ctc.c199 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_CKLIM); in ctc_clock_limit_value_config()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f4xx/standard_peripheral/include/
Dgd32f4xx_ctc.h65 #define CTC_CTL1_CKLIM BITS(16,23) /*!< clock trim base limit value */ macro
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f3x0/standard_peripheral/include/
Dgd32f3x0_ctc.h64 #define CTC_CTL1_CKLIM BITS(16,23) /*!< clock trim base limit value */ macro