CTC_CTL0_SWREFPUL (reference) in projects: hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0

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Searched refs:CTC_CTL0_SWREFPUL (Results 1 – 12 of 12) sorted by relevance

/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32l23x/standard_peripheral/source/
D	gd32l23x_ctc.c	`103 CTC_CTL0 \|= (uint32_t)CTC_CTL0_SWREFPUL; in ctc_software_refsource_pulse_generate()`
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32l23x/standard_peripheral/include/
D	gd32l23x_ctc.h	`57 #define CTC_CTL0_SWREFPUL BIT(7) /*!< software reference source sync … macro`
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/standard_peripheral/include/
D	gd32e10x_ctc.h	`60 #define CTC_CTL0_SWREFPUL BIT(7) /*!< software reference source sync … macro`
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/source/
D	gd32e50x_ctc.c	`107 CTC_CTL0 \|= (uint32_t)CTC_CTL0_SWREFPUL; in ctc_software_refsource_pulse_generate()`
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/standard_peripheral/source/
D	gd32f403_ctc.c	`105 CTC_CTL0 \|= (uint32_t)CTC_CTL0_SWREFPUL; in ctc_software_refsource_pulse_generate()`
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f3x0/standard_peripheral/source/
D	gd32f3x0_ctc.c	`177 CTC_CTL0 \|= (uint32_t)CTC_CTL0_SWREFPUL; in ctc_software_refsource_pulse_generate()`
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/standard_peripheral/include/
D	gd32f403_ctc.h	`59 #define CTC_CTL0_SWREFPUL BIT(7) /*!< software reference source sync … macro`
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/include/
D	gd32e50x_ctc.h	`59 #define CTC_CTL0_SWREFPUL BIT(7) /*!< software reference source sync … macro`
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/standard_peripheral/source/
D	gd32e10x_ctc.c	`106 CTC_CTL0 \|= (uint32_t)CTC_CTL0_SWREFPUL; in ctc_software_refsource_pulse_generate()`
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f4xx/standard_peripheral/source/
D	gd32f4xx_ctc.c	`106 CTC_CTL0 \|= (uint32_t)CTC_CTL0_SWREFPUL; in ctc_software_refsource_pulse_generate()`
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f4xx/standard_peripheral/include/
D	gd32f4xx_ctc.h	`60 #define CTC_CTL0_SWREFPUL BIT(7) /*!< software reference source sync … macro`
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f3x0/standard_peripheral/include/
D	gd32f3x0_ctc.h	`59 #define CTC_CTL0_SWREFPUL BIT(7) /*!< software reference source sync … macro`

TraceRecorderSource-2.7.6
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Zephyr-Core-3.5.0
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babblesim_ext_2G4_channel_multiatt-3.7.0-3.6.0-3.5.0
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babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
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