Searched refs:CTC_CTL0 (Results 1 – 12 of 12) sorted by relevance
66 CTC_CTL0 |= (uint32_t)CTC_CTL0_CNTEN; in ctc_counter_enable()77 CTC_CTL0 &= (uint32_t)(~CTC_CTL0_CNTEN); in ctc_counter_disable()90 CTC_CTL0 &= (~(uint32_t)CTC_CTL0_TRIMVALUE); in ctc_irc48m_trim_value_config()92 CTC_CTL0 |= ((uint32_t)trim_value << CTC_TRIM_VALUE_OFFSET); in ctc_irc48m_trim_value_config()103 CTC_CTL0 |= (uint32_t)CTC_CTL0_SWREFPUL; in ctc_software_refsource_pulse_generate()117 CTC_CTL0 &= (uint32_t)(~CTC_CTL0_AUTOTRIM); in ctc_hardware_trim_mode_config()118 CTC_CTL0 |= (uint32_t)hardmode; in ctc_hardware_trim_mode_config()251 trim_value = (uint8_t)((CTC_CTL0 & CTC_CTL0_TRIMVALUE) >> CTC_TRIMVALUE_OFFSET); in ctc_irc48m_trim_value_read()268 CTC_CTL0 |= (uint32_t)interrupt; in ctc_interrupt_enable()284 CTC_CTL0 &= (uint32_t)(~interrupt); in ctc_interrupt_disable()[all …]
70 CTC_CTL0 |= (uint32_t)CTC_CTL0_CNTEN; in ctc_counter_enable()81 CTC_CTL0 &= (uint32_t)(~CTC_CTL0_CNTEN); in ctc_counter_disable()94 CTC_CTL0 &= (~(uint32_t)CTC_CTL0_TRIMVALUE); in ctc_irc48m_trim_value_config()96 CTC_CTL0 |= ((uint32_t)trim_value << CTC_TRIM_VALUE_OFFSET); in ctc_irc48m_trim_value_config()107 CTC_CTL0 |= (uint32_t)CTC_CTL0_SWREFPUL; in ctc_software_refsource_pulse_generate()121 CTC_CTL0 &= (uint32_t)(~CTC_CTL0_AUTOTRIM); in ctc_hardware_trim_mode_config()122 CTC_CTL0 |= (uint32_t)hardmode; in ctc_hardware_trim_mode_config()254 trim_value = (uint8_t)((CTC_CTL0 & CTC_CTL0_TRIMVALUE) >> CTC_TRIMVALUE_OFFSET); in ctc_irc48m_trim_value_read()317 CTC_CTL0 |= (uint32_t)interrupt; in ctc_interrupt_enable()333 CTC_CTL0 &= (uint32_t)(~interrupt); in ctc_interrupt_disable()[all …]
68 CTC_CTL0 |= (uint32_t)CTC_CTL0_CNTEN; in ctc_counter_enable()79 CTC_CTL0 &= (uint32_t)(~CTC_CTL0_CNTEN); in ctc_counter_disable()92 CTC_CTL0 &= (~(uint32_t)CTC_CTL0_TRIMVALUE); in ctc_irc48m_trim_value_config()94 CTC_CTL0 |= ((uint32_t)trim_value << CTC_TRIM_VALUE_OFFSET); in ctc_irc48m_trim_value_config()105 CTC_CTL0 |= (uint32_t)CTC_CTL0_SWREFPUL; in ctc_software_refsource_pulse_generate()119 CTC_CTL0 &= (uint32_t)(~CTC_CTL0_AUTOTRIM); in ctc_hardware_trim_mode_config()120 CTC_CTL0 |= (uint32_t)hardmode; in ctc_hardware_trim_mode_config()253 trim_value = (uint8_t)((CTC_CTL0 & CTC_CTL0_TRIMVALUE) >> CTC_TRIMVALUE_OFFSET); in ctc_irc48m_trim_value_read()270 CTC_CTL0 |= (uint32_t)interrupt; in ctc_interrupt_enable()286 CTC_CTL0 &= (uint32_t)(~interrupt); in ctc_interrupt_disable()[all …]
140 CTC_CTL0 |= (uint32_t)CTC_CTL0_CNTEN; in ctc_counter_enable()151 CTC_CTL0 &= (uint32_t)(~CTC_CTL0_CNTEN); in ctc_counter_disable()164 CTC_CTL0 &= (~(uint32_t)CTC_CTL0_TRIMVALUE); in ctc_irc48m_trim_value_config()166 CTC_CTL0 |= CTL0_TRIMVALUE(trim_value); in ctc_irc48m_trim_value_config()177 CTC_CTL0 |= (uint32_t)CTC_CTL0_SWREFPUL; in ctc_software_refsource_pulse_generate()191 CTC_CTL0 &= (uint32_t)(~CTC_CTL0_AUTOTRIM); in ctc_hardware_trim_mode_config()192 CTC_CTL0 |= (uint32_t)hardmode; in ctc_hardware_trim_mode_config()247 trim_value = (uint8_t)GET_CTL0_TRIMVALUE(CTC_CTL0); in ctc_irc48m_trim_value_read()264 CTC_CTL0 |= (uint32_t)interrupt; in ctc_interrupt_enable()280 CTC_CTL0 &= (uint32_t)(~(interrupt)); in ctc_interrupt_disable()[all …]
69 CTC_CTL0 |= (uint32_t)CTC_CTL0_CNTEN; in ctc_counter_enable()80 CTC_CTL0 &= (uint32_t)(~CTC_CTL0_CNTEN); in ctc_counter_disable()93 CTC_CTL0 &= (~(uint32_t)CTC_CTL0_TRIMVALUE); in ctc_irc48m_trim_value_config()95 CTC_CTL0 |= ((uint32_t)trim_value << CTC_TRIM_VALUE_OFFSET); in ctc_irc48m_trim_value_config()106 CTC_CTL0 |= (uint32_t)CTC_CTL0_SWREFPUL; in ctc_software_refsource_pulse_generate()120 CTC_CTL0 &= (uint32_t)(~CTC_CTL0_AUTOTRIM); in ctc_hardware_trim_mode_config()121 CTC_CTL0 |= (uint32_t)hardmode; in ctc_hardware_trim_mode_config()253 trim_value = (uint8_t)((CTC_CTL0 & CTC_CTL0_TRIMVALUE) >> CTC_TRIMVALUE_OFFSET); in ctc_irc48m_trim_value_read()270 CTC_CTL0 |= (uint32_t)interrupt; in ctc_interrupt_enable()286 CTC_CTL0 &= (uint32_t)(~interrupt); in ctc_interrupt_disable()[all …]
69 CTC_CTL0 |= (uint32_t)CTC_CTL0_CNTEN; in ctc_counter_enable()80 CTC_CTL0 &= (uint32_t)(~CTC_CTL0_CNTEN); in ctc_counter_disable()93 CTC_CTL0 &= (~(uint32_t)CTC_CTL0_TRIMVALUE); in ctc_irc48m_trim_value_config()95 CTC_CTL0 |= ((uint32_t)trim_value << CTC_TRIM_VALUE_OFFSET); in ctc_irc48m_trim_value_config()106 CTC_CTL0 |= (uint32_t)CTC_CTL0_SWREFPUL; in ctc_software_refsource_pulse_generate()120 CTC_CTL0 &= (uint32_t)(~CTC_CTL0_AUTOTRIM); in ctc_hardware_trim_mode_config()121 CTC_CTL0 |= (uint32_t)hardmode; in ctc_hardware_trim_mode_config()268 trim_value = (uint8_t)((CTC_CTL0 & CTC_CTL0_TRIMVALUE) >> CTC_TRIMVALUE_OFFSET); in ctc_irc48m_trim_value_read()285 CTC_CTL0 |= (uint32_t)interrupt; in ctc_interrupt_enable()301 CTC_CTL0 &= (uint32_t)(~interrupt); in ctc_interrupt_disable()[all …]
44 #define CTC_CTL0 REG32((CTC) + 0x00U) /*!< CTC control register 0 */ macro
47 #define CTC_CTL0 REG32((CTC) + 0x00U) /*!< CTC control register 0 */ macro
46 #define CTC_CTL0 REG32((CTC) + 0x00U) /*!< CTC control register 0 */ macro
46 #define CTC_CTL0 REG32(CTC + 0x00000000U) /*!< CTC control register 0 */ macro