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Searched refs:CTC (Results 1 – 6 of 6) sorted by relevance

/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32l23x/standard_peripheral/include/
Dgd32l23x_ctc.h41 #define CTC CTC_BASE macro
44 #define CTC_CTL0 REG32((CTC) + 0x00U) /*!< CTC control register 0 */
45 #define CTC_CTL1 REG32((CTC) + 0x04U) /*!< CTC control register 1 */
46 #define CTC_STAT REG32((CTC) + 0x08U) /*!< CTC status register */
47 #define CTC_INTC REG32((CTC) + 0x0CU) /*!< CTC interrupt clear register */
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/standard_peripheral/include/
Dgd32e10x_ctc.h44 #define CTC CTC_BASE macro
47 #define CTC_CTL0 REG32((CTC) + 0x00U) /*!< CTC control register 0 */
48 #define CTC_CTL1 REG32((CTC) + 0x04U) /*!< CTC control register 1 */
49 #define CTC_STAT REG32((CTC) + 0x08U) /*!< CTC status register */
50 #define CTC_INTC REG32((CTC) + 0x0CU) /*!< CTC interrupt clear register */
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/standard_peripheral/include/
Dgd32f403_ctc.h43 #define CTC CTC_BASE macro
46 #define CTC_CTL0 REG32((CTC) + 0x00U) /*!< CTC control register 0 */
47 #define CTC_CTL1 REG32((CTC) + 0x04U) /*!< CTC control register 1 */
48 #define CTC_STAT REG32((CTC) + 0x08U) /*!< CTC status register */
49 #define CTC_INTC REG32((CTC) + 0x0CU) /*!< CTC interrupt clear register */
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/include/
Dgd32e50x_ctc.h43 #define CTC CTC_BASE macro
46 #define CTC_CTL0 REG32((CTC) + 0x00U) /*!< CTC control register 0 */
47 #define CTC_CTL1 REG32((CTC) + 0x04U) /*!< CTC control register 1 */
48 #define CTC_STAT REG32((CTC) + 0x08U) /*!< CTC status register */
49 #define CTC_INTC REG32((CTC) + 0x0CU) /*!< CTC interrupt clear register */
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f4xx/standard_peripheral/include/
Dgd32f4xx_ctc.h44 #define CTC CTC_BASE macro
47 #define CTC_CTL0 REG32((CTC) + 0x00U) /*!< CTC control register 0 */
48 #define CTC_CTL1 REG32((CTC) + 0x04U) /*!< CTC control register 1 */
49 #define CTC_STAT REG32((CTC) + 0x08U) /*!< CTC status register */
50 #define CTC_INTC REG32((CTC) + 0x0CU) /*!< CTC interrupt clear register */
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f3x0/standard_peripheral/include/
Dgd32f3x0_ctc.h43 #define CTC CTC_BASE macro
46 #define CTC_CTL0 REG32(CTC + 0x00000000U) /*!< CTC control register 0 */
47 #define CTC_CTL1 REG32(CTC + 0x00000004U) /*!< CTC control register 1 */
48 #define CTC_STAT REG32(CTC + 0x00000008U) /*!< CTC status register */
49 #define CTC_INTC REG32(CTC + 0x0000000CU) /*!< CTC interrupt clear register */