1 /*! 2 \file gd32e50x_cmp.h 3 \brief definitions for the CMP 4 5 \version 2020-03-10, V1.0.0, firmware for GD32E50x 6 \version 2020-08-26, V1.1.0, firmware for GD32E50x 7 \version 2021-03-23, V1.2.0, firmware for GD32E50x 8 \version 2021-05-19, V1.2.1, firmware for GD32E50x 9 */ 10 11 /* 12 Copyright (c) 2021, GigaDevice Semiconductor Inc. 13 14 Redistribution and use in source and binary forms, with or without modification, 15 are permitted provided that the following conditions are met: 16 17 1. Redistributions of source code must retain the above copyright notice, this 18 list of conditions and the following disclaimer. 19 2. Redistributions in binary form must reproduce the above copyright notice, 20 this list of conditions and the following disclaimer in the documentation 21 and/or other materials provided with the distribution. 22 3. Neither the name of the copyright holder nor the names of its contributors 23 may be used to endorse or promote products derived from this software without 24 specific prior written permission. 25 26 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 28 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 33 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 35 OF SUCH DAMAGE. 36 */ 37 38 #ifndef GD32E50X_CMP_H 39 #define GD32E50X_CMP_H 40 41 #include "gd32e50x.h" 42 43 /* CMP definitions */ 44 #define CMP CMP_BASE /*!< CMP base address */ 45 46 /* registers definitions */ 47 #define CMP_CS(CMPx) REG32((CMP) + 0x00000020U + (CMPx) * 0x00000008U) 48 49 50 /* CMPx_CS bits definitions */ 51 #define CMP_CS_CMPEN BIT(0) /*!< CMPx enable */ 52 #define CMP_CS_CMPMSEL BITS(4,6) /*!< CMPx_IM input selection */ 53 #define CMP_CS_CMPOSEL BITS(10,13) /*!< CMPx output selection */ 54 #define CMP_CS_CMPPL BIT(15) /*!< polarity of CMPx output */ 55 #define CMP_CS_CMPBLK BITS(18,20) /*!< CMPx output blanking source */ 56 #define CMP_CS_CMPMSEL_3 BIT(22) /*!< bit3 of CMPx_CS_CMP1MSEL */ 57 #define CMP_CS_CMPO BIT(30) /*!< CMPx output */ 58 #define CMP_CS_CMPLK BIT(31) /*!< CMPx lock */ 59 60 /* CMP1_CS bits definitions */ 61 #define CMP1_CS_CMP1EN BIT(0) /*!< CMP1 enable */ 62 #define CMP1_CS_CMP1MSEL BITS(4,6) /*!< CMP1_IM input selection */ 63 #define CMP1_CS_CMP1OSEL BITS(10,13) /*!< CMP1 output selection */ 64 #define CMP1_CS_CMP1PL BIT(15) /*!< polarity of CMP1 output */ 65 #define CMP1_CS_CMP1BLK BITS(18,20) /*!< CMP1 output blanking source */ 66 #define CMP1_CS_CMP1MSEL_3 BIT(22) /*!< bit3 of CMP1_CS_CMP1MSEL */ 67 #define CMP1_CS_CMP1O BIT(30) /*!< CMP1 output */ 68 #define CMP1_CS_CMP1LK BIT(31) /*!< CMP1 lock */ 69 70 /* CMP3_CS bits definitions */ 71 #define CMP3_CS_CMP3EN BIT(0) /*!< CMP3 enable */ 72 #define CMP3_CS_CMP3MSEL BITS(4,6) /*!< CMP3_IM input selection */ 73 #define CMP3_CS_CMP3OSEL BITS(10,13) /*!< CMP3 output selection */ 74 #define CMP3_CS_CMP3PL BIT(15) /*!< polarity of CMP3 output */ 75 #define CMP3_CS_CMP3BLK BITS(18,20) /*!< CMP3 output blanking source */ 76 #define CMP3_CS_CMP3MSEL_3 BIT(22) /*!< bit3 of CMP3_CS_CMP3MSEL */ 77 #define CMP3_CS_CMP3O BIT(30) /*!< CMP3 output */ 78 #define CMP3_CS_CMP3LK BIT(31) /*!< CMP3 lock */ 79 80 /* CMP5_CS bits definitions */ 81 #define CMP5_CS_CMP5EN BIT(0) /*!< CMP5 enable */ 82 #define CMP5_CS_CMP5MSEL BITS(4,6) /*!< CMP5_IM input selection */ 83 #define CMP5_CS_CMP5OSEL BITS(10,13) /*!< CMP5 output selection */ 84 #define CMP5_CS_CMP5PL BIT(15) /*!< polarity of CMP5 output */ 85 #define CMP5_CS_CMP5BLK BITS(18,20) /*!< CMP5 output blanking source */ 86 #define CMP5_CS_CMP5MSEL_3 BIT(22) /*!< bit3 of CMP5_CS_CMP5MSEL */ 87 #define CMP5_CS_CMP5O BIT(30) /*!< CMP5 output */ 88 #define CMP5_CS_CMP5LK BIT(31) /*!< CMP5 lock */ 89 90 /* consts definitions */ 91 /* CMP units */ 92 typedef enum 93 { 94 CMP1, /*!< Cmoparator 1 */ 95 CMP3, /*!< Cmoparator 3 */ 96 CMP5 /*!< Cmoparator 5 */ 97 }cmp_enum; 98 99 /* inverting input */ 100 typedef enum 101 { 102 CMP_1_4VREFINT = 0, /*!< VREFINT /4 input */ 103 CMP_1_2VREFINT, /*!< VREFINT /2 input */ 104 CMP_3_4VREFINT, /*!< VREFINT *3/4 input */ 105 CMP_VREFINT, /*!< VREFINT input */ 106 CMP_PA4, /*!< PA4 input */ 107 CMP_PA5, /*!< PA5 input */ 108 CMP_PA2, /*!< PA2 input */ 109 CMP_PB_2_15 /*!< PB2 or PB15 input */ 110 }inverting_input_enum; 111 112 /* output */ 113 typedef enum 114 { 115 CMP_OUTPUT_NONE = 0x0U, /*!< output no selection */ 116 CMP_OUTPUT_TIMER0_BKIN = 0x1U, /*!< TIMER 0 break input */ 117 CMP_OUTPUT_TIMER2IC2_TIMER1IC1= 0x6U, /*!< TIMER 2 channel2 or TIMER 1 channel1 input */ 118 CMP_OUTPUT_TIMER0IC0 = 0x7U, /*!< TIMER 0 channel0 input */ 119 CMP_OUTPUT_TIMER1IC3 = 0x08U, /*!< TIMER 1 channel3 input */ 120 CMP_OUTPUT_TIMER2IC0 = 0xAU, /*!< TIMER 2 channel0 input*/ 121 }cmp_output_enum; 122 123 typedef enum 124 { 125 CMP_OUTPUTBLANK_NONE = 0x0U, /*!< output no blanking */ 126 CMP_OUTPUTBLANK_TIMER2_IC3 = 0x1U, /*!< select TIMER2_CH3 as blanking source */ 127 CMP_OUTPUTBLANK_TIMER1IC2 = 0x2U, /*!< select TIMER1_CH2 as blanking source */ 128 CMP_OUTPUTBLANK_TIMER2IC2_TIMER1IC3 = 0x3U, /*!< select TIMER2_CH2 or TIMER1_CH3 as blanking source */ 129 }cmp_outputblank_enum; 130 131 /* comparator inverting input */ 132 #define CS_CMPMSEL(regval) (BITS(4,6) & ((uint32_t)(regval) << 4)) 133 #define CS_CMPMSEL_1_4VREFINT CS_CMPMSEL(0) /*!< CMP inverting input 1/4 Vrefint */ 134 #define CS_CMPMSEL_1_2VREFINT CS_CMPMSEL(1) /*!< CMP inverting input 1/2 Vrefint */ 135 #define CS_CMPMSEL_3_4VREFINT CS_CMPMSEL(2) /*!< CMP inverting input 3/4 Vrefint */ 136 #define CS_CMPMSEL_VREFINT CS_CMPMSEL(3) /*!< CMP inverting input Vrefint */ 137 #define CS_CMPMSEL_PA4 CS_CMPMSEL(4) /*!< CMP inverting input PA4 */ 138 #define CS_CMPMSEL_PA5 CS_CMPMSEL(5) /*!< CMP inverting input PA5 */ 139 #define CS_CMPMSEL_PA2 CS_CMPMSEL(6) /*!< CMP inverting input PA2 */ 140 #define CS_CMPMSEL_PB_2_15 CS_CMPMSEL(7) /*!< CMP inverting input PB2 or PB15 */ 141 142 /* CMP output */ 143 #define CS_CMPOSEL(regval) (BITS(10,13) & ((uint32_t)(regval) << 10)) 144 #define CS_CMPOSEL_OUTPUT_NONE CS_CMPOSEL(0) /*!< CMP output none */ 145 #define CS_CMPOSEL_OUTPUT_TIMER0_BKIN CS_CMPOSEL(1) /*!< CMP output TIMER 0 break input */ 146 #define CS_CMPOSEL_OUTPUT_TIMER2IC2_TIMER1IC1 CS_CMPOSEL(6) /*!< TIMER 2 channel 2 or TIMER 1 channel 1 input capture */ 147 #define CS_CMPOSEL_OUTPUT_TIMER0IC0 CS_CMPOSEL(7) /*!< CMP output TIMER 0 channle 1 input capture */ 148 #define CS_CMPOSEL_OUTPUT_TIMER1IC3 CS_CMPOSEL(8) /*!< CMP output TIMER 1 channle 3 input capture */ 149 #define CS_CMPOSEL_OUTPUT_TIMER2IC0 CS_CMPOSEL(10) /*!< CMP output TIMER 2 channle 0 input capture */ 150 151 /* output polarity of comparator */ 152 #define CMP_OUTPUT_POLARITY_INVERTED ((uint32_t)0x00000001) /*!< output is inverted */ 153 #define CMP_OUTPUT_POLARITY_NOINVERTED ((uint32_t)0x00000000) /*!< output is not inverted */ 154 155 /* CMP output blanking source */ 156 #define CS_CMPMBLK(regval) (BITS(18,20) & ((uint32_t)(regval) << 18)) 157 #define CS_CMPMBLK_OUTPUTBLANK_NONE CS_CMPMBLK(0) /*!< output no blanking */ 158 #define CS_CMPMBLK_OUTPUTBLANK_TIMER2_IC3 CS_CMPMBLK(1) /*!< select TIMER2_CH3 as blanking source */ 159 #define CS_CMPMBLK_OUTPUTBLANK_TIMER1IC2 CS_CMPMBLK(2) /*!< select TIMER1_CH2 as blanking source */ 160 #define CS_CMPMBLK_OUTPUTBLANK_TIMER2IC2_TIMER1IC3 CS_CMPMBLK(3) /*!< select TIMER2_CH2 or TIMER1_CH3 as blanking source */ 161 162 /* CMP output level */ 163 #define CMP_OUTPUTLEVEL_HIGH ((uint32_t)0x00000001) /*!< comparator output high */ 164 #define CMP_OUTPUTLEVEL_LOW ((uint32_t)0x00000000) /*!< comparator output low */ 165 166 /* function declarations */ 167 /* initialization functions */ 168 /* CMP deinit */ 169 void cmp_deinit(void); 170 /* CMP input init */ 171 void cmp_input_init(cmp_enum cmp_periph,inverting_input_enum inverting_input); 172 /* CMP output init */ 173 void cmp_output_init(cmp_enum cmp_periph,cmp_output_enum output_slection, uint32_t output_polarity); 174 /* CMP output blank init */ 175 void cmp_outputblank_init(cmp_enum cmp_periph,cmp_outputblank_enum output_blank); 176 177 /* enable CMP */ 178 void cmp_enable(cmp_enum cmp_periph); 179 /* disable CMP */ 180 void cmp_disable(cmp_enum cmp_periph); 181 /* lock the CMP */ 182 void cmp_lock_enable(cmp_enum cmp_periph); 183 184 /* get output level */ 185 uint32_t cmp_output_level_get(cmp_enum cmp_periph); 186 #endif /* GD32E50X_CMP_H */ 187
