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Searched refs:CRC_CTL_RST (Results 1 – 16 of 16) sorted by relevance

/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/standard_peripheral/source/
Dgd32f403_crc.c52 CRC_CTL = (uint32_t)CRC_CTL_RST; in crc_deinit()
63 CRC_CTL |= (uint32_t)CRC_CTL_RST; in crc_data_register_reset()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f4xx/standard_peripheral/source/
Dgd32f4xx_crc.c53 CRC_CTL = (uint32_t)CRC_CTL_RST; in crc_deinit()
64 CRC_CTL |= (uint32_t)CRC_CTL_RST; in crc_data_register_reset()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32vf103/standard_peripheral/source/
Dgd32vf103_crc.c51 CRC_CTL = (uint32_t)CRC_CTL_RST; in crc_deinit()
62 CRC_CTL |= (uint32_t)CRC_CTL_RST; in crc_data_register_reset()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/standard_peripheral/source/
Dgd32e10x_crc.c53 CRC_CTL = (uint32_t)CRC_CTL_RST; in crc_deinit()
64 CRC_CTL |= (uint32_t)CRC_CTL_RST; in crc_data_register_reset()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32l23x/standard_peripheral/source/
Dgd32l23x_crc.c49 CRC_CTL = CRC_CTL_RST; in crc_deinit()
83 CRC_CTL |= (uint32_t)CRC_CTL_RST; in crc_data_register_reset()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32a50x/standard_peripheral/source/
Dgd32a50x_crc.c49 CRC_CTL = CRC_CTL_RST; in crc_deinit()
83 CRC_CTL |= (uint32_t)CRC_CTL_RST; in crc_data_register_reset()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f3x0/standard_peripheral/source/
Dgd32f3x0_crc.c51 CRC_CTL = CRC_CTL_RST; in crc_deinit()
85 CRC_CTL |= (uint32_t)CRC_CTL_RST; in crc_data_register_reset()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/source/
Dgd32e50x_crc.c51 CRC_CTL = CRC_CTL_RST; in crc_deinit()
62 CRC_CTL |= (uint32_t)CRC_CTL_RST; in crc_data_register_reset()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/standard_peripheral/include/
Dgd32f403_crc.h58 #define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA regi… macro
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32vf103/standard_peripheral/include/
Dgd32vf103_crc.h57 #define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA regi… macro
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f4xx/standard_peripheral/include/
Dgd32f4xx_crc.h59 #define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA regi… macro
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/standard_peripheral/include/
Dgd32e10x_crc.h59 #define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA regi… macro
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f3x0/standard_peripheral/include/
Dgd32f3x0_crc.h60 #define CRC_CTL_RST BIT(0) /*!< CRC reset bit */ macro
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/include/
Dgd32e50x_crc.h60 #define CRC_CTL_RST BIT(0) /*!< CRC reset */ macro
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32a50x/standard_peripheral/include/
Dgd32a50x_crc.h58 #define CRC_CTL_RST BIT(0) /*!< CRC reset bit */ macro
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32l23x/standard_peripheral/include/
Dgd32l23x_crc.h58 #define CRC_CTL_RST BIT(0) /*!< CRC reset bit */ macro