1 /*! 2 \file gd32l23x_cau.h 3 \brief definitions for the CAU 4 5 \version 2021-08-04, V1.0.0, firmware for GD32L23x 6 \version 2021-08-12, V1.0.1, firmware for GD32L23x 7 */ 8 9 /* 10 Copyright (c) 2021, GigaDevice Semiconductor Inc. 11 12 Redistribution and use in source and binary forms, with or without modification, 13 are permitted provided that the following conditions are met: 14 15 1. Redistributions of source code must retain the above copyright notice, this 16 list of conditions and the following disclaimer. 17 2. Redistributions in binary form must reproduce the above copyright notice, 18 this list of conditions and the following disclaimer in the documentation 19 and/or other materials provided with the distribution. 20 3. Neither the name of the copyright holder nor the names of its contributors 21 may be used to endorse or promote products derived from this software without 22 specific prior written permission. 23 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 30 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 33 OF SUCH DAMAGE. 34 */ 35 36 #ifndef GD32L23X_CAU_H 37 #define GD32L23X_CAU_H 38 39 #include "gd32l23x.h" 40 41 /* CAU definitions */ 42 #define CAU CAU_BASE /*!< CAU base address */ 43 44 /* registers definitions */ 45 #define CAU_CTL REG32(CAU + 0x00000000U) /*!< control register */ 46 #define CAU_STAT0 REG32(CAU + 0x00000004U) /*!< status register 0 */ 47 #define CAU_DI REG32(CAU + 0x00000008U) /*!< data input register */ 48 #define CAU_DO REG32(CAU + 0x0000000CU) /*!< data output register */ 49 #define CAU_DMAEN REG32(CAU + 0x00000010U) /*!< DMA enable register */ 50 #define CAU_INTEN REG32(CAU + 0x00000014U) /*!< interrupt enable register */ 51 #define CAU_STAT1 REG32(CAU + 0x00000018U) /*!< status register 1 */ 52 #define CAU_INTF REG32(CAU + 0x0000001CU) /*!< interrupt flag register */ 53 #define CAU_KEY0H REG32(CAU + 0x00000020U) /*!< key 0 high register */ 54 #define CAU_KEY0L REG32(CAU + 0x00000024U) /*!< key 0 low register */ 55 #define CAU_KEY1H REG32(CAU + 0x00000028U) /*!< key 1 high register */ 56 #define CAU_KEY1L REG32(CAU + 0x0000002CU) /*!< key 1 low register */ 57 #define CAU_KEY2H REG32(CAU + 0x00000030U) /*!< key 2 high register */ 58 #define CAU_KEY2L REG32(CAU + 0x00000034U) /*!< key 2 low register */ 59 #define CAU_KEY3H REG32(CAU + 0x00000038U) /*!< key 3 high register */ 60 #define CAU_KEY3L REG32(CAU + 0x0000003CU) /*!< key 3 low register */ 61 #define CAU_IV0H REG32(CAU + 0x00000040U) /*!< initial vector 0 high register */ 62 #define CAU_IV0L REG32(CAU + 0x00000044U) /*!< initial vector 0 low register */ 63 #define CAU_IV1H REG32(CAU + 0x00000048U) /*!< initial vector 1 high register */ 64 #define CAU_IV1L REG32(CAU + 0x0000004CU) /*!< initial vector 1 low register */ 65 #define CAU_GCMCCMCTXSx(x) REG32(CAU + 0x00000050U + (uint32_t)(4U * (x))) /*!< GCM or CCM mode context switch register */ 66 #define CAU_GCMCTXSx(x) REG32(CAU + 0x00000070U + (uint32_t)(4U * (x))) /*!< GCM mode context switch register */ 67 68 /* bits definitions */ 69 /* CAU_CTL */ 70 #define CAU_CTL_CAUDIR BIT(2) /*!< algorithm direction */ 71 #define CAU_CTL_ALGM (BITS(3,5) | BIT(19)) /*!< cryptographic algorithm mode */ 72 #define CAU_CTL_DATAM BITS(6,7) /*!< data swapping selection */ 73 #define CAU_CTL_KEYM BITS(8,9) /*!< key length selection when aes mode */ 74 #define CAU_CTL_FFLUSH BIT(14) /*!< FIFO flush */ 75 #define CAU_CTL_CAUEN BIT(15) /*!< cryptographic module enable */ 76 #define CAU_CTL_GCM_CCMPH BITS(16,17) /*!< GCM CCM phase */ 77 #define CAU_CTL_NBPILB BITS(20,23) /*!< number of bytes padding in last block */ 78 79 /* CAU_STAT0 */ 80 #define CAU_STAT0_IEM BIT(0) /*!< IN FIFO empty flag */ 81 #define CAU_STAT0_INF BIT(1) /*!< IN FIFO not full flag */ 82 #define CAU_STAT0_ONE BIT(2) /*!< OUT FIFO not empty flag */ 83 #define CAU_STAT0_OFU BIT(3) /*!< OUT FIFO full flag */ 84 #define CAU_STAT0_BUSY BIT(4) /*!< busy flag */ 85 86 /* CAU_DI */ 87 #define CAU_DI_DI BITS(0,31) /*!< data input */ 88 89 /* CAU_DO */ 90 #define CAU_DO_DO BITS(0,31) /*!< data output */ 91 92 /* CAU_DMAEN */ 93 #define CAU_DMAEN_DMAIEN BIT(0) /*!< IN FIFO DMA enable */ 94 #define CAU_DMAEN_DMAOEN BIT(1) /*!< OUT FIFO DMA enable */ 95 96 /* CAU_INTEN */ 97 #define CAU_INTEN_IINTEN BIT(0) /*!< IN FIFO interrupt enable */ 98 #define CAU_INTEN_OINTEN BIT(1) /*!< OUT FIFO interrupt enable */ 99 100 /* CAU_STAT1 */ 101 #define CAU_STAT1_ISTA BIT(0) /*!< flag set when there is less than 4 words in IN FIFO */ 102 #define CAU_STAT1_OSTA BIT(1) /*!< flag set when there is one or more word in OUT FIFO */ 103 104 /* CAU_INTF */ 105 #define CAU_INTF_IINTF BIT(0) /*!< IN FIFO interrupt flag */ 106 #define CAU_INTF_OINTF BIT(1) /*!< OUT FIFO interrupt flag */ 107 108 /* CAU_KEYxH x=0..3 */ 109 #define CAU_KEYXH_KEYXH BITS(0,31) /*!< the key for des, tdes, aes */ 110 111 /* CAU_KEYxL x=0..3 */ 112 #define CAU_KEYXL_KEYXL BITS(0,31) /*!< the key for des, tdes, aes */ 113 114 /* CAU_IVxH x=0..1 */ 115 #define CAU_IVXH_IVXH BITS(0,31) /*!< the initialization vector for des, tdes, aes */ 116 117 /* CAU_IVxL x=0..1 */ 118 #define CAU_IVXL_IVXL BITS(0,31) /*!< the initialization vector for des, tdes, aes */ 119 120 /* constants definitions */ 121 /* structure for keys initialization of the cau */ 122 typedef struct { 123 uint32_t key_0_high; /*!< key 0 high */ 124 uint32_t key_0_low; /*!< key 0 low */ 125 uint32_t key_1_high; /*!< key 1 high */ 126 uint32_t key_1_low; /*!< key 1 low */ 127 uint32_t key_2_high; /*!< key 2 high */ 128 uint32_t key_2_low; /*!< key 2 low */ 129 uint32_t key_3_high; /*!< key 3 high */ 130 uint32_t key_3_low; /*!< key 3 low */ 131 } cau_key_parameter_struct; 132 133 /* structure for vectors initialization of the cau */ 134 typedef struct { 135 uint32_t iv_0_high; /*!< init vector 0 high */ 136 uint32_t iv_0_low; /*!< init vector 0 low */ 137 uint32_t iv_1_high; /*!< init vector 1 high */ 138 uint32_t iv_1_low; /*!< init vector 1 low */ 139 } cau_iv_parameter_struct; 140 141 /* structure for cau context swapping */ 142 typedef struct { 143 uint32_t ctl_config; /*!< current configuration */ 144 uint32_t iv_0_high; /*!< init vector 0 high */ 145 uint32_t iv_0_low; /*!< init vector 0 low */ 146 uint32_t iv_1_high; /*!< init vector 1 high */ 147 uint32_t iv_1_low; /*!< init vector 1 low */ 148 uint32_t key_0_high; /*!< key 0 high */ 149 uint32_t key_0_low; /*!< key 0 low */ 150 uint32_t key_1_high; /*!< key 1 high */ 151 uint32_t key_1_low; /*!< key 1 low */ 152 uint32_t key_2_high; /*!< key 2 high */ 153 uint32_t key_2_low; /*!< key 2 low */ 154 uint32_t key_3_high; /*!< key 3 high */ 155 uint32_t key_3_low; /*!< key 3 low */ 156 uint32_t gcmccmctxs[8]; /*!< GCM or CCM mode context switch */ 157 uint32_t gcmctxs[8]; /*!< GCM mode context switch */ 158 } cau_context_parameter_struct; 159 160 /* structure for encrypt and decrypt parameters */ 161 typedef struct { 162 uint32_t alg_dir; /*!< algorithm dirctory */ 163 uint8_t *key; /*!< key */ 164 uint32_t key_size; /*!< key size in bytes */ 165 uint8_t *iv; /*!< initialization vector */ 166 uint32_t iv_size; /*!< iv size in bytes */ 167 uint8_t *input; /*!< input data */ 168 uint32_t in_length; /*!< input data length in bytes */ 169 uint8_t *aad; /*!< additional authentication data */ 170 uint32_t aad_size; /*!< aad size */ 171 } cau_parameter_struct; 172 173 /* cau_ctl register value */ 174 #define CAU_ENCRYPT ((uint32_t)0x00000000U) /*!< encrypt */ 175 #define CAU_DECRYPT CAU_CTL_CAUDIR /*!< decrypt */ 176 177 #define CTL_ALGM(regval) ((BITS(3,5) & ((uint32_t)(regval) << 3U)) | \ 178 (BIT(19) & ((uint32_t)(regval) << 16U))) /*!< write value to CAU_CTL_ALGM bit field */ 179 #define CAU_MODE_TDES_ECB CTL_ALGM(0) /*!< TDES-ECB (3DES Electronic codebook) */ 180 #define CAU_MODE_TDES_CBC CTL_ALGM(1) /*!< TDES-CBC (3DES Cipher block chaining) */ 181 #define CAU_MODE_DES_ECB CTL_ALGM(2) /*!< DES-ECB (simple DES Electronic codebook) */ 182 #define CAU_MODE_DES_CBC CTL_ALGM(3) /*!< DES-CBC (simple DES Cipher block chaining) */ 183 #define CAU_MODE_AES_ECB CTL_ALGM(4) /*!< AES-ECB (AES Electronic codebook) */ 184 #define CAU_MODE_AES_CBC CTL_ALGM(5) /*!< AES-CBC (AES Cipher block chaining) */ 185 #define CAU_MODE_AES_CTR CTL_ALGM(6) /*!< AES-CTR (AES counter mode) */ 186 #define CAU_MODE_AES_KEY CTL_ALGM(7) /*!< AES decryption key preparation mode */ 187 #define CAU_MODE_AES_GCM CTL_ALGM(8) /*!< AES-GCM (AES Galois/counter mode) */ 188 #define CAU_MODE_AES_CCM CTL_ALGM(9) /*!< AES-CCM (AES combined cipher machine mode) */ 189 #define CAU_MODE_AES_CFB CTL_ALGM(10) /*!< AES-CFB (cipher feedback mode) */ 190 #define CAU_MODE_AES_OFB CTL_ALGM(11) /*!< AES-OFB (output feedback mode) */ 191 192 #define CTL_DATAM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6U)) /*!< write value to CAU_CTL_DATAM bit field */ 193 #define CAU_SWAPPING_32BIT CTL_DATAM(0) /*!< no swapping */ 194 #define CAU_SWAPPING_16BIT CTL_DATAM(1) /*!< half-word swapping */ 195 #define CAU_SWAPPING_8BIT CTL_DATAM(2) /*!< bytes swapping */ 196 #define CAU_SWAPPING_1BIT CTL_DATAM(3) /*!< bit swapping */ 197 198 #define CTL_KEYM(regval) (BITS(8,9) & ((uint32_t)(regval) << 8U)) /*!< write value to CAU_CTL_KEYM bit field */ 199 #define CAU_KEYSIZE_128BIT CTL_KEYM(0) /*!< 128 bit key length */ 200 #define CAU_KEYSIZE_192BIT CTL_KEYM(1) /*!< 192 bit key length */ 201 #define CAU_KEYSIZE_256BIT CTL_KEYM(2) /*!< 256 bit key length */ 202 203 #define CTL_GCM_CCMPH(regval) (BITS(16,17) & ((uint32_t)(regval) << 16U)) /*!< write value to CAU_CTL_GCM_CCMPH bit field */ 204 #define CAU_PREPARE_PHASE CTL_GCM_CCMPH(0) /*!< prepare phase */ 205 #define CAU_AAD_PHASE CTL_GCM_CCMPH(1) /*!< AAD phase */ 206 #define CAU_ENCRYPT_DECRYPT_PHASE CTL_GCM_CCMPH(2) /*!< encryption/decryption phase */ 207 #define CAU_TAG_PHASE CTL_GCM_CCMPH(3) /*!< tag phase */ 208 209 #define CAU_PADDING_BYTES(regval) (BITS(20, 23) & ((uint32_t)(regval) << 20U)) 210 211 /* cau_stat0 register value */ 212 #define CAU_FLAG_INFIFO_EMPTY CAU_STAT0_IEM /*!< IN FIFO empty */ 213 #define CAU_FLAG_INFIFO_NO_FULL CAU_STAT0_INF /*!< IN FIFO is not full */ 214 #define CAU_FLAG_OUTFIFO_NO_EMPTY CAU_STAT0_ONE /*!< OUT FIFO not empty */ 215 #define CAU_FLAG_OUTFIFO_FULL CAU_STAT0_OFU /*!< OUT FIFO is full */ 216 #define CAU_FLAG_BUSY CAU_STAT0_BUSY /*!< the CAU core is busy */ 217 218 /* cau_dmaen register value */ 219 #define CAU_DMA_INFIFO CAU_DMAEN_DMAIEN /*!< DMA input enable */ 220 #define CAU_DMA_OUTFIFO CAU_DMAEN_DMAOEN /*!< DMA output enable */ 221 222 /* cau_inten register value */ 223 #define CAU_INT_INFIFO CAU_INTEN_IINTEN /*!< IN FIFO Interrupt */ 224 #define CAU_INT_OUTFIFO CAU_INTEN_OINTEN /*!< OUT FIFO Interrupt */ 225 226 /* cau_stat1 register value */ 227 #define CAU_FLAG_INFIFO CAU_STAT1_ISTA /*!< IN FIFO flag status */ 228 #define CAU_FLAG_OUTFIFO CAU_STAT1_OSTA /*!< OUT FIFO flag status */ 229 230 /* cau_intf register value */ 231 #define CAU_INT_FLAG_INFIFO CAU_INTF_IINTF /*!< IN FIFO interrupt status */ 232 #define CAU_INT_FLAG_OUTFIFO CAU_INTF_OINTF /*!< OUT FIFO interrupt status */ 233 234 /* function declarations */ 235 /* initialization functions */ 236 /* reset the CAU peripheral */ 237 void cau_deinit(void); 238 /* initialize the CAU encrypt and decrypt parameter struct with the default values */ 239 void cau_struct_para_init(cau_parameter_struct *cau_parameter); 240 /* initialize the key parameter struct with the default values */ 241 void cau_key_struct_para_init(cau_key_parameter_struct *key_initpara); 242 /* initialize the vectors parameter struct with the default values */ 243 void cau_iv_struct_para_init(cau_iv_parameter_struct *iv_initpara); 244 /* initialize the context parameter struct with the default values */ 245 void cau_context_struct_para_init(cau_context_parameter_struct *cau_context); 246 247 /* configuration functions */ 248 /* enable the CAU peripheral */ 249 void cau_enable(void); 250 /* disable the CAU peripheral */ 251 void cau_disable(void); 252 /* enable the CAU DMA interface */ 253 void cau_dma_enable(uint32_t dma_req); 254 /* disable the CAU DMA interface */ 255 void cau_dma_disable(uint32_t dma_req); 256 /* initialize the CAU peripheral */ 257 void cau_init(uint32_t alg_dir, uint32_t algo_mode, uint32_t swapping); 258 /* configure key size if use AES algorithm */ 259 void cau_aes_keysize_config(uint32_t key_size); 260 /* initialize the key parameters */ 261 void cau_key_init(cau_key_parameter_struct *key_initpara); 262 /* initialize the vectors parameters */ 263 void cau_iv_init(cau_iv_parameter_struct *iv_initpara); 264 /* configure phase */ 265 void cau_phase_config(uint32_t phase); 266 /* flush the IN and OUT FIFOs */ 267 void cau_fifo_flush(void); 268 /* return whether CAU peripheral is enabled or disabled */ 269 ControlStatus cau_enable_state_get(void); 270 271 /* read and write functions */ 272 /* write data to the IN FIFO */ 273 void cau_data_write(uint32_t data); 274 /* return the last data entered into the output FIFO */ 275 uint32_t cau_data_read(void); 276 277 /* context switch functions */ 278 /* save context before context switching */ 279 void cau_context_save(cau_context_parameter_struct *cau_context, cau_key_parameter_struct *key_initpara); 280 /* restore context after context switching */ 281 void cau_context_restore(cau_context_parameter_struct *cau_context); 282 283 /* encrypt and decrypt functions */ 284 /* encrypt and decrypt using AES in ECB mode */ 285 ErrStatus cau_aes_ecb(cau_parameter_struct *cau_parameter, uint8_t *output); 286 /* encrypt and decrypt using AES in CBC mode */ 287 ErrStatus cau_aes_cbc(cau_parameter_struct *cau_parameter, uint8_t *output); 288 /* encrypt and decrypt using AES in CTR mode */ 289 ErrStatus cau_aes_ctr(cau_parameter_struct *cau_parameter, uint8_t *output); 290 /* encrypt and decrypt using AES in CFB mode */ 291 ErrStatus cau_aes_cfb(cau_parameter_struct *cau_parameter, uint8_t *output); 292 /* encrypt and decrypt using AES in OFB mode */ 293 ErrStatus cau_aes_ofb(cau_parameter_struct *cau_parameter, uint8_t *output); 294 /* encrypt and decrypt using AES in GCM mode */ 295 ErrStatus cau_aes_gcm(cau_parameter_struct *cau_parameter, uint8_t *output, uint8_t *tag); 296 /* encrypt and decrypt using AES in CCM mode */ 297 ErrStatus cau_aes_ccm(cau_parameter_struct *cau_parameter, uint8_t *output, uint8_t tag[], uint32_t tag_size, uint8_t aad_buf[]); 298 /* encrypt and decrypt using TDES in ECB mode */ 299 ErrStatus cau_tdes_ecb(cau_parameter_struct *cau_parameter, uint8_t *output); 300 /* encrypt and decrypt using TDES in CBC mode */ 301 ErrStatus cau_tdes_cbc(cau_parameter_struct *cau_parameter, uint8_t *output); 302 /* encrypt and decrypt using DES in ECB mode */ 303 ErrStatus cau_des_ecb(cau_parameter_struct *cau_parameter, uint8_t *output); 304 /* encrypt and decrypt using DES in CBC mode */ 305 ErrStatus cau_des_cbc(cau_parameter_struct *cau_parameter, uint8_t *output); 306 307 /* interrupt & flag functions */ 308 /* enable the CAU interrupts */ 309 void cau_interrupt_enable(uint32_t interrupt); 310 /* disable the CAU interrupts */ 311 void cau_interrupt_disable(uint32_t interrupt); 312 /* get the interrupt flag */ 313 FlagStatus cau_interrupt_flag_get(uint32_t interrupt); 314 /* get the CAU flag status */ 315 FlagStatus cau_flag_get(uint32_t flag); 316 317 #endif /* GD32L23X_CAU_H */ 318
