1 /*! 2 \file gd32e50x_can.h 3 \brief definitions for the CAN 4 5 \version 2020-03-10, V1.0.0, firmware for GD32E50x 6 \version 2021-03-23, V1.2.0, firmware for GD32E50x 7 */ 8 9 /* 10 Copyright (c) 2021, GigaDevice Semiconductor Inc. 11 12 Redistribution and use in source and binary forms, with or without modification, 13 are permitted provided that the following conditions are met: 14 15 1. Redistributions of source code must retain the above copyright notice, this 16 list of conditions and the following disclaimer. 17 2. Redistributions in binary form must reproduce the above copyright notice, 18 this list of conditions and the following disclaimer in the documentation 19 and/or other materials provided with the distribution. 20 3. Neither the name of the copyright holder nor the names of its contributors 21 may be used to endorse or promote products derived from this software without 22 specific prior written permission. 23 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 30 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 33 OF SUCH DAMAGE. 34 */ 35 36 #ifndef GD32E50X_CAN_H 37 #define GD32E50X_CAN_H 38 39 #include "gd32e50x.h" 40 41 /* CAN definitions */ 42 #define CAN0 CAN_BASE /*!< CAN0 base address */ 43 #define CAN1 (CAN_BASE + 0x00000400U) /*!< CAN1 base address */ 44 #define CAN2 (CAN_BASE + 0x00006800U) /*!< CAN2 base address */ 45 46 47 /* registers definitions */ 48 #define CAN_CTL(canx) REG32((canx) + 0x00000000U) /*!< CAN control register */ 49 #define CAN_STAT(canx) REG32((canx) + 0x00000004U) /*!< CAN status register */ 50 #define CAN_TSTAT(canx) REG32((canx) + 0x00000008U) /*!< CAN transmit status register*/ 51 #define CAN_RFIFO0(canx) REG32((canx) + 0x0000000CU) /*!< CAN receive FIFO0 register */ 52 #define CAN_RFIFO1(canx) REG32((canx) + 0x00000010U) /*!< CAN receive FIFO1 register */ 53 #define CAN_INTEN(canx) REG32((canx) + 0x00000014U) /*!< CAN interrupt enable register */ 54 #define CAN_ERR(canx) REG32((canx) + 0x00000018U) /*!< CAN error register */ 55 #define CAN_BT(canx) REG32((canx) + 0x0000001CU) /*!< CAN bit timing register */ 56 #ifdef GD32E508 57 #define CAN_FDCTL(canx) REG32((canx) + 0x00000020U) /*!< CAN FD control register */ 58 #define CAN_FDSTAT(canx) REG32((canx) + 0x00000024U) /*!< CAN FD status register */ 59 #define CAN_FDTDC(canx) REG32((canx) + 0x00000028U) /*!< CAN FD transmitter delay compensation register */ 60 #define CAN_DBT(canx) REG32((canx) + 0x0000002CU) /*!< CAN date bit timing register */ 61 #endif /* GD32E508 */ 62 #define CAN_TMI0(canx) REG32((canx) + 0x00000180U) /*!< CAN transmit mailbox0 identifier register */ 63 #define CAN_TMP0(canx) REG32((canx) + 0x00000184U) /*!< CAN transmit mailbox0 property register */ 64 #define CAN_TMDATA00(canx) REG32((canx) + 0x00000188U) /*!< CAN transmit mailbox0 data0 register */ 65 #define CAN_TMDATA10(canx) REG32((canx) + 0x0000018CU) /*!< CAN transmit mailbox0 data1 register */ 66 #define CAN_TMI1(canx) REG32((canx) + 0x00000190U) /*!< CAN transmit mailbox1 identifier register */ 67 #define CAN_TMP1(canx) REG32((canx) + 0x00000194U) /*!< CAN transmit mailbox1 property register */ 68 #define CAN_TMDATA01(canx) REG32((canx) + 0x00000198U) /*!< CAN transmit mailbox1 data0 register */ 69 #define CAN_TMDATA11(canx) REG32((canx) + 0x0000019CU) /*!< CAN transmit mailbox1 data1 register */ 70 #define CAN_TMI2(canx) REG32((canx) + 0x000001A0U) /*!< CAN transmit mailbox2 identifier register */ 71 #define CAN_TMP2(canx) REG32((canx) + 0x000001A4U) /*!< CAN transmit mailbox2 property register */ 72 #define CAN_TMDATA02(canx) REG32((canx) + 0x000001A8U) /*!< CAN transmit mailbox2 data0 register */ 73 #define CAN_TMDATA12(canx) REG32((canx) + 0x000001ACU) /*!< CAN transmit mailbox2 data1 register */ 74 #define CAN_RFIFOMI0(canx) REG32((canx) + 0x000001B0U) /*!< CAN receive FIFO0 mailbox identifier register */ 75 #define CAN_RFIFOMP0(canx) REG32((canx) + 0x000001B4U) /*!< CAN receive FIFO0 mailbox property register */ 76 #define CAN_RFIFOMDATA00(canx) REG32((canx) + 0x000001B8U) /*!< CAN receive FIFO0 mailbox data0 register */ 77 #define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x000001BCU) /*!< CAN receive FIFO0 mailbox data1 register */ 78 #define CAN_RFIFOMI1(canx) REG32((canx) + 0x000001C0U) /*!< CAN receive FIFO1 mailbox identifier register */ 79 #define CAN_RFIFOMP1(canx) REG32((canx) + 0x000001C4U) /*!< CAN receive FIFO1 mailbox property register */ 80 #define CAN_RFIFOMDATA01(canx) REG32((canx) + 0x000001C8U) /*!< CAN receive FIFO1 mailbox data0 register */ 81 #define CAN_RFIFOMDATA11(canx) REG32((canx) + 0x000001CCU) /*!< CAN receive FIFO1 mailbox data1 register */ 82 #define CAN_FCTL(canx) REG32((canx) + 0x00000200U) /*!< CAN filter control register */ 83 #define CAN_FMCFG(canx) REG32((canx) + 0x00000204U) /*!< CAN filter mode register */ 84 #define CAN_FSCFG(canx) REG32((canx) + 0x0000020CU) /*!< CAN filter scale register */ 85 #define CAN_FAFIFO(canx) REG32((canx) + 0x00000214U) /*!< CAN filter associated FIFO register */ 86 #define CAN_FW(canx) REG32((canx) + 0x0000021CU) /*!< CAN filter working register */ 87 #define CAN_F0DATA0(canx) REG32((canx) + 0x00000240U) /*!< CAN filter 0 data 0 register */ 88 #define CAN_F1DATA0(canx) REG32((canx) + 0x00000248U) /*!< CAN filter 1 data 0 register */ 89 #define CAN_F2DATA0(canx) REG32((canx) + 0x00000250U) /*!< CAN filter 2 data 0 register */ 90 #define CAN_F3DATA0(canx) REG32((canx) + 0x00000258U) /*!< CAN filter 3 data 0 register */ 91 #define CAN_F4DATA0(canx) REG32((canx) + 0x00000260U) /*!< CAN filter 4 data 0 register */ 92 #define CAN_F5DATA0(canx) REG32((canx) + 0x00000268U) /*!< CAN filter 5 data 0 register */ 93 #define CAN_F6DATA0(canx) REG32((canx) + 0x00000270U) /*!< CAN filter 6 data 0 register */ 94 #define CAN_F7DATA0(canx) REG32((canx) + 0x00000278U) /*!< CAN filter 7 data 0 register */ 95 #define CAN_F8DATA0(canx) REG32((canx) + 0x00000280U) /*!< CAN filter 8 data 0 register */ 96 #define CAN_F9DATA0(canx) REG32((canx) + 0x00000288U) /*!< CAN filter 9 data 0 register */ 97 #define CAN_F10DATA0(canx) REG32((canx) + 0x00000290U) /*!< CAN filter 10 data 0 register */ 98 #define CAN_F11DATA0(canx) REG32((canx) + 0x00000298U) /*!< CAN filter 11 data 0 register */ 99 #define CAN_F12DATA0(canx) REG32((canx) + 0x000002A0U) /*!< CAN filter 12 data 0 register */ 100 #define CAN_F13DATA0(canx) REG32((canx) + 0x000002A8U) /*!< CAN filter 13 data 0 register */ 101 #define CAN_F14DATA0(canx) REG32((canx) + 0x000002B0U) /*!< CAN filter 14 data 0 register */ 102 #define CAN_F15DATA0(canx) REG32((canx) + 0x000002B8U) /*!< CAN filter 15 data 0 register */ 103 #define CAN_F16DATA0(canx) REG32((canx) + 0x000002C0U) /*!< CAN filter 16 data 0 register */ 104 #define CAN_F17DATA0(canx) REG32((canx) + 0x000002C8U) /*!< CAN filter 17 data 0 register */ 105 #define CAN_F18DATA0(canx) REG32((canx) + 0x000002D0U) /*!< CAN filter 18 data 0 register */ 106 #define CAN_F19DATA0(canx) REG32((canx) + 0x000002D8U) /*!< CAN filter 19 data 0 register */ 107 #define CAN_F20DATA0(canx) REG32((canx) + 0x000002E0U) /*!< CAN filter 20 data 0 register */ 108 #define CAN_F21DATA0(canx) REG32((canx) + 0x000002E8U) /*!< CAN filter 21 data 0 register */ 109 #define CAN_F22DATA0(canx) REG32((canx) + 0x000002F0U) /*!< CAN filter 22 data 0 register */ 110 #define CAN_F23DATA0(canx) REG32((canx) + 0x000003F8U) /*!< CAN filter 23 data 0 register */ 111 #define CAN_F24DATA0(canx) REG32((canx) + 0x00000300U) /*!< CAN filter 24 data 0 register */ 112 #define CAN_F25DATA0(canx) REG32((canx) + 0x00000308U) /*!< CAN filter 25 data 0 register */ 113 #define CAN_F26DATA0(canx) REG32((canx) + 0x00000310U) /*!< CAN filter 26 data 0 register */ 114 #define CAN_F27DATA0(canx) REG32((canx) + 0x00000318U) /*!< CAN filter 27 data 0 register */ 115 #define CAN_F0DATA1(canx) REG32((canx) + 0x00000244U) /*!< CAN filter 0 data 1 register */ 116 #define CAN_F1DATA1(canx) REG32((canx) + 0x0000024CU) /*!< CAN filter 1 data 1 register */ 117 #define CAN_F2DATA1(canx) REG32((canx) + 0x00000254U) /*!< CAN filter 2 data 1 register */ 118 #define CAN_F3DATA1(canx) REG32((canx) + 0x0000025CU) /*!< CAN filter 3 data 1 register */ 119 #define CAN_F4DATA1(canx) REG32((canx) + 0x00000264U) /*!< CAN filter 4 data 1 register */ 120 #define CAN_F5DATA1(canx) REG32((canx) + 0x0000026CU) /*!< CAN filter 5 data 1 register */ 121 #define CAN_F6DATA1(canx) REG32((canx) + 0x00000274U) /*!< CAN filter 6 data 1 register */ 122 #define CAN_F7DATA1(canx) REG32((canx) + 0x0000027CU) /*!< CAN filter 7 data 1 register */ 123 #define CAN_F8DATA1(canx) REG32((canx) + 0x00000284U) /*!< CAN filter 8 data 1 register */ 124 #define CAN_F9DATA1(canx) REG32((canx) + 0x0000028CU) /*!< CAN filter 9 data 1 register */ 125 #define CAN_F10DATA1(canx) REG32((canx) + 0x00000294U) /*!< CAN filter 10 data 1 register */ 126 #define CAN_F11DATA1(canx) REG32((canx) + 0x0000029CU) /*!< CAN filter 11 data 1 register */ 127 #define CAN_F12DATA1(canx) REG32((canx) + 0x000002A4U) /*!< CAN filter 12 data 1 register */ 128 #define CAN_F13DATA1(canx) REG32((canx) + 0x000002ACU) /*!< CAN filter 13 data 1 register */ 129 #define CAN_F14DATA1(canx) REG32((canx) + 0x000002B4U) /*!< CAN filter 14 data 1 register */ 130 #define CAN_F15DATA1(canx) REG32((canx) + 0x000002BCU) /*!< CAN filter 15 data 1 register */ 131 #define CAN_F16DATA1(canx) REG32((canx) + 0x000002C4U) /*!< CAN filter 16 data 1 register */ 132 #define CAN_F17DATA1(canx) REG32((canx) + 0x0000024CU) /*!< CAN filter 17 data 1 register */ 133 #define CAN_F18DATA1(canx) REG32((canx) + 0x000002D4U) /*!< CAN filter 18 data 1 register */ 134 #define CAN_F19DATA1(canx) REG32((canx) + 0x000002DCU) /*!< CAN filter 19 data 1 register */ 135 #define CAN_F20DATA1(canx) REG32((canx) + 0x000002E4U) /*!< CAN filter 20 data 1 register */ 136 #define CAN_F21DATA1(canx) REG32((canx) + 0x000002ECU) /*!< CAN filter 21 data 1 register */ 137 #define CAN_F22DATA1(canx) REG32((canx) + 0x000002F4U) /*!< CAN filter 22 data 1 register */ 138 #define CAN_F23DATA1(canx) REG32((canx) + 0x000002FCU) /*!< CAN filter 23 data 1 register */ 139 #define CAN_F24DATA1(canx) REG32((canx) + 0x00000304U) /*!< CAN filter 24 data 1 register */ 140 #define CAN_F25DATA1(canx) REG32((canx) + 0x0000030CU) /*!< CAN filter 25 data 1 register */ 141 #define CAN_F26DATA1(canx) REG32((canx) + 0x00000314U) /*!< CAN filter 26 data 1 register */ 142 #define CAN_F27DATA1(canx) REG32((canx) + 0x0000031CU) /*!< CAN filter 27 data 1 register */ 143 144 /* CAN transmit mailbox bank */ 145 #define CAN_TMI(canx, bank) REG32((canx) + 0x00000180U + ((bank) * 0x00000010U)) /*!< CAN transmit mailbox identifier register */ 146 #define CAN_TMP(canx, bank) REG32((canx) + 0x00000184U + ((bank) * 0x00000010U)) /*!< CAN transmit mailbox property register */ 147 #define CAN_TMDATA0(canx, bank) REG32((canx) + 0x00000188U + ((bank) * 0x00000010U)) /*!< CAN transmit mailbox data0 register */ 148 #define CAN_TMDATA1(canx, bank) REG32((canx) + 0x0000018CU + ((bank) * 0x00000010U)) /*!< CAN transmit mailbox data1 register */ 149 150 /* CAN filter bank */ 151 #define CAN_FDATA0(canx, bank) REG32((canx) + 0x00000240U + ((bank) * 0x00000008U) + 0x00000000U) /*!< CAN filter data 0 register */ 152 #define CAN_FDATA1(canx, bank) REG32((canx) + 0x00000240U + ((bank) * 0x00000008U) + 0x00000004U) /*!< CAN filter data 1 register */ 153 154 /* CAN receive fifo mailbox bank */ 155 #define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x000001B0U + ((bank) * 0x00000010U)) /*!< CAN receive FIFO mailbox identifier register */ 156 #define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x000001B4U + ((bank) * 0x00000010U)) /*!< CAN receive FIFO mailbox property register */ 157 #define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x000001B8U + ((bank) * 0x00000010U)) /*!< CAN receive FIFO mailbox data0 register */ 158 #define CAN_RFIFOMDATA1(canx, bank) REG32((canx) + 0x000001BCU + ((bank) * 0x00000010U)) /*!< CAN receive FIFO mailbox data1 register */ 159 160 /* bits definitions */ 161 /* CAN_CTL */ 162 #define CAN_CTL_IWMOD BIT(0) /*!< initial working mode */ 163 #define CAN_CTL_SLPWMOD BIT(1) /*!< sleep working mode */ 164 #define CAN_CTL_TFO BIT(2) /*!< transmit FIFO order */ 165 #define CAN_CTL_RFOD BIT(3) /*!< receive FIFO overwrite disable */ 166 #define CAN_CTL_ARD BIT(4) /*!< automatic retransmission disable */ 167 #define CAN_CTL_AWU BIT(5) /*!< automatic wakeup */ 168 #define CAN_CTL_ABOR BIT(6) /*!< automatic bus-off recovery */ 169 #define CAN_CTL_TTC BIT(7) /*!< time triggered communication */ 170 #define CAN_CTL_SWRST BIT(15) /*!< CAN software reset */ 171 #define CAN_CTL_DFZ BIT(16) /*!< CAN debug freeze */ 172 173 /* CAN_STAT */ 174 #define CAN_STAT_IWS BIT(0) /*!< initial working state */ 175 #define CAN_STAT_SLPWS BIT(1) /*!< sleep working state */ 176 #define CAN_STAT_ERRIF BIT(2) /*!< error interrupt flag*/ 177 #define CAN_STAT_WUIF BIT(3) /*!< status change interrupt flag of wakeup from sleep working mode */ 178 #define CAN_STAT_SLPIF BIT(4) /*!< status change interrupt flag of sleep working mode entering */ 179 #define CAN_STAT_TS BIT(8) /*!< transmitting state */ 180 #define CAN_STAT_RS BIT(9) /*!< receiving state */ 181 #define CAN_STAT_LASTRX BIT(10) /*!< last sample value of rx pin */ 182 #define CAN_STAT_RXL BIT(11) /*!< CAN rx signal */ 183 184 /* CAN_TSTAT */ 185 #define CAN_TSTAT_MTF0 BIT(0) /*!< mailbox0 transmit finished */ 186 #define CAN_TSTAT_MTFNERR0 BIT(1) /*!< mailbox0 transmit finished and no error */ 187 #define CAN_TSTAT_MAL0 BIT(2) /*!< mailbox0 arbitration lost */ 188 #define CAN_TSTAT_MTE0 BIT(3) /*!< mailbox0 transmit error */ 189 #define CAN_TSTAT_MST0 BIT(7) /*!< mailbox0 stop transmitting */ 190 #define CAN_TSTAT_MTF1 BIT(8) /*!< mailbox1 transmit finished */ 191 #define CAN_TSTAT_MTFNERR1 BIT(9) /*!< mailbox1 transmit finished and no error */ 192 #define CAN_TSTAT_MAL1 BIT(10) /*!< mailbox1 arbitration lost */ 193 #define CAN_TSTAT_MTE1 BIT(11) /*!< mailbox1 transmit error */ 194 #define CAN_TSTAT_MST1 BIT(15) /*!< mailbox1 stop transmitting */ 195 #define CAN_TSTAT_MTF2 BIT(16) /*!< mailbox2 transmit finished */ 196 #define CAN_TSTAT_MTFNERR2 BIT(17) /*!< mailbox2 transmit finished and no error */ 197 #define CAN_TSTAT_MAL2 BIT(18) /*!< mailbox2 arbitration lost */ 198 #define CAN_TSTAT_MTE2 BIT(19) /*!< mailbox2 transmit error */ 199 #define CAN_TSTAT_MST2 BIT(23) /*!< mailbox2 stop transmitting */ 200 #define CAN_TSTAT_NUM BITS(24,25) /*!< mailbox number */ 201 #define CAN_TSTAT_TME0 BIT(26) /*!< transmit mailbox0 empty */ 202 #define CAN_TSTAT_TME1 BIT(27) /*!< transmit mailbox1 empty */ 203 #define CAN_TSTAT_TME2 BIT(28) /*!< transmit mailbox2 empty */ 204 #define CAN_TSTAT_TMLS0 BIT(29) /*!< last sending priority flag for mailbox0 */ 205 #define CAN_TSTAT_TMLS1 BIT(30) /*!< last sending priority flag for mailbox1 */ 206 #define CAN_TSTAT_TMLS2 BIT(31) /*!< last sending priority flag for mailbox2 */ 207 208 /* CAN_RFIFO0 */ 209 #define CAN_RFIFO0_RFL0 BITS(0,1) /*!< receive FIFO0 length */ 210 #define CAN_RFIFO0_RFF0 BIT(3) /*!< receive FIFO0 full */ 211 #define CAN_RFIFO0_RFO0 BIT(4) /*!< receive FIFO0 overfull */ 212 #define CAN_RFIFO0_RFD0 BIT(5) /*!< receive FIFO0 dequeue */ 213 214 /* CAN_RFIFO1 */ 215 #define CAN_RFIFO1_RFL1 BITS(0,1) /*!< receive FIFO1 length */ 216 #define CAN_RFIFO1_RFF1 BIT(3) /*!< receive FIFO1 full */ 217 #define CAN_RFIFO1_RFO1 BIT(4) /*!< receive FIFO1 overfull */ 218 #define CAN_RFIFO1_RFD1 BIT(5) /*!< receive FIFO1 dequeue */ 219 220 /* CAN_INTEN */ 221 #define CAN_INTEN_TMEIE BIT(0) /*!< transmit mailbox empty interrupt enable */ 222 #define CAN_INTEN_RFNEIE0 BIT(1) /*!< receive FIFO0 not empty interrupt enable */ 223 #define CAN_INTEN_RFFIE0 BIT(2) /*!< receive FIFO0 full interrupt enable */ 224 #define CAN_INTEN_RFOIE0 BIT(3) /*!< receive FIFO0 overfull interrupt enable */ 225 #define CAN_INTEN_RFNEIE1 BIT(4) /*!< receive FIFO1 not empty interrupt enable */ 226 #define CAN_INTEN_RFFIE1 BIT(5) /*!< receive FIFO1 full interrupt enable */ 227 #define CAN_INTEN_RFOIE1 BIT(6) /*!< receive FIFO1 overfull interrupt enable */ 228 #define CAN_INTEN_WERRIE BIT(8) /*!< warning error interrupt enable */ 229 #define CAN_INTEN_PERRIE BIT(9) /*!< passive error interrupt enable */ 230 #define CAN_INTEN_BOIE BIT(10) /*!< bus-off interrupt enable */ 231 #define CAN_INTEN_ERRNIE BIT(11) /*!< error number interrupt enable */ 232 #define CAN_INTEN_ERRIE BIT(15) /*!< error interrupt enable */ 233 #define CAN_INTEN_WIE BIT(16) /*!< wakeup interrupt enable */ 234 #define CAN_INTEN_SLPWIE BIT(17) /*!< sleep working interrupt enable */ 235 236 /* CAN_ERR */ 237 #define CAN_ERR_WERR BIT(0) /*!< warning error */ 238 #define CAN_ERR_PERR BIT(1) /*!< passive error */ 239 #define CAN_ERR_BOERR BIT(2) /*!< bus-off error */ 240 #define CAN_ERR_ERRN BITS(4,6) /*!< error number */ 241 #define CAN_ERR_TECNT BITS(16,23) /*!< transmit error count */ 242 #define CAN_ERR_RECNT BITS(24,31) /*!< receive error count */ 243 244 /* CAN_BT */ 245 #define CAN_BT_BAUDPSC BITS(0,9) /*!< baudrate prescaler */ 246 #ifdef GD32E508 247 #define CAN_BT_BS1_6_4 BITS(10,12) /*!< bit segment 1 [6:4] */ 248 #define CAN_BT_BS2_4_3 BITS(13,14) /*!< bit segment 2 [4:3] */ 249 #endif /* GD32E508 */ 250 #define CAN_BT_BS1_3_0 BITS(16,19) /*!< bit segment 1 [3:0] */ 251 #define CAN_BT_BS2_2_0 BITS(20,22) /*!< bit segment 2 [2:0]*/ 252 #define CAN_BT_SJW BITS(24,28) /*!< resynchronization jump width */ 253 #define CAN_BT_LCMOD BIT(30) /*!< loopback communication mode */ 254 #define CAN_BT_SCMOD BIT(31) /*!< silent communication mode */ 255 256 #ifdef GD32E508 257 /* CAN_FDCTL */ 258 #define CAN_FDCTL_FDEN BIT(0) /*!< FD operation enable */ 259 #define CAN_FDCTL_PRED BIT(2) /*!< protocol exception event detection disable */ 260 #define CAN_FDCTL_NISO BIT(3) /*!< ISO/Bosch */ 261 #define CAN_FDCTL_TDCEN BIT(4) /*!< transmitter delay compensation enable */ 262 #define CAN_FDCTL_TDCMOD BIT(5) /*!< transmitter delay compensation mode */ 263 #define CAN_FDCTL_ESIMOD BIT(6) /*!< error state indicator mode */ 264 265 /* CAN_FDSTAT */ 266 #define CAN_FDSTAT_TDCV BITS(0,6) /*!< transmitter delay compensation value */ 267 #define CAN_FDSTAT_PRE BIT(16) /*!< protocol exception event */ 268 269 /* CAN_FDTDC */ 270 #define CAN_FDTDC_TDCF BITS(0,6) /*!< transmitter delay compensation filter */ 271 #define CAN_FDTDC_TDCO BITS(8,14) /*!< transmitter delay compensation offset */ 272 273 /* CAN_DBT */ 274 #define CAN_DBT_DBAUDPSC BITS(0,9) /*!< baud rate prescaler */ 275 #define CAN_DBT_DBS1 BITS(16,19) /*!< bit segment 1 */ 276 #define CAN_DBT_DBS2 BITS(20,22) /*!< bit segment 2 */ 277 #define CAN_DBT_DSJW BITS(24,26) /*!< resynchronization jump width */ 278 #endif /* GD32E508 */ 279 280 /* CAN_TMIx */ 281 #define CAN_TMI_TEN BIT(0) /*!< transmit enable */ 282 #define CAN_TMI_FT BIT(1) /*!< frame type */ 283 #define CAN_TMI_FF BIT(2) /*!< frame format */ 284 #define CAN_TMI_EFID BITS(3,31) /*!< the frame identifier */ 285 #define CAN_TMI_SFID BITS(21,31) /*!< the frame identifier */ 286 287 /* CAN_TMPx */ 288 #define CAN_TMP_DLENC BITS(0,3) /*!< data length code */ 289 #ifdef GD32E508 290 #define CAN_TMP_ESI BIT(4) /*!< error status indicator */ 291 #define CAN_TMP_BRS BIT(5) /*!< bit rate of data switch */ 292 #define CAN_TMP_FDF BIT(7) /*!< CAN FD frame flag */ 293 #endif /* GD32E508 */ 294 #define CAN_TMP_TSEN BIT(8) /*!< time stamp enable */ 295 #define CAN_TMP_TS BITS(16,31) /*!< time stamp */ 296 297 /* CAN_TMDATA0x */ 298 #define CAN_TMDATA0_DB0 BITS(0,7) /*!< transmit data byte 0 */ 299 #define CAN_TMDATA0_DB1 BITS(8,15) /*!< transmit data byte 1 */ 300 #define CAN_TMDATA0_DB2 BITS(16,23) /*!< transmit data byte 2 */ 301 #define CAN_TMDATA0_DB3 BITS(24,31) /*!< transmit data byte 3 */ 302 303 /* CAN_TMDATA1x */ 304 #define CAN_TMDATA1_DB4 BITS(0,7) /*!< transmit data byte 4 */ 305 #define CAN_TMDATA1_DB5 BITS(8,15) /*!< transmit data byte 5 */ 306 #define CAN_TMDATA1_DB6 BITS(16,23) /*!< transmit data byte 6 */ 307 #define CAN_TMDATA1_DB7 BITS(24,31) /*!< transmit data byte 7 */ 308 309 /* CAN_RFIFOMIx */ 310 #define CAN_RFIFOMI_FT BIT(1) /*!< frame type */ 311 #define CAN_RFIFOMI_FF BIT(2) /*!< frame format */ 312 #define CAN_RFIFOMI_EFID BITS(3,31) /*!< the frame identifier */ 313 #define CAN_RFIFOMI_SFID BITS(21,31) /*!< the frame identifier */ 314 315 /* CAN_RFIFOMPx */ 316 #define CAN_RFIFOMP_DLENC BITS(0,3) /*!< receive data length code */ 317 #ifdef GD32E508 318 #define CAN_RFIFOMP_ESI BIT(4) /*!< error status indicator */ 319 #define CAN_RFIFOMP_BRS BIT(5) /*!< bit rate of data switch */ 320 #define CAN_RFIFOMP_FDF BIT(7) /*!< CAN FD frame flag */ 321 #endif /* GD32E508 */ 322 #define CAN_RFIFOMP_FI BITS(8,15) /*!< filter index */ 323 #define CAN_RFIFOMP_TS BITS(16,31) /*!< time stamp */ 324 325 /* CAN_RFIFOMDATA0x */ 326 #define CAN_RFIFOMDATA0_DB0 BITS(0,7) /*!< receive data byte 0 */ 327 #define CAN_RFIFOMDATA0_DB1 BITS(8,15) /*!< receive data byte 1 */ 328 #define CAN_RFIFOMDATA0_DB2 BITS(16,23) /*!< receive data byte 2 */ 329 #define CAN_RFIFOMDATA0_DB3 BITS(24,31) /*!< receive data byte 3 */ 330 331 /* CAN_RFIFOMDATA1x */ 332 #define CAN_RFIFOMDATA1_DB4 BITS(0,7) /*!< receive data byte 4 */ 333 #define CAN_RFIFOMDATA1_DB5 BITS(8,15) /*!< receive data byte 5 */ 334 #define CAN_RFIFOMDATA1_DB6 BITS(16,23) /*!< receive data byte 6 */ 335 #define CAN_RFIFOMDATA1_DB7 BITS(24,31) /*!< receive data byte 7 */ 336 337 /* CAN_FCTL */ 338 #define CAN_FCTL_FLD BIT(0) /*!< filter lock disable */ 339 #define CAN_FCTL_HBC1F BITS(8,13) /*!< header bank of CAN1 filter */ 340 341 /* CAN_FMCFG */ 342 #define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask*/ 343 344 /* CAN_FSCFG */ 345 #define CAN_FSCFG_FS(regval) BIT(regval) /*!< filter scale, 32 bits or 16 bits*/ 346 347 /* CAN_FAFIFO */ 348 #define CAN_FAFIFOR_FAF(regval) BIT(regval) /*!< filter associated with FIFO */ 349 350 /* CAN_FW */ 351 #define CAN_FW_FW(regval) BIT(regval) /*!< filter working */ 352 353 /* CAN_FxDATAy */ 354 #define CAN_FDATA_FD(regval) BIT(regval) /*!< filter data */ 355 356 /* consts definitions */ 357 /* define the CAN bit position and its register index offset */ 358 #define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) 359 #define CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6))) 360 #define CAN_BIT_POS(val) ((uint32_t)(val) & 0x1FU) 361 362 #define CAN_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1)) 363 #define CAN_REG_VALS(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 12))) 364 #define CAN_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU) 365 #define CAN_BIT_POS1(val) ((uint32_t)(val) & 0x1FU) 366 367 /* register offset */ 368 #define STAT_REG_OFFSET ((uint8_t)0x04U) /*!< STAT register offset */ 369 #define TSTAT_REG_OFFSET ((uint8_t)0x08U) /*!< TSTAT register offset */ 370 #define RFIFO0_REG_OFFSET ((uint8_t)0x0CU) /*!< RFIFO0 register offset */ 371 #define RFIFO1_REG_OFFSET ((uint8_t)0x10U) /*!< RFIFO1 register offset */ 372 #define ERR_REG_OFFSET ((uint8_t)0x18U) /*!< ERR register offset */ 373 374 /* CAN flags */ 375 typedef enum 376 { 377 /* flags in STAT register */ 378 CAN_FLAG_RXL = CAN_REGIDX_BIT(STAT_REG_OFFSET, 11U), /*!< RX level */ 379 CAN_FLAG_LASTRX = CAN_REGIDX_BIT(STAT_REG_OFFSET, 10U), /*!< last sample value of RX pin */ 380 CAN_FLAG_RS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 9U), /*!< receiving state */ 381 CAN_FLAG_TS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 8U), /*!< transmitting state */ 382 CAN_FLAG_SLPIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 4U), /*!< status change flag of entering sleep working mode */ 383 CAN_FLAG_WUIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 3U), /*!< status change flag of wakeup from sleep working mode */ 384 CAN_FLAG_ERRIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 2U), /*!< error flag */ 385 CAN_FLAG_SLPWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 1U), /*!< sleep working state */ 386 CAN_FLAG_IWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 0U), /*!< initial working state */ 387 /* flags in TSTAT register */ 388 CAN_FLAG_TMLS2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 31U), /*!< transmit mailbox 2 last sending in Tx FIFO */ 389 CAN_FLAG_TMLS1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 30U), /*!< transmit mailbox 1 last sending in Tx FIFO */ 390 CAN_FLAG_TMLS0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 29U), /*!< transmit mailbox 0 last sending in Tx FIFO */ 391 CAN_FLAG_TME2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 28U), /*!< transmit mailbox 2 empty */ 392 CAN_FLAG_TME1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 27U), /*!< transmit mailbox 1 empty */ 393 CAN_FLAG_TME0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 26U), /*!< transmit mailbox 0 empty */ 394 CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */ 395 CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */ 396 CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U), /*!< mailbox 0 transmit error */ 397 CAN_FLAG_MAL2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 18U), /*!< mailbox 2 arbitration lost */ 398 CAN_FLAG_MAL1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 10U), /*!< mailbox 1 arbitration lost */ 399 CAN_FLAG_MAL0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 2U), /*!< mailbox 0 arbitration lost */ 400 CAN_FLAG_MTFNERR2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 17U), /*!< mailbox 2 transmit finished with no error */ 401 CAN_FLAG_MTFNERR1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 9U), /*!< mailbox 1 transmit finished with no error */ 402 CAN_FLAG_MTFNERR0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 1U), /*!< mailbox 0 transmit finished with no error */ 403 CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U), /*!< mailbox 2 transmit finished */ 404 CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U), /*!< mailbox 1 transmit finished */ 405 CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U), /*!< mailbox 0 transmit finished */ 406 /* flags in RFIFO0 register */ 407 CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U), /*!< receive FIFO0 overfull */ 408 CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U), /*!< receive FIFO0 full */ 409 /* flags in RFIFO1 register */ 410 CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U), /*!< receive FIFO1 overfull */ 411 CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U), /*!< receive FIFO1 full */ 412 /* flags in ERR register */ 413 CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */ 414 CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */ 415 CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */ 416 }can_flag_enum; 417 418 /* CAN interrupt flags */ 419 typedef enum 420 { 421 /* interrupt flags in STAT register */ 422 CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */ 423 CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */ 424 CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15), /*!< error interrupt flag */ 425 /* interrupt flags in TSTAT register */ 426 CAN_INT_FLAG_MTF2 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 16U, 0U), /*!< mailbox 2 transmit finished interrupt flag */ 427 CAN_INT_FLAG_MTF1 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 8U, 0U), /*!< mailbox 1 transmit finished interrupt flag */ 428 CAN_INT_FLAG_MTF0 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 0U, 0U), /*!< mailbox 0 transmit finished interrupt flag */ 429 /* interrupt flags in RFIFO0 register */ 430 CAN_INT_FLAG_RFO0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 4U, 3U), /*!< receive FIFO0 overfull interrupt flag */ 431 CAN_INT_FLAG_RFF0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 3U, 2U), /*!< receive FIFO0 full interrupt flag */ 432 CAN_INT_FLAG_RFL0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 2U, 1U), /*!< receive FIFO0 not empty interrupt flag */ 433 /* interrupt flags in RFIFO0 register */ 434 CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U), /*!< receive FIFO1 overfull interrupt flag */ 435 CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U), /*!< receive FIFO1 full interrupt flag */ 436 CAN_INT_FLAG_RFL1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 2U, 4U), /*!< receive FIFO0 not empty interrupt flag */ 437 /* interrupt flags in ERR register */ 438 CAN_INT_FLAG_ERRN = CAN_REGIDX_BITS(ERR_REG_OFFSET, 3U, 11U), /*!< error number interrupt flag */ 439 CAN_INT_FLAG_BOERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 2U, 10U), /*!< bus-off error interrupt flag */ 440 CAN_INT_FLAG_PERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 1U, 9U), /*!< passive error interrupt flag */ 441 CAN_INT_FLAG_WERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 0U, 8U), /*!< warning error interrupt flag */ 442 }can_interrupt_flag_enum; 443 444 /* CAN initiliaze parameters struct */ 445 typedef struct 446 { 447 uint8_t working_mode; /*!< CAN working mode */ 448 uint8_t resync_jump_width; /*!< CAN resynchronization jump width */ 449 uint8_t time_segment_1; /*!< time segment 1 */ 450 uint8_t time_segment_2; /*!< time segment 2 */ 451 ControlStatus time_triggered; /*!< time triggered communication mode */ 452 ControlStatus auto_bus_off_recovery; /*!< automatic bus-off recovery */ 453 ControlStatus auto_wake_up; /*!< automatic wake-up mode */ 454 ControlStatus auto_retrans; /*!< automatic retransmission mode disable */ 455 ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode */ 456 ControlStatus trans_fifo_order; /*!< transmit FIFO order */ 457 uint16_t prescaler; /*!< baudrate prescaler */ 458 }can_parameter_struct; 459 460 #ifdef GD32E508 461 /* CAN FD transmitter delay compensation parameters struct */ 462 typedef struct 463 { 464 uint32_t tdc_mode; /*!< transmitter delay compensation mode */ 465 uint8_t tdc_filter; /*!< transmitter delay compensation filter */ 466 uint8_t tdc_offset; /*!< transmitter delay compensation offset */ 467 }can_fd_tdc_struct; 468 469 /* CAN initiliaze FD frame parameters struct */ 470 typedef struct 471 { 472 ControlStatus fd_frame; /*!< FD operation function */ 473 ControlStatus excp_event_detect; /*!< protocol exception event detection function*/ 474 ControlStatus delay_compensation; /*!< transmitter delay compensation mode */ 475 can_fd_tdc_struct *p_delay_compensation; /*!< pointer to the struct of the transmitter delay compensation */ 476 uint32_t iso_bosch; /*!< ISO/Bosch mode choice */ 477 uint32_t esi_mode; /*!< error state indicator mode */ 478 uint8_t data_resync_jump_width; /*!< CAN resynchronization jump width */ 479 uint8_t data_time_segment_1; /*!< time segment 1 */ 480 uint8_t data_time_segment_2; /*!< time segment 2 */ 481 uint16_t data_prescaler; /*!< baudrate prescaler */ 482 }can_fdframe_struct; 483 484 /* CAN transmit message struct */ 485 typedef struct 486 { 487 uint32_t tx_sfid; /*!< standard format frame identifier */ 488 uint32_t tx_efid; /*!< extended format frame identifier */ 489 uint8_t tx_ff; /*!< format of frame, standard or extended format */ 490 uint8_t tx_ft; /*!< type of frame, data or remote */ 491 uint8_t tx_dlen; /*!< data length */ 492 uint8_t tx_data[64]; /*!< transmit data */ 493 uint8_t fd_flag; /*!< CAN FD frame flag */ 494 uint8_t fd_brs; /*!< bit rate of data switch */ 495 uint8_t fd_esi; /*!< error status indicator */ 496 }can_trasnmit_message_struct; 497 498 /* CAN receive message struct */ 499 typedef struct 500 { 501 uint32_t rx_sfid; /*!< standard format frame identifier */ 502 uint32_t rx_efid; /*!< extended format frame identifier */ 503 uint8_t rx_ff; /*!< format of frame, standard or extended format */ 504 uint8_t rx_ft; /*!< type of frame, data or remote */ 505 uint8_t rx_dlen; /*!< data length */ 506 uint8_t rx_data[64]; /*!< receive data */ 507 uint8_t rx_fi; /*!< filtering index */ 508 uint8_t fd_flag; /*!< CAN FD frame flag */ 509 uint8_t fd_brs; /*!< bit rate of data switch */ 510 uint8_t fd_esi; /*!< error status indicator */ 511 } can_receive_message_struct; 512 #else 513 /* CAN transmit message struct */ 514 typedef struct 515 { 516 uint32_t tx_sfid; /*!< standard format frame identifier */ 517 uint32_t tx_efid; /*!< extended format frame identifier */ 518 uint8_t tx_ff; /*!< format of frame, standard or extended format */ 519 uint8_t tx_ft; /*!< type of frame, data or remote */ 520 uint8_t tx_dlen; /*!< data length */ 521 uint8_t tx_data[8]; /*!< transmit data */ 522 }can_trasnmit_message_struct; 523 524 /* CAN receive message struct */ 525 typedef struct 526 { 527 uint32_t rx_sfid; /*!< standard format frame identifier */ 528 uint32_t rx_efid; /*!< extended format frame identifier */ 529 uint8_t rx_ff; /*!< format of frame, standard or extended format */ 530 uint8_t rx_ft; /*!< type of frame, data or remote */ 531 uint8_t rx_dlen; /*!< data length */ 532 uint8_t rx_data[8]; /*!< receive data */ 533 uint8_t rx_fi; /*!< filtering index */ 534 } can_receive_message_struct; 535 #endif /* GD32E508 */ 536 537 /* CAN filter parameters struct */ 538 typedef struct 539 { 540 uint16_t filter_list_high; /*!< filter list number high bits*/ 541 uint16_t filter_list_low; /*!< filter list number low bits */ 542 uint16_t filter_mask_high; /*!< filter mask number high bits */ 543 uint16_t filter_mask_low; /*!< filter mask number low bits */ 544 uint16_t filter_fifo_number; /*!< receive FIFO associated with the filter */ 545 uint16_t filter_number; /*!< filter number */ 546 uint16_t filter_mode; /*!< filter mode, list or mask */ 547 uint16_t filter_bits; /*!< filter scale */ 548 ControlStatus filter_enable; /*!< filter work or not */ 549 }can_filter_parameter_struct; 550 551 /* CAN errors */ 552 typedef enum 553 { 554 CAN_ERROR_NONE = 0U, /*!< no error */ 555 CAN_ERROR_FILL, /*!< fill error */ 556 CAN_ERROR_FORMATE, /*!< format error */ 557 CAN_ERROR_ACK, /*!< ACK error */ 558 CAN_ERROR_BITRECESSIVE, /*!< bit recessive error */ 559 CAN_ERROR_BITDOMINANTER, /*!< bit dominant error */ 560 CAN_ERROR_CRC, /*!< CRC error */ 561 CAN_ERROR_SOFTWARECFG, /*!< software configure */ 562 }can_error_enum; 563 564 /* transmit states */ 565 typedef enum 566 { 567 CAN_TRANSMIT_FAILED = 0U, /*!< CAN transmitted failure */ 568 CAN_TRANSMIT_OK = 1U, /*!< CAN transmitted success */ 569 CAN_TRANSMIT_PENDING = 2U, /*!< CAN transmitted pending */ 570 CAN_TRANSMIT_NOMAILBOX = 4U, /*!< no empty mailbox to be used for CAN */ 571 }can_transmit_state_enum; 572 573 /* format and fifo states */ 574 typedef enum 575 { 576 CAN_STANDARD_FIFO0 = 0U, /*!< standard frame and used FIFO0 */ 577 CAN_STANDARD_FIFO1, /*!< standard frame and used FIFO1 */ 578 CAN_EXTENDED_FIFO0, /*!< extended frame and used FIFO0 */ 579 CAN_EXTENDED_FIFO1, /*!< extended frame and used FIFO1 */ 580 }can_format_fifo_enum; 581 582 typedef enum 583 { 584 CAN_INIT_STRUCT = 0U, /* CAN initiliaze parameters struct */ 585 CAN_FILTER_STRUCT, /* CAN filter parameters struct */ 586 CAN_FD_FRAME_STRUCT, /* CAN initiliaze FD frame parameters struct */ 587 CAN_TX_MESSAGE_STRUCT, /* CAN transmit message struct */ 588 CAN_RX_MESSAGE_STRUCT, /* CAN receive message struct */ 589 }can_struct_type_enum; 590 591 #ifdef GD32E508 592 /* CAN baudrate prescaler*/ 593 #define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0)) 594 595 /* CAN bit segment 1*/ 596 #define BT_BS1(regval) ((BITS(16,19) & ((uint32_t)(regval) << 16)) | (BITS(10,12) & ((uint32_t)(regval) << 6))) 597 #define BT_DBS1(regval) ((BITS(16,19) & ((uint32_t)(regval) << 16))) 598 599 /* CAN bit segment 2*/ 600 #define BT_BS2(regval) ((BITS(20,22) & ((uint32_t)(regval) << 20)) | (BITS(13,14) & ((uint32_t)(regval) << 10))) 601 #define BT_DBS2(regval) ((BITS(20,22)) & ((uint32_t)(regval) << 20)) 602 603 /* CAN resynchronization jump width*/ 604 #define BT_SJW(regval) (BITS(24,28) & ((uint32_t)(regval) << 24)) 605 #define BT_DSJW(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) 606 607 #define FDTDC_TDCF(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) 608 #define FDTDC_TDCO(regval) (BITS(8,14) & ((uint32_t)(regval) << 8)) 609 #else 610 /* CAN baudrate prescaler*/ 611 #define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0)) 612 613 /* CAN bit segment 1*/ 614 #define BT_BS1(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) 615 616 /* CAN bit segment 2*/ 617 #define BT_BS2(regval) (BITS(20,22) & ((uint32_t)(regval) << 20)) 618 619 /* CAN resynchronization jump width*/ 620 #define BT_SJW(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) 621 #endif /* GD32E508 */ 622 623 /* CAN communication mode*/ 624 #define BT_MODE(regval) (BITS(30,31) & ((uint32_t)(regval) << 30)) 625 626 /* CAN FDATA high 16 bits */ 627 #define FDATA_MASK_HIGH(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) 628 629 /* CAN FDATA low 16 bits */ 630 #define FDATA_MASK_LOW(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) 631 632 /* CAN1 filter start bank_number*/ 633 #define FCTL_HBC1F(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) 634 635 /* CAN transmit mailbox extended identifier*/ 636 #define TMI_EFID(regval) (BITS(3,31) & ((uint32_t)(regval) << 3)) 637 638 /* CAN transmit mailbox standard identifier*/ 639 #define TMI_SFID(regval) (BITS(21,31) & ((uint32_t)(regval) << 21)) 640 641 /* transmit data byte 0 */ 642 #define TMDATA0_DB0(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) 643 644 /* transmit data byte 1 */ 645 #define TMDATA0_DB1(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) 646 647 /* transmit data byte 2 */ 648 #define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) 649 650 /* transmit data byte 3 */ 651 #define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) 652 653 /* transmit data byte 4 */ 654 #define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) 655 656 /* transmit data byte 5 */ 657 #define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) 658 659 /* transmit data byte 6 */ 660 #define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) 661 662 /* transmit data byte 7 */ 663 #define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) 664 665 /* receive mailbox extended identifier*/ 666 #define GET_RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3, 31) 667 668 /* receive mailbox standrad identifier*/ 669 #define GET_RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21, 31) 670 671 /* receive data length */ 672 #define GET_RFIFOMP_DLENC(regval) GET_BITS((uint32_t)(regval), 0, 3) 673 674 /* the index of the filter by which the frame is passed */ 675 #define GET_RFIFOMP_FI(regval) GET_BITS((uint32_t)(regval), 8, 15) 676 677 /* receive data byte 0 */ 678 #define GET_RFIFOMDATA0_DB0(regval) GET_BITS((uint32_t)(regval), 0, 7) 679 680 /* receive data byte 1 */ 681 #define GET_RFIFOMDATA0_DB1(regval) GET_BITS((uint32_t)(regval), 8, 15) 682 683 /* receive data byte 2 */ 684 #define GET_RFIFOMDATA0_DB2(regval) GET_BITS((uint32_t)(regval), 16, 23) 685 686 /* receive data byte 3 */ 687 #define GET_RFIFOMDATA0_DB3(regval) GET_BITS((uint32_t)(regval), 24, 31) 688 689 /* receive data byte 4 */ 690 #define GET_RFIFOMDATA1_DB4(regval) GET_BITS((uint32_t)(regval), 0, 7) 691 692 /* receive data byte 5 */ 693 #define GET_RFIFOMDATA1_DB5(regval) GET_BITS((uint32_t)(regval), 8, 15) 694 695 /* receive data byte 6 */ 696 #define GET_RFIFOMDATA1_DB6(regval) GET_BITS((uint32_t)(regval), 16, 23) 697 698 /* receive data byte 7 */ 699 #define GET_RFIFOMDATA1_DB7(regval) GET_BITS((uint32_t)(regval), 24, 31) 700 701 /* error number */ 702 #define GET_ERR_ERRN(regval) GET_BITS((uint32_t)(regval), 4, 6) 703 704 /* transmit error count */ 705 #define GET_ERR_TECNT(regval) GET_BITS((uint32_t)(regval), 16, 23) 706 707 /* receive error count */ 708 #define GET_ERR_RECNT(regval) GET_BITS((uint32_t)(regval), 24, 31) 709 710 /* CAN errors */ 711 #define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4)) 712 #define CAN_ERRN_0 ERR_ERRN(0) /* no error */ 713 #define CAN_ERRN_1 ERR_ERRN(1) /*!< fill error */ 714 #define CAN_ERRN_2 ERR_ERRN(2) /*!< format error */ 715 #define CAN_ERRN_3 ERR_ERRN(3) /*!< ACK error */ 716 #define CAN_ERRN_4 ERR_ERRN(4) /*!< bit recessive error */ 717 #define CAN_ERRN_5 ERR_ERRN(5) /*!< bit dominant error */ 718 #define CAN_ERRN_6 ERR_ERRN(6) /*!< CRC error */ 719 #define CAN_ERRN_7 ERR_ERRN(7) /*!< software error */ 720 721 #define CAN_STATE_PENDING ((uint32_t)0x00000000U) /*!< CAN pending */ 722 723 /* CAN communication mode */ 724 #define CAN_NORMAL_MODE ((uint8_t)0x00U) /*!< normal communication mode */ 725 #define CAN_LOOPBACK_MODE ((uint8_t)0x01U) /*!< loopback communication mode */ 726 #define CAN_SILENT_MODE ((uint8_t)0x02U) /*!< silent communication mode */ 727 #define CAN_SILENT_LOOPBACK_MODE ((uint8_t)0x03U) /*!< loopback and silent communication mode */ 728 729 /* CAN resynchronisation jump width */ 730 #define CAN_BT_SJW_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ 731 #define CAN_BT_SJW_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ 732 #define CAN_BT_SJW_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ 733 #define CAN_BT_SJW_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ 734 735 /* CAN time segment 1 */ 736 #define CAN_BT_BS1_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ 737 #define CAN_BT_BS1_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ 738 #define CAN_BT_BS1_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ 739 #define CAN_BT_BS1_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ 740 #define CAN_BT_BS1_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */ 741 #define CAN_BT_BS1_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */ 742 #define CAN_BT_BS1_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */ 743 #define CAN_BT_BS1_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */ 744 #define CAN_BT_BS1_9TQ ((uint8_t)0x08U) /*!< 9 time quanta */ 745 #define CAN_BT_BS1_10TQ ((uint8_t)0x09U) /*!< 10 time quanta */ 746 #define CAN_BT_BS1_11TQ ((uint8_t)0x0AU) /*!< 11 time quanta */ 747 #define CAN_BT_BS1_12TQ ((uint8_t)0x0BU) /*!< 12 time quanta */ 748 #define CAN_BT_BS1_13TQ ((uint8_t)0x0CU) /*!< 13 time quanta */ 749 #define CAN_BT_BS1_14TQ ((uint8_t)0x0DU) /*!< 14 time quanta */ 750 #define CAN_BT_BS1_15TQ ((uint8_t)0x0EU) /*!< 15 time quanta */ 751 #define CAN_BT_BS1_16TQ ((uint8_t)0x0FU) /*!< 16 time quanta */ 752 753 /* CAN time segment 2 */ 754 #define CAN_BT_BS2_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ 755 #define CAN_BT_BS2_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ 756 #define CAN_BT_BS2_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ 757 #define CAN_BT_BS2_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ 758 #define CAN_BT_BS2_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */ 759 #define CAN_BT_BS2_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */ 760 #define CAN_BT_BS2_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */ 761 #define CAN_BT_BS2_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */ 762 763 /* CAN mailbox number */ 764 #define CAN_MAILBOX0 ((uint8_t)0x00U) /*!< mailbox0 */ 765 #define CAN_MAILBOX1 ((uint8_t)0x01U) /*!< mailbox1 */ 766 #define CAN_MAILBOX2 ((uint8_t)0x02U) /*!< mailbox2 */ 767 #define CAN_NOMAILBOX ((uint8_t)0x03U) /*!< no mailbox empty */ 768 769 /* CAN frame format */ 770 #define CAN_FF_STANDARD ((uint32_t)0x00000000U) /*!< standard frame */ 771 #define CAN_FF_EXTENDED ((uint32_t)0x00000004U) /*!< extended frame */ 772 773 /* CAN receive fifo */ 774 #define CAN_FIFO0 ((uint8_t)0x00U) /*!< receive FIFO0 */ 775 #define CAN_FIFO1 ((uint8_t)0x01U) /*!< receive FIFO1 */ 776 777 /* frame number of receive fifo */ 778 #define CAN_RFIF_RFL_MASK ((uint32_t)0x00000003U) /*!< mask for frame number in receive FIFOx */ 779 780 #define CAN_SFID_MASK ((uint32_t)0x000007FFU) /*!< mask of standard identifier */ 781 #define CAN_EFID_MASK ((uint32_t)0x1FFFFFFFU) /*!< mask of extended identifier */ 782 783 /* CAN working mode */ 784 #define GD32_CAN_MODE_INITIALIZE ((uint8_t)0x01U) /*!< CAN initialize mode */ 785 #define GD32_CAN_MODE_NORMAL ((uint8_t)0x02U) /*!< CAN normal mode */ 786 #define GD32_CAN_MODE_SLEEP ((uint8_t)0x04U) /*!< CAN sleep mode */ 787 788 /* filter bits */ 789 #define CAN_FILTERBITS_16BIT ((uint8_t)0x00U) /*!< CAN filter 16 bits */ 790 #define CAN_FILTERBITS_32BIT ((uint8_t)0x01U) /*!< CAN filter 32 bits */ 791 792 /* filter mode */ 793 #define CAN_FILTERMODE_MASK ((uint8_t)0x00U) /*!< mask mode */ 794 #define CAN_FILTERMODE_LIST ((uint8_t)0x01U) /*!< list mode */ 795 796 /* filter 16 bits mask */ 797 #define CAN_FILTER_MASK_16BITS ((uint32_t)0x0000FFFFU) /*!< can filter 16 bits mask */ 798 799 /* frame type */ 800 #define CAN_FT_DATA ((uint32_t)0x00000000U) /*!< data frame */ 801 #define CAN_FT_REMOTE ((uint32_t)0x00000002U) /*!< remote frame */ 802 803 #ifdef GD32E508 804 #define CAN_ESIMOD_HARDWARE ((uint32_t)0x00000000U) /*!< displays the node error state by hardware */ 805 #define CAN_ESIMOD_SOFTWARE CAN_FDCTL_ESIMOD /*!< displays the node error state by software */ 806 807 #define CAN_TDCMOD_CALC_AND_OFFSET ((uint32_t)0x00000000U) /*!< measurement and offset */ 808 #define CAN_TDCMOD_OFFSET CAN_FDCTL_TDCMOD /*!< only offset */ 809 810 #define CAN_FDMOD_ISO ((uint32_t)0x00000000U) /*!< ISO mode */ 811 #define CAN_FDMOD_BOSCH CAN_FDCTL_NISO /*!< BOSCH mode */ 812 813 /* CAN FD frame flag */ 814 #define CAN_FDF_CLASSIC (0U) /*!< classical frames */ 815 #define CAN_FDF_FDFRAME (1U) /*!< FD frames */ 816 817 /* bit rate of data switch */ 818 #define CAN_BRS_DISABLE (0U) /*!< bit rate not switch */ 819 #define CAN_BRS_ENABLE (1U) /*!< the bit rate shall be switched */ 820 821 /* error status indicator */ 822 #define CAN_ESI_DOMINANT (0U) /*!< transmit the dominant bit in ESI phase */ 823 #define CAN_ESI_RECESSIVE (1U) /*!< transmit the recessive bit in ESI phase */ 824 825 #endif /* GD32E508 */ 826 827 /* CAN timeout */ 828 #define CAN_TIMEOUT ((uint32_t)0x0000FFFFU) /*!< timeout value */ 829 830 /* interrupt enable bits */ 831 #define CAN_INT_TME CAN_INTEN_TMEIE /*!< transmit mailbox empty interrupt enable */ 832 #define CAN_INT_RFNE0 CAN_INTEN_RFNEIE0 /*!< receive FIFO0 not empty interrupt enable */ 833 #define CAN_INT_RFF0 CAN_INTEN_RFFIE0 /*!< receive FIFO0 full interrupt enable */ 834 #define CAN_INT_RFO0 CAN_INTEN_RFOIE0 /*!< receive FIFO0 overfull interrupt enable */ 835 #define CAN_INT_RFNE1 CAN_INTEN_RFNEIE1 /*!< receive FIFO1 not empty interrupt enable */ 836 #define CAN_INT_RFF1 CAN_INTEN_RFFIE1 /*!< receive FIFO1 full interrupt enable */ 837 #define CAN_INT_RFO1 CAN_INTEN_RFOIE1 /*!< receive FIFO1 overfull interrupt enable */ 838 #define CAN_INT_WERR CAN_INTEN_WERRIE /*!< warning error interrupt enable */ 839 #define CAN_INT_PERR CAN_INTEN_PERRIE /*!< passive error interrupt enable */ 840 #define CAN_INT_BO CAN_INTEN_BOIE /*!< bus-off interrupt enable */ 841 #define CAN_INT_ERRN CAN_INTEN_ERRNIE /*!< error number interrupt enable */ 842 #define CAN_INT_ERR CAN_INTEN_ERRIE /*!< error interrupt enable */ 843 #define CAN_INT_WAKEUP CAN_INTEN_WIE /*!< wakeup interrupt enable */ 844 #define CAN_INT_SLPW CAN_INTEN_SLPWIE /*!< sleep working interrupt enable */ 845 846 /* function declarations */ 847 /* deinitialize CAN */ 848 void can_deinit(uint32_t can_periph); 849 /* initialize CAN parameter struct */ 850 void can_struct_para_init(can_struct_type_enum type, void* p_struct); 851 /* initialize CAN */ 852 ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init); 853 /* initialize CAN filter */ 854 void can_filter_init(uint32_t can_periph, can_filter_parameter_struct* can_filter_parameter_init); 855 /* CAN filter mask mode initialization */ 856 void can_filter_mask_mode_init(uint32_t can_periph, uint32_t id, uint32_t mask, can_format_fifo_enum format_fifo, uint16_t filter_number); 857 /* CAN baud rate configure in classic mode */ 858 ErrStatus can_frequency_set(uint32_t can_periph, uint32_t hz); 859 /* CAN communication mode configure */ 860 ErrStatus can_monitor_mode_set(uint32_t can_periph, uint8_t mode); 861 862 #ifdef GD32E508 863 /* initialize CAN FD function */ 864 ErrStatus can_fd_init(uint32_t can_periph, can_fdframe_struct* can_fdframe_init); 865 /* CAN baud rate configure in FD mode */ 866 ErrStatus can_fd_frequency_set(uint32_t can_periph, uint32_t hz); 867 /* CAN FD frame function enable */ 868 void can_fd_function_enable(uint32_t can_periph); 869 /* CAN FD frame function disable */ 870 void can_fd_function_disable(uint32_t can_periph); 871 #endif /* GD32E508 */ 872 873 /* set can1 fliter start bank number */ 874 void can1_filter_start_bank(uint8_t start_bank); 875 /* enable functions */ 876 /* CAN debug freeze enable */ 877 void can_debug_freeze_enable(uint32_t can_periph); 878 /* CAN debug freeze disable */ 879 void can_debug_freeze_disable(uint32_t can_periph); 880 /* CAN time trigger mode enable */ 881 void can_time_trigger_mode_enable(uint32_t can_periph); 882 /* CAN time trigger mode disable */ 883 void can_time_trigger_mode_disable(uint32_t can_periph); 884 885 /* transmit CAN message */ 886 uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message); 887 /* get CAN transmit state */ 888 can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number); 889 /* stop CAN transmission */ 890 void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number); 891 /* CAN receive message */ 892 void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message); 893 /* CAN release fifo */ 894 void can_fifo_release(uint32_t can_periph, uint8_t fifo_number); 895 /* CAN receive message length */ 896 uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number); 897 /* CAN working mode */ 898 ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode); 899 /* CAN wakeup from sleep mode */ 900 ErrStatus can_wakeup(uint32_t can_periph); 901 902 /* CAN get error */ 903 can_error_enum can_error_get(uint32_t can_periph); 904 /* get CAN receive error number */ 905 uint8_t can_receive_error_number_get(uint32_t can_periph); 906 /* get CAN transmit error number */ 907 uint8_t can_transmit_error_number_get(uint32_t can_periph); 908 909 /* CAN interrupt enable */ 910 void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt); 911 /* CAN interrupt disable */ 912 void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt); 913 /* CAN get flag state */ 914 FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag); 915 /* CAN clear flag state */ 916 void can_flag_clear(uint32_t can_periph, can_flag_enum flag); 917 /* CAN get interrupt flag state */ 918 FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum int_flag); 919 /* CAN clear interrupt flag state */ 920 void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum int_flag); 921 922 #endif /* GD32E50X_CAN_H */ 923
