Searched refs:AHBRST_REG_OFFSET (Results 1 – 6 of 6) sorted by relevance
| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32a50x/standard_peripheral/include/ |
| D | gd32a50x_rcu.h | 263 #define AHBRST_REG_OFFSET 0x00000028U /*!< AHB reset registe… macro
327 … RCU_DMA0RST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 0U), /*!< DMA0 clock reset */
328 … RCU_DMA1RST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 1U), /*!< DMA1 clock reset */
329 …RCU_DMAMUXRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 3U), /*!< DMAMUX clock reset */
330 RCU_CRCRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 6U), /*!< CRC clock reset */
331 … RCU_MFCOMRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 14U), /*!< MFCOM clock reset */
332 … RCU_GPIOARST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 17U), /*!< GPIOA clock reset */
333 … RCU_GPIOBRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 18U), /*!< GPIOB clock reset */
334 … RCU_GPIOCRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 19U), /*!< GPIOC clock reset */
335 … RCU_GPIODRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 20U), /*!< GPIOD clock reset */
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32l23x/standard_peripheral/include/ |
| D | gd32l23x_rcu.h | 270 #define AHBRST_REG_OFFSET 0x28U /*!< AHB reset register offset */ macro
350 RCU_CRCRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 6U), /*!< CRC reset */
351 RCU_GPIOARST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 17U), /*!< GPIOA reset */
352 RCU_GPIOBRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 18U), /*!< GPIOB reset */
353 RCU_GPIOCRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 19U), /*!< GPIOC reset */
354 RCU_GPIODRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 19U), /*!< GPIOD reset */
355 RCU_GPIOFRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 22U), /*!< GPIOF reset */
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/include/ |
| D | gd32e50x_rcu.h | 508 #define AHBRST_REG_OFFSET 0x28U /*!< AHB reset register offset */ macro
634 … RCU_USBHSRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 12U), /*!< USBHS clock reset */
635 RCU_TMURST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 30U), /*!< TMU clock reset */
638 RCU_ENETRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 14U), /*!< ENET clock reset */
640 RCU_SQPIRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 31U), /*!< SQPI clock reset */
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32vf103/standard_peripheral/include/ |
| D | gd32vf103_rcu.h | 245 #define AHBRST_REG_OFFSET 0x28U /*!< AHB reset register offset */ macro
315 RCU_USBFSRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 12U), /*!< USBFS clock reset */
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/standard_peripheral/include/ |
| D | gd32e10x_rcu.h | 282 #define AHBRST_REG_OFFSET 0x28U /*!< AHB reset register offset */ macro
371 … RCU_USBFSRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 12U), /*!< USBFS clock reset */
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| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/standard_peripheral/include/ |
| D | gd32f403_rcu.h | 289 #define AHBRST_REG_OFFSET 0x28U /*!< AHB reset register offset */ macro
377 … RCU_USBFSRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 12U), /*!< USBFS clock reset */
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