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Searched refs:ADC_RSQ0 (Results 1 – 16 of 16) sorted by relevance

/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f3x0/standard_peripheral/source/
Dgd32f3x0_adc.c275 ADC_RSQ0 &= ~((uint32_t)ADC_RSQ0_RL); in adc_channel_length_config()
276 ADC_RSQ0 |= RSQ0_RL((uint32_t)(length-1U)); in adc_channel_length_config()
323 rsq = ADC_RSQ0; in adc_regular_channel_config()
326 ADC_RSQ0 = rsq; in adc_regular_channel_config()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32l23x/standard_peripheral/source/
Dgd32l23x_adc.c311 ADC_RSQ0 &= ~((uint32_t)ADC_RSQ0_RL); in adc_channel_length_config()
312 ADC_RSQ0 |= RSQ0_RL((uint32_t)(length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); in adc_channel_length_config()
367 rsq = ADC_RSQ0; in adc_regular_channel_config()
371 ADC_RSQ0 = rsq; in adc_regular_channel_config()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/standard_peripheral/source/
Dgd32f403_adc.c313 ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL); in adc_channel_length_config()
314 ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length-1U)); in adc_channel_length_config()
364 rsq = ADC_RSQ0(adc_periph); in adc_regular_channel_config()
367 ADC_RSQ0(adc_periph) = rsq; in adc_regular_channel_config()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32a50x/standard_peripheral/source/
Dgd32a50x_adc.c306 ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL); in adc_channel_length_config()
307 ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length-1U)); in adc_channel_length_config()
355 rsq = ADC_RSQ0(adc_periph); in adc_regular_channel_config()
358 ADC_RSQ0(adc_periph) = rsq; in adc_regular_channel_config()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/standard_peripheral/source/
Dgd32e10x_adc.c404 ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL); in adc_channel_length_config()
405 ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length-ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); in adc_channel_length_config()
458 rsq = ADC_RSQ0(adc_periph); in adc_regular_channel_config()
462 ADC_RSQ0(adc_periph) = rsq; in adc_regular_channel_config()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32vf103/standard_peripheral/source/
Dgd32vf103_adc.c319 ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL); in adc_channel_length_config()
320 ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length-ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); in adc_channel_length_config()
373 rsq = ADC_RSQ0(adc_periph); in adc_regular_channel_config()
377 ADC_RSQ0(adc_periph) = rsq; in adc_regular_channel_config()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/source/
Dgd32e50x_adc.c311 ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL); in adc_channel_length_config()
312 ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length-1U)); in adc_channel_length_config()
360 rsq = ADC_RSQ0(adc_periph); in adc_regular_channel_config()
363 ADC_RSQ0(adc_periph) = rsq; in adc_regular_channel_config()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f4xx/standard_peripheral/source/
Dgd32f4xx_adc.c425 ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL); in adc_channel_length_config()
426 ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); in adc_channel_length_config()
481 rsq = ADC_RSQ0(adc_periph); in adc_regular_channel_config()
485 ADC_RSQ0(adc_periph) = rsq; in adc_regular_channel_config()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f3x0/standard_peripheral/include/
Dgd32f3x0_adc.h57 #define ADC_RSQ0 REG32(ADC + 0x0000002CU) /*!< ADC regular seque… macro
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32l23x/standard_peripheral/include/
Dgd32l23x_adc.h55 #define ADC_RSQ0 REG32(ADC + 0x0000002CU) /*!< ADC regula… macro
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/standard_peripheral/include/
Dgd32e10x_adc.h59 #define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC regular sequence … macro
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/standard_peripheral/include/
Dgd32f403_adc.h59 #define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC regular sequence … macro
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32vf103/standard_peripheral/include/
Dgd32vf103_adc.h57 #define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC regular sequence … macro
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32a50x/standard_peripheral/include/
Dgd32a50x_adc.h56 #define ADC_RSQ0(adcx) REG32((adcx) + 0x0000002CU) /*!< ADC regular sequence … macro
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f4xx/standard_peripheral/include/
Dgd32f4xx_adc.h60 #define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC regular sequence… macro
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/include/
Dgd32e50x_adc.h61 #define ADC_RSQ0(adcx) REG32((adcx) + 0x0000002CU) /*!< ADC regular sequence … macro