1 /* 2 * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #ifdef __cplusplus 9 extern "C" { 10 #endif 11 12 /* 13 ************************* ESP32S3 Root Clock Source **************************** 14 * 1) Internal 17.5MHz RC Oscillator: RC_FAST (usually referred as FOSC or CK8M/CLK8M in TRM and reg. description) 15 * 16 * This RC oscillator generates a ~17.5MHz clock signal output as the RC_FAST_CLK. 17 * The ~17.5MHz signal output is also passed into a configurable divider, which by default divides the input clock 18 * frequency by 256, to generate a RC_FAST_D256_CLK (usually referred as 8md256 or simply d256 in reg. description). 19 * 20 * The exact frequency of RC_FAST_CLK can be computed in runtime through calibration on the RC_FAST_D256_CLK. 21 * 22 * 2) External 40MHz Crystal Clock: XTAL 23 * 24 * 3) Internal 136kHz RC Oscillator: RC_SLOW (usually referrred as RTC in TRM or reg. description) 25 * 26 * This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock 27 * can be computed in runtime through calibration. 28 * 29 * 4) External 32kHz Crystal Clock (optional): XTAL32K 30 * 31 * The clock source for this XTAL32K_CLK can be either a 32kHz crystal connecting to the XTAL_32K_P and XTAL_32K_N 32 * pins or a 32kHz clock signal generated by an external circuit. The external signal must be connected to the 33 * XTAL_32K_P pin. 34 * 35 * XTAL32K_CLK can also be calibrated to get its exact frequency. 36 */ 37 38 /* With the default value of CK8M_DFREQ = 100, RC_FAST clock frequency is 17.5 MHz +/- 7% */ 39 #define SOC_CLK_RC_FAST_FREQ_APPROX 17500000 /*!< Approximate RC_FAST_CLK frequency in Hz */ 40 #define SOC_CLK_RC_SLOW_FREQ_APPROX 136000 /*!< Approximate RC_SLOW_CLK frequency in Hz */ 41 #define SOC_CLK_RC_FAST_D256_FREQ_APPROX (SOC_CLK_RC_FAST_FREQ_APPROX / 256) /*!< Approximate RC_FAST_D256_CLK frequency in Hz */ 42 #define SOC_CLK_XTAL32K_FREQ_APPROX 32768 /*!< Approximate XTAL32K_CLK frequency in Hz */ 43 44 // Naming convention: SOC_ROOT_CLK_{loc}_{type}_[attr] 45 // {loc}: EXT, INT 46 // {type}: XTAL, RC 47 // [attr] - optional: [frequency], FAST, SLOW 48 /** 49 * @brief Root clock 50 */ 51 typedef enum { 52 SOC_ROOT_CLK_INT_RC_FAST, /*!< Internal 17.5MHz RC oscillator */ 53 SOC_ROOT_CLK_INT_RC_SLOW, /*!< Internal 136kHz RC oscillator */ 54 SOC_ROOT_CLK_EXT_XTAL, /*!< External 40MHz crystal */ 55 SOC_ROOT_CLK_EXT_XTAL32K, /*!< External 32kHz crystal/clock signal */ 56 } soc_root_clk_t; 57 58 /** 59 * @brief CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK 60 * @note Enum values are matched with the register field values on purpose 61 */ 62 typedef enum { 63 SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */ 64 SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, can be 480MHz or 320MHz) */ 65 SOC_CPU_CLK_SRC_RC_FAST = 2, /*!< Select RC_FAST_CLK as CPU_CLK source */ 66 SOC_CPU_CLK_SRC_INVALID, /*!< Invalid CPU_CLK source */ 67 } soc_cpu_clk_src_t; 68 69 /** 70 * @brief RTC_SLOW_CLK mux inputs, which are the supported clock sources for the RTC_SLOW_CLK 71 * @note Enum values are matched with the register field values on purpose 72 */ 73 typedef enum { 74 SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */ 75 SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */ 76 SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 = 2, /*!< Select RC_FAST_D256_CLK (referred as FOSC_DIV or 8m_d256/8md256 in TRM and reg. description) as RTC_SLOW_CLK source */ 77 SOC_RTC_SLOW_CLK_SRC_INVALID, /*!< Invalid RTC_SLOW_CLK source */ 78 } soc_rtc_slow_clk_src_t; 79 80 /** 81 * @brief RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK 82 * @note Enum values are matched with the register field values on purpose 83 */ 84 typedef enum { 85 SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 0, /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */ 86 SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */ 87 SOC_RTC_FAST_CLK_SRC_RC_FAST = 1, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */ 88 SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */ 89 } soc_rtc_fast_clk_src_t; 90 91 /** 92 * @brief Possible main XTAL frequency options on the target 93 * @note Enum values equal to the frequency value in MHz 94 * @note Not all frequency values listed here are supported in IDF. Please check SOC_XTAL_SUPPORT_XXX in soc_caps.h for 95 * the supported ones. 96 */ 97 typedef enum { 98 SOC_XTAL_FREQ_32M = 32, /*!< 32MHz XTAL */ 99 SOC_XTAL_FREQ_40M = 40, /*!< 40MHz XTAL */ 100 } soc_xtal_freq_t; 101 102 // Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr] 103 // {[upstream]clock_name}: APB, (BB)PLL, etc. 104 // [attr] - optional: FAST, SLOW, D<divider>, F<freq> 105 /** 106 * @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.) 107 * 108 * @note enum starts from 1, to save 0 for special purpose 109 */ 110 typedef enum { 111 // For CPU domain 112 SOC_MOD_CLK_CPU = 1, /*!< CPU_CLK can be sourced from XTAL, PLL, or RC_FAST by configuring soc_cpu_clk_src_t */ 113 // For RTC domain 114 SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */ 115 SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, or RC_FAST_D256 by configuring soc_rtc_slow_clk_src_t */ 116 // For digital domain: peripherals, WIFI, BLE 117 SOC_MOD_CLK_APB, /*!< APB_CLK is highly dependent on the CPU_CLK source */ 118 SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from PLL, and has a fixed frequency of 80MHz */ 119 SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from PLL, and has a fixed frequency of 160MHz */ 120 SOC_MOD_CLK_PLL_D2, /*!< PLL_D2_CLK is derived from PLL, it has a fixed divider of 2 */ 121 SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */ 122 SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */ 123 SOC_MOD_CLK_RC_FAST_D256, /*!< RC_FAST_D256_CLK comes from the internal 20MHz rc oscillator, divided by 256, and passing a clock gating to the peripherals */ 124 SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 40MHz crystal */ 125 SOC_MOD_CLK_TEMP_SENSOR, /*!< TEMP_SENSOR_CLK comes directly from the internal 20MHz rc oscillator */ 126 SOC_MOD_CLK_INVALID, /*!< Indication of the end of the available module clock sources */ 127 } soc_module_clk_t; 128 129 //////////////////////////////////////////////////SYSTIMER/////////////////////////////////////////////////////////////// 130 131 /** 132 * @brief Type of SYSTIMER clock source 133 */ 134 typedef enum { 135 SYSTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock is XTAL */ 136 SYSTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock default choice is XTAL */ 137 } soc_periph_systimer_clk_src_t; 138 139 //////////////////////////////////////////////////GPTimer/////////////////////////////////////////////////////////////// 140 141 /** 142 * @brief Array initializer for all supported clock sources of GPTimer 143 * 144 * The following code can be used to iterate all possible clocks: 145 * @code{c} 146 * soc_periph_gptimer_clk_src_t gptimer_clks[] = (soc_periph_gptimer_clk_src_t)SOC_GPTIMER_CLKS; 147 * for (size_t i = 0; i< sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) { 148 * soc_periph_gptimer_clk_src_t clk = gptimer_clks[i]; 149 * // Test GPTimer with the clock `clk` 150 * } 151 * @endcode 152 */ 153 #define SOC_GPTIMER_CLKS {SOC_MOD_CLK_APB, SOC_MOD_CLK_XTAL} 154 155 /** 156 * @brief Type of GPTimer clock source 157 */ 158 typedef enum { 159 GPTIMER_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */ 160 GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ 161 GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default choice */ 162 } soc_periph_gptimer_clk_src_t; 163 164 /** 165 * @brief Type of Timer Group clock source, reserved for the legacy timer group driver 166 */ 167 typedef enum { 168 TIMER_SRC_CLK_APB = SOC_MOD_CLK_APB, /*!< Timer group source clock is APB */ 169 TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group source clock is XTAL */ 170 TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_APB, /*!< Timer group source clock default choice is APB */ 171 } soc_periph_tg_clk_src_legacy_t; 172 173 //////////////////////////////////////////////////LCD/////////////////////////////////////////////////////////////////// 174 175 /** 176 * @brief Array initializer for all supported clock sources of LCD 177 */ 178 #define SOC_LCD_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_PLL_D2, SOC_MOD_CLK_XTAL} 179 180 /** 181 * @brief Type of LCD clock source 182 */ 183 typedef enum { 184 LCD_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */ 185 LCD_CLK_SRC_PLL240M = SOC_MOD_CLK_PLL_D2, /*!< Select PLL_D2 as the source clock */ 186 LCD_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ 187 LCD_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default choice */ 188 } soc_periph_lcd_clk_src_t; 189 190 //////////////////////////////////////////////////RMT/////////////////////////////////////////////////////////////////// 191 192 /** 193 * @brief Array initializer for all supported clock sources of RMT 194 */ 195 #define SOC_RMT_CLKS {SOC_MOD_CLK_APB, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL} 196 197 /** 198 * @brief Type of RMT clock source 199 */ 200 typedef enum { 201 RMT_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */ 202 RMT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ 203 RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ 204 RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default choice */ 205 } soc_periph_rmt_clk_src_t; 206 207 /** 208 * @brief Type of RMT clock source, reserved for the legacy RMT driver 209 */ 210 typedef enum { 211 RMT_BASECLK_APB = SOC_MOD_CLK_APB, /*!< RMT source clock is APB */ 212 RMT_BASECLK_XTAL = SOC_MOD_CLK_XTAL, /*!< RMT source clock is XTAL */ 213 RMT_BASECLK_DEFAULT = SOC_MOD_CLK_APB, /*!< RMT source clock default choice is APB */ 214 } soc_periph_rmt_clk_src_legacy_t; 215 216 //////////////////////////////////////////////////Temp Sensor/////////////////////////////////////////////////////////// 217 218 /** 219 * @brief Array initializer for all supported clock sources of Temperature Sensor 220 */ 221 #define SOC_TEMP_SENSOR_CLKS {SOC_MOD_CLK_TEMP_SENSOR} 222 223 /** 224 * @brief Type of Temp Sensor clock source 225 */ 226 typedef enum { 227 TEMPERATURE_SENSOR_CLK_SRC_RC_FAST = SOC_MOD_CLK_TEMP_SENSOR, /*!< Select RC_FAST as the source clock */ 228 TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_TEMP_SENSOR, /*!< Select RC_FAST as the default choice */ 229 } soc_periph_temperature_sensor_clk_src_t; 230 231 ///////////////////////////////////////////////////UART///////////////////////////////////////////////////////////////// 232 233 /** 234 * @brief Array initializer for all supported clock sources of UART 235 */ 236 #define SOC_UART_CLKS {SOC_MOD_CLK_APB, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} 237 238 /** 239 * @brief Type of UART clock source, reserved for the legacy UART driver 240 */ 241 typedef enum { 242 UART_SCLK_APB = SOC_MOD_CLK_APB, /*!< UART source clock is APB CLK */ 243 UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */ 244 UART_SCLK_XTAL = SOC_MOD_CLK_XTAL, /*!< UART source clock is XTAL */ 245 UART_SCLK_DEFAULT = SOC_MOD_CLK_APB, /*!< UART source clock default choice is APB */ 246 } soc_periph_uart_clk_src_legacy_t; 247 248 //////////////////////////////////////////////////MCPWM///////////////////////////////////////////////////////////////// 249 250 /** 251 * @brief Array initializer for all supported clock sources of MCPWM Timer 252 */ 253 #define SOC_MCPWM_TIMER_CLKS {SOC_MOD_CLK_PLL_F160M} 254 255 /** 256 * @brief Type of MCPWM timer clock source 257 */ 258 typedef enum { 259 MCPWM_TIMER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */ 260 MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */ 261 } soc_periph_mcpwm_timer_clk_src_t; 262 263 /** 264 * @brief Array initializer for all supported clock sources of MCPWM Capture Timer 265 */ 266 #define SOC_MCPWM_CAPTURE_CLKS {SOC_MOD_CLK_APB} 267 268 /** 269 * @brief Type of MCPWM capture clock source 270 */ 271 typedef enum { 272 MCPWM_CAPTURE_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */ 273 MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default clock choice */ 274 } soc_periph_mcpwm_capture_clk_src_t; 275 276 /** 277 * @brief Array initializer for all supported clock sources of MCPWM Carrier 278 */ 279 #define SOC_MCPWM_CARRIER_CLKS {SOC_MOD_CLK_PLL_F160M} 280 281 /** 282 * @brief Type of MCPWM carrier clock source 283 */ 284 typedef enum { 285 MCPWM_CARRIER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */ 286 MCPWM_CARRIER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */ 287 } soc_periph_mcpwm_carrier_clk_src_t; 288 289 ///////////////////////////////////////////////////// I2S ////////////////////////////////////////////////////////////// 290 291 /** 292 * @brief Array initializer for all supported clock sources of I2S 293 */ 294 #define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL, I2S_CLK_SRC_EXTERNAL} 295 296 /** 297 * @brief I2S clock source enum 298 */ 299 typedef enum { 300 I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default source clock */ 301 I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */ 302 I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ 303 I2S_CLK_SRC_EXTERNAL = -1, /*!< Select external clock as source clock */ 304 } soc_periph_i2s_clk_src_t; 305 306 /////////////////////////////////////////////////I2C//////////////////////////////////////////////////////////////////// 307 308 /** 309 * @brief Array initializer for all supported clock sources of I2C 310 */ 311 #define SOC_I2C_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} 312 313 /** 314 * @brief Type of I2C clock source. 315 */ 316 typedef enum { 317 I2C_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, 318 I2C_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, 319 I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, 320 } soc_periph_i2c_clk_src_t; 321 322 /////////////////////////////////////////////////SPI//////////////////////////////////////////////////////////////////// 323 324 /** 325 * @brief Array initializer for all supported clock sources of SPI 326 */ 327 #define SOC_SPI_CLKS {SOC_MOD_CLK_APB, SOC_MOD_CLK_XTAL} 328 329 /** 330 * @brief Type of SPI clock source. 331 */ 332 typedef enum { 333 SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as SPI source clock */ 334 SPI_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as SPI source clock */ 335 SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */ 336 } soc_periph_spi_clk_src_t; 337 338 //////////////////////////////////////////////////SDM////////////////////////////////////////////////////////////// 339 340 /** 341 * @brief Array initializer for all supported clock sources of SDM 342 */ 343 #define SOC_SDM_CLKS {SOC_MOD_CLK_APB} 344 345 /** 346 * @brief Sigma Delta Modulator clock source 347 */ 348 typedef enum { 349 SDM_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */ 350 SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default clock choice */ 351 } soc_periph_sdm_clk_src_t; 352 353 //////////////////////////////////////////////////GPIO Glitch Filter//////////////////////////////////////////////////// 354 355 /** 356 * @brief Array initializer for all supported clock sources of Glitch Filter 357 */ 358 #define SOC_GLITCH_FILTER_CLKS {SOC_MOD_CLK_APB} 359 360 /** 361 * @brief Glitch filter clock source 362 */ 363 364 typedef enum { 365 GLITCH_FILTER_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB clock as the source clock */ 366 GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB clock as the default clock choice */ 367 } soc_periph_glitch_filter_clk_src_t; 368 369 //////////////////////////////////////////////////TWAI///////////////////////////////////////////////////////////////// 370 371 /** 372 * @brief Array initializer for all supported clock sources of TWAI 373 */ 374 #define SOC_TWAI_CLKS {SOC_MOD_CLK_APB} 375 376 /** 377 * @brief TWAI clock source 378 */ 379 typedef enum { 380 TWAI_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */ 381 TWAI_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default clock choice */ 382 } soc_periph_twai_clk_src_t; 383 384 //////////////////////////////////////////////////ADC/////////////////////////////////////////////////////////////////// 385 386 /** 387 * @brief Array initializer for all supported clock sources of ADC digital controller 388 */ 389 #define SOC_ADC_DIGI_CLKS {SOC_MOD_CLK_APB, SOC_MOD_CLK_PLL_D2} 390 391 /** 392 * @brief ADC digital controller clock source 393 */ 394 typedef enum { 395 ADC_DIGI_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */ 396 ADC_DIGI_CLK_SRC_PLL_F240M = SOC_MOD_CLK_PLL_D2, /*!< Select PLL_D2 (default value PLL_F240M) as the source clock */ 397 ADC_DIGI_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default clock choice */ 398 } soc_periph_adc_digi_clk_src_t; 399 400 /** 401 * @brief Array initializer for all supported clock sources of ADC RTC controller 402 */ 403 #define SOC_ADC_RTC_CLKS {SOC_MOD_CLK_RC_FAST} 404 405 /** 406 * @brief ADC RTC controller clock source 407 */ 408 typedef enum { 409 ADC_RTC_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ 410 ADC_RTC_CLK_SRC_DEFAULT = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the default clock choice */ 411 } soc_periph_adc_rtc_clk_src_t; 412 413 //////////////////////////////////////////////////MWDT///////////////////////////////////////////////////////////////// 414 415 /** 416 * @brief Array initializer for all supported clock sources of MWDT 417 */ 418 #define SOC_MWDT_CLKS {SOC_MOD_CLK_APB} 419 420 /** 421 * @brief MWDT clock source 422 */ 423 typedef enum { 424 MWDT_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */ 425 MWDT_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default clock choice */ 426 } soc_periph_mwdt_clk_src_t; 427 428 //////////////////////////////////////////////////LEDC///////////////////////////////////////////////////////////////// 429 430 /** 431 * @brief Array initializer for all supported clock sources of LEDC 432 */ 433 #define SOC_LEDC_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_APB, SOC_MOD_CLK_RC_FAST} 434 435 /** 436 * @brief Type of LEDC clock source, reserved for the legacy LEDC driver 437 */ 438 typedef enum { 439 LEDC_AUTO_CLK = 0, /*!< LEDC source clock will be automatically selected based on the giving resolution and duty parameter when init the timer*/ 440 LEDC_USE_APB_CLK = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */ 441 LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ 442 LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ 443 444 LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */ 445 } soc_periph_ledc_clk_src_legacy_t; 446 447 //////////////////////////////////////////////////SDMMC/////////////////////////////////////////////////////////////// 448 449 /** 450 * @brief Array initializer for all supported clock sources of SDMMC 451 */ 452 #define SOC_SDMMC_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL} 453 454 /** 455 * @brief Type of SDMMC clock source 456 */ 457 typedef enum { 458 SDMMC_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_160M as the default choice */ 459 SDMMC_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_160M as the source clock */ 460 SDMMC_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ 461 } soc_periph_sdmmc_clk_src_t; 462 463 //////////////////////////////////////////////CLOCK OUTPUT/////////////////////////////////////////////////////////// 464 typedef enum { 465 CLKOUT_SIG_PLL = 1, /*!< PLL_CLK is the output of crystal oscillator frequency multiplier */ 466 CLKOUT_SIG_RC_SLOW = 4, /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */ 467 CLKOUT_SIG_XTAL = 5, /*!< Main crystal oscillator clock */ 468 CLKOUT_SIG_PLL_F80M = 13, /*!< From PLL, usually be 80MHz */ 469 CLKOUT_SIG_RC_FAST = 14, /*!< RC fast clock, about 17.5MHz */ 470 CLKOUT_SIG_INVALID = 0xFF, 471 } soc_clkout_sig_id_t; 472 473 #ifdef __cplusplus 474 } 475 #endif 476
