1 /** 2 * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #ifdef __cplusplus 10 extern "C" { 11 #endif 12 13 /** Group: User-defined control registers */ 14 /** Type of cmd register 15 * Command control register 16 */ 17 typedef union { 18 struct { 19 /** conf_bitlen : R/W; bitpos: [17:0]; default: 0; 20 * Define the APB cycles of SPI_CONF state. Can be configured in CONF state. 21 */ 22 uint32_t conf_bitlen:18; 23 uint32_t reserved_18:5; 24 /** update : WT; bitpos: [23]; default: 0; 25 * Set this bit to synchronize SPI registers from APB clock domain into SPI module 26 * clock domain, which is only used in SPI master mode. 27 */ 28 uint32_t update:1; 29 /** usr : R/W/SC; bitpos: [24]; default: 0; 30 * User define command enable. An operation will be triggered when the bit is set. 31 * The bit will be cleared once the operation done.1: enable 0: disable. Can not be 32 * changed by CONF_buf. 33 */ 34 uint32_t usr:1; 35 uint32_t reserved_25:7; 36 }; 37 uint32_t val; 38 } spi_cmd_reg_t; 39 40 /** Type of addr register 41 * Address value register 42 */ 43 typedef union { 44 struct { 45 /** usr_addr_value : R/W; bitpos: [31:0]; default: 0; 46 * Address to slave. Can be configured in CONF state. 47 */ 48 uint32_t usr_addr_value:32; 49 }; 50 uint32_t val; 51 } spi_addr_reg_t; 52 53 /** Type of user register 54 * SPI USER control register 55 */ 56 typedef union { 57 struct { 58 /** doutdin : R/W; bitpos: [0]; default: 0; 59 * Set the bit to enable full duplex communication. 1: enable 0: disable. Can be 60 * configured in CONF state. 61 */ 62 uint32_t doutdin:1; 63 uint32_t reserved_1:2; 64 /** qpi_mode : R/W/SS/SC; bitpos: [3]; default: 0; 65 * Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. 66 * Can be configured in CONF state. 67 */ 68 uint32_t qpi_mode:1; 69 /** opi_mode : HRO; bitpos: [4]; default: 0; 70 * Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. 71 * Can be configured in CONF state. 72 */ 73 uint32_t opi_mode:1; 74 /** tsck_i_edge : R/W; bitpos: [5]; default: 0; 75 * In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = 76 * spi_ck_i. 1:tsck = !spi_ck_i. 77 */ 78 uint32_t tsck_i_edge:1; 79 /** cs_hold : R/W; bitpos: [6]; default: 1; 80 * spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be 81 * configured in CONF state. 82 */ 83 uint32_t cs_hold:1; 84 /** cs_setup : R/W; bitpos: [7]; default: 1; 85 * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be 86 * configured in CONF state. 87 */ 88 uint32_t cs_setup:1; 89 /** rsck_i_edge : R/W; bitpos: [8]; default: 0; 90 * In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = 91 * !spi_ck_i. 1:rsck = spi_ck_i. 92 */ 93 uint32_t rsck_i_edge:1; 94 /** ck_out_edge : R/W; bitpos: [9]; default: 0; 95 * the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can 96 * be configured in CONF state. 97 */ 98 uint32_t ck_out_edge:1; 99 uint32_t reserved_10:2; 100 /** fwrite_dual : R/W; bitpos: [12]; default: 0; 101 * In the write operations read-data phase apply 2 signals. Can be configured in CONF 102 * state. 103 */ 104 uint32_t fwrite_dual:1; 105 /** fwrite_quad : R/W; bitpos: [13]; default: 0; 106 * In the write operations read-data phase apply 4 signals. Can be configured in CONF 107 * state. 108 */ 109 uint32_t fwrite_quad:1; 110 /** fwrite_oct : HRO; bitpos: [14]; default: 0; 111 * In the write operations read-data phase apply 8 signals. Can be configured in CONF 112 * state. 113 */ 114 uint32_t fwrite_oct:1; 115 /** usr_conf_nxt : R/W; bitpos: [15]; default: 0; 116 * 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans 117 * will continue. 0: The seg-trans will end after the current SPI seg-trans or this is 118 * not seg-trans mode. Can be configured in CONF state. 119 */ 120 uint32_t usr_conf_nxt:1; 121 uint32_t reserved_16:1; 122 /** sio : R/W; bitpos: [17]; default: 0; 123 * Set the bit to enable 3-line half duplex communication mosi and miso signals share 124 * the same pin. 1: enable 0: disable. Can be configured in CONF state. 125 */ 126 uint32_t sio:1; 127 uint32_t reserved_18:6; 128 /** usr_miso_highpart : R/W; bitpos: [24]; default: 0; 129 * read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: 130 * disable. Can be configured in CONF state. 131 */ 132 uint32_t usr_miso_highpart:1; 133 /** usr_mosi_highpart : R/W; bitpos: [25]; default: 0; 134 * write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 135 * 0: disable. Can be configured in CONF state. 136 */ 137 uint32_t usr_mosi_highpart:1; 138 /** usr_dummy_idle : R/W; bitpos: [26]; default: 0; 139 * spi clock is disable in dummy phase when the bit is enable. Can be configured in 140 * CONF state. 141 */ 142 uint32_t usr_dummy_idle:1; 143 /** usr_mosi : R/W; bitpos: [27]; default: 0; 144 * This bit enable the write-data phase of an operation. Can be configured in CONF 145 * state. 146 */ 147 uint32_t usr_mosi:1; 148 /** usr_miso : R/W; bitpos: [28]; default: 0; 149 * This bit enable the read-data phase of an operation. Can be configured in CONF 150 * state. 151 */ 152 uint32_t usr_miso:1; 153 /** usr_dummy : R/W; bitpos: [29]; default: 0; 154 * This bit enable the dummy phase of an operation. Can be configured in CONF state. 155 */ 156 uint32_t usr_dummy:1; 157 /** usr_addr : R/W; bitpos: [30]; default: 0; 158 * This bit enable the address phase of an operation. Can be configured in CONF state. 159 */ 160 uint32_t usr_addr:1; 161 /** usr_command : R/W; bitpos: [31]; default: 1; 162 * This bit enable the command phase of an operation. Can be configured in CONF state. 163 */ 164 uint32_t usr_command:1; 165 }; 166 uint32_t val; 167 } spi_user_reg_t; 168 169 /** Type of user1 register 170 * SPI USER control register 1 171 */ 172 typedef union { 173 struct { 174 /** usr_dummy_cyclelen : R/W; bitpos: [7:0]; default: 7; 175 * The length in spi_clk cycles of dummy phase. The register value shall be 176 * (cycle_num-1). Can be configured in CONF state. 177 */ 178 uint32_t usr_dummy_cyclelen:8; 179 uint32_t reserved_8:8; 180 /** mst_wfull_err_end_en : R/W; bitpos: [16]; default: 1; 181 * 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master 182 * FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in 183 * GP-SPI master FD/HD-mode. 184 */ 185 uint32_t mst_wfull_err_end_en:1; 186 /** cs_setup_time : R/W; bitpos: [21:17]; default: 0; 187 * (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup 188 * bit. Can be configured in CONF state. 189 */ 190 uint32_t cs_setup_time:5; 191 /** cs_hold_time : R/W; bitpos: [26:22]; default: 1; 192 * delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. 193 * Can be configured in CONF state. 194 */ 195 uint32_t cs_hold_time:5; 196 /** usr_addr_bitlen : R/W; bitpos: [31:27]; default: 23; 197 * The length in bits of address phase. The register value shall be (bit_num-1). Can 198 * be configured in CONF state. 199 */ 200 uint32_t usr_addr_bitlen:5; 201 }; 202 uint32_t val; 203 } spi_user1_reg_t; 204 205 /** Type of user2 register 206 * SPI USER control register 2 207 */ 208 typedef union { 209 struct { 210 /** usr_command_value : R/W; bitpos: [15:0]; default: 0; 211 * The value of command. Can be configured in CONF state. 212 */ 213 uint32_t usr_command_value:16; 214 uint32_t reserved_16:11; 215 /** mst_rempty_err_end_en : R/W; bitpos: [27]; default: 1; 216 * 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI 217 * master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error 218 * is valid in GP-SPI master FD/HD-mode. 219 */ 220 uint32_t mst_rempty_err_end_en:1; 221 /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7; 222 * The length in bits of command phase. The register value shall be (bit_num-1). Can 223 * be configured in CONF state. 224 */ 225 uint32_t usr_command_bitlen:4; 226 }; 227 uint32_t val; 228 } spi_user2_reg_t; 229 230 231 /** Group: Control and configuration registers */ 232 /** Type of ctrl register 233 * SPI control register 234 */ 235 typedef union { 236 struct { 237 uint32_t reserved_0:3; 238 /** dummy_out : R/W; bitpos: [3]; default: 0; 239 * 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, 240 * the FSPI bus signals are output. Can be configured in CONF state. 241 */ 242 uint32_t dummy_out:1; 243 uint32_t reserved_4:1; 244 /** faddr_dual : R/W; bitpos: [5]; default: 0; 245 * Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF 246 * state. 247 */ 248 uint32_t faddr_dual:1; 249 /** faddr_quad : R/W; bitpos: [6]; default: 0; 250 * Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF 251 * state. 252 */ 253 uint32_t faddr_quad:1; 254 /** faddr_oct : HRO; bitpos: [7]; default: 0; 255 * Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF 256 * state. 257 */ 258 uint32_t faddr_oct:1; 259 /** fcmd_dual : R/W; bitpos: [8]; default: 0; 260 * Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF 261 * state. 262 */ 263 uint32_t fcmd_dual:1; 264 /** fcmd_quad : R/W; bitpos: [9]; default: 0; 265 * Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF 266 * state. 267 */ 268 uint32_t fcmd_quad:1; 269 /** fcmd_oct : HRO; bitpos: [10]; default: 0; 270 * Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF 271 * state. 272 */ 273 uint32_t fcmd_oct:1; 274 uint32_t reserved_11:3; 275 /** fread_dual : R/W; bitpos: [14]; default: 0; 276 * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can 277 * be configured in CONF state. 278 */ 279 uint32_t fread_dual:1; 280 /** fread_quad : R/W; bitpos: [15]; default: 0; 281 * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can 282 * be configured in CONF state. 283 */ 284 uint32_t fread_quad:1; 285 /** fread_oct : HRO; bitpos: [16]; default: 0; 286 * In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can 287 * be configured in CONF state. 288 */ 289 uint32_t fread_oct:1; 290 uint32_t reserved_17:1; 291 /** q_pol : R/W; bitpos: [18]; default: 1; 292 * The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in 293 * CONF state. 294 */ 295 uint32_t q_pol:1; 296 /** d_pol : R/W; bitpos: [19]; default: 1; 297 * The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in 298 * CONF state. 299 */ 300 uint32_t d_pol:1; 301 /** hold_pol : R/W; bitpos: [20]; default: 1; 302 * SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be 303 * configured in CONF state. 304 */ 305 uint32_t hold_pol:1; 306 /** wp_pol : R/W; bitpos: [21]; default: 1; 307 * Write protect signal output when SPI is idle. 1: output high, 0: output low. Can 308 * be configured in CONF state. 309 */ 310 uint32_t wp_pol:1; 311 uint32_t reserved_22:1; 312 /** rd_bit_order : R/W; bitpos: [24:23]; default: 0; 313 * In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF 314 * state. 315 */ 316 uint32_t rd_bit_order:2; 317 /** wr_bit_order : R/W; bitpos: [26:25]; default: 0; 318 * In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be 319 * configured in CONF state. 320 */ 321 uint32_t wr_bit_order:2; 322 uint32_t reserved_27:5; 323 }; 324 uint32_t val; 325 } spi_ctrl_reg_t; 326 327 /** Type of ms_dlen register 328 * SPI data bit length control register 329 */ 330 typedef union { 331 struct { 332 /** ms_data_bitlen : R/W; bitpos: [17:0]; default: 0; 333 * The value of these bits is the configured SPI transmission data bit length in 334 * master mode DMA controlled transfer or CPU controlled transfer. The value is also 335 * the configured bit length in slave mode DMA RX controlled transfer. The register 336 * value shall be (bit_num-1). Can be configured in CONF state. 337 */ 338 uint32_t ms_data_bitlen:18; 339 uint32_t reserved_18:14; 340 }; 341 uint32_t val; 342 } spi_ms_dlen_reg_t; 343 344 /** Type of misc register 345 * SPI misc register 346 */ 347 typedef union { 348 struct { 349 /** cs0_dis : R/W; bitpos: [0]; default: 0; 350 * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can 351 * be configured in CONF state. 352 */ 353 uint32_t cs0_dis:1; 354 /** cs1_dis : R/W; bitpos: [1]; default: 1; 355 * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can 356 * be configured in CONF state. 357 */ 358 uint32_t cs1_dis:1; 359 /** cs2_dis : R/W; bitpos: [2]; default: 1; 360 * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can 361 * be configured in CONF state. 362 */ 363 uint32_t cs2_dis:1; 364 /** cs3_dis : R/W; bitpos: [3]; default: 1; 365 * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can 366 * be configured in CONF state. 367 */ 368 uint32_t cs3_dis:1; 369 /** cs4_dis : R/W; bitpos: [4]; default: 1; 370 * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can 371 * be configured in CONF state. 372 */ 373 uint32_t cs4_dis:1; 374 /** cs5_dis : R/W; bitpos: [5]; default: 1; 375 * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can 376 * be configured in CONF state. 377 */ 378 uint32_t cs5_dis:1; 379 /** ck_dis : R/W; bitpos: [6]; default: 0; 380 * 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. 381 */ 382 uint32_t ck_dis:1; 383 /** master_cs_pol : R/W; bitpos: [12:7]; default: 0; 384 * In the master mode the bits are the polarity of spi cs line, the value is 385 * equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. 386 */ 387 uint32_t master_cs_pol:6; 388 uint32_t reserved_13:3; 389 /** clk_data_dtr_en : HRO; bitpos: [16]; default: 0; 390 * 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR 391 * mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. 392 */ 393 uint32_t clk_data_dtr_en:1; 394 /** data_dtr_en : HRO; bitpos: [17]; default: 0; 395 * 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 396 * 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. 397 * Can be configured in CONF state. 398 */ 399 uint32_t data_dtr_en:1; 400 /** addr_dtr_en : HRO; bitpos: [18]; default: 0; 401 * 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 402 * 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be 403 * configured in CONF state. 404 */ 405 uint32_t addr_dtr_en:1; 406 /** cmd_dtr_en : HRO; bitpos: [19]; default: 0; 407 * 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 408 * 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be 409 * configured in CONF state. 410 */ 411 uint32_t cmd_dtr_en:1; 412 uint32_t reserved_20:3; 413 /** slave_cs_pol : R/W; bitpos: [23]; default: 0; 414 * spi slave input cs polarity select. 1: inv 0: not change. Can be configured in 415 * CONF state. 416 */ 417 uint32_t slave_cs_pol:1; 418 /** dqs_idle_edge : HRO; bitpos: [24]; default: 0; 419 * The default value of spi_dqs. Can be configured in CONF state. 420 */ 421 uint32_t dqs_idle_edge:1; 422 uint32_t reserved_25:4; 423 /** ck_idle_edge : R/W; bitpos: [29]; default: 0; 424 * 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be 425 * configured in CONF state. 426 */ 427 uint32_t ck_idle_edge:1; 428 /** cs_keep_active : R/W; bitpos: [30]; default: 0; 429 * spi cs line keep low when the bit is set. Can be configured in CONF state. 430 */ 431 uint32_t cs_keep_active:1; 432 /** quad_din_pin_swap : R/W; bitpos: [31]; default: 0; 433 * 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: 434 * spi quad input swap disable. Can be configured in CONF state. 435 */ 436 uint32_t quad_din_pin_swap:1; 437 }; 438 uint32_t val; 439 } spi_misc_reg_t; 440 441 /** Type of dma_conf register 442 * SPI DMA control register 443 */ 444 typedef union { 445 struct { 446 /** dma_outfifo_empty : RO; bitpos: [0]; default: 1; 447 * Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: 448 * DMA TX FIFO is ready for sending data. 449 */ 450 uint32_t dma_outfifo_empty:1; 451 /** dma_infifo_full : RO; bitpos: [1]; default: 1; 452 * Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 453 * 0: DMA RX FIFO is ready for receiving data. 454 */ 455 uint32_t dma_infifo_full:1; 456 uint32_t reserved_2:16; 457 /** dma_slv_seg_trans_en : R/W; bitpos: [18]; default: 0; 458 * Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. 459 */ 460 uint32_t dma_slv_seg_trans_en:1; 461 /** slv_rx_seg_trans_clr_en : R/W; bitpos: [19]; default: 0; 462 * 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: 463 * spi_dma_infifo_full_vld is cleared by spi_trans_done. 464 */ 465 uint32_t slv_rx_seg_trans_clr_en:1; 466 /** slv_tx_seg_trans_clr_en : R/W; bitpos: [20]; default: 0; 467 * 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: 468 * spi_dma_outfifo_empty_vld is cleared by spi_trans_done. 469 */ 470 uint32_t slv_tx_seg_trans_clr_en:1; 471 /** rx_eof_en : R/W; bitpos: [21]; default: 0; 472 * 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to 473 * the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: 474 * spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or 475 * spi_dma_seg_trans_done in seg-trans. 476 */ 477 uint32_t rx_eof_en:1; 478 uint32_t reserved_22:5; 479 /** dma_rx_ena : R/W; bitpos: [27]; default: 0; 480 * Set this bit to enable SPI DMA controlled receive data mode. 481 */ 482 uint32_t dma_rx_ena:1; 483 /** dma_tx_ena : R/W; bitpos: [28]; default: 0; 484 * Set this bit to enable SPI DMA controlled send data mode. 485 */ 486 uint32_t dma_tx_ena:1; 487 /** rx_afifo_rst : WT; bitpos: [29]; default: 0; 488 * Set this bit to reset RX AFIFO, which is used to receive data in SPI master and 489 * slave mode transfer. 490 */ 491 uint32_t rx_afifo_rst:1; 492 /** buf_afifo_rst : WT; bitpos: [30]; default: 0; 493 * Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU 494 * controlled mode transfer and master mode transfer. 495 */ 496 uint32_t buf_afifo_rst:1; 497 /** dma_afifo_rst : WT; bitpos: [31]; default: 0; 498 * Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA 499 * controlled mode transfer. 500 */ 501 uint32_t dma_afifo_rst:1; 502 }; 503 uint32_t val; 504 } spi_dma_conf_reg_t; 505 506 /** Type of slave register 507 * SPI slave control register 508 */ 509 typedef union { 510 struct { 511 /** clk_mode : R/W; bitpos: [1:0]; default: 0; 512 * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed 513 * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: 514 * SPI clock is alwasy on. Can be configured in CONF state. 515 */ 516 uint32_t clk_mode:2; 517 /** clk_mode_13 : R/W; bitpos: [2]; default: 0; 518 * {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: 519 * support spi clk mode 0 and 2, first edge output data B[1]/B[6]. 520 */ 521 uint32_t clk_mode_13:1; 522 /** rsck_data_out : R/W; bitpos: [3]; default: 0; 523 * It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 524 * 0: output data at tsck posedge 525 */ 526 uint32_t rsck_data_out:1; 527 uint32_t reserved_4:4; 528 /** slv_rddma_bitlen_en : R/W; bitpos: [8]; default: 0; 529 * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in 530 * DMA controlled mode(Rd_DMA). 0: others 531 */ 532 uint32_t slv_rddma_bitlen_en:1; 533 /** slv_wrdma_bitlen_en : R/W; bitpos: [9]; default: 0; 534 * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length 535 * in DMA controlled mode(Wr_DMA). 0: others 536 */ 537 uint32_t slv_wrdma_bitlen_en:1; 538 /** slv_rdbuf_bitlen_en : R/W; bitpos: [10]; default: 0; 539 * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in 540 * CPU controlled mode(Rd_BUF). 0: others 541 */ 542 uint32_t slv_rdbuf_bitlen_en:1; 543 /** slv_wrbuf_bitlen_en : R/W; bitpos: [11]; default: 0; 544 * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length 545 * in CPU controlled mode(Wr_BUF). 0: others 546 */ 547 uint32_t slv_wrbuf_bitlen_en:1; 548 uint32_t reserved_12:10; 549 /** dma_seg_magic_value : R/W; bitpos: [25:22]; default: 10; 550 * The magic value of BM table in master DMA seg-trans. 551 */ 552 uint32_t dma_seg_magic_value:4; 553 /** slave_mode : R/W; bitpos: [26]; default: 0; 554 * Set SPI work mode. 1: slave mode 0: master mode. 555 */ 556 uint32_t slave_mode:1; 557 /** soft_reset : WT; bitpos: [27]; default: 0; 558 * Software reset enable, reset the spi clock line cs line and data lines. Can be 559 * configured in CONF state. 560 */ 561 uint32_t soft_reset:1; 562 /** usr_conf : R/W; bitpos: [28]; default: 0; 563 * 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans 564 * will start. 0: This is not seg-trans mode. 565 */ 566 uint32_t usr_conf:1; 567 /** mst_fd_wait_dma_tx_data : R/W; bitpos: [29]; default: 0; 568 * In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before 569 * starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI 570 * transfer. 571 */ 572 uint32_t mst_fd_wait_dma_tx_data:1; 573 uint32_t reserved_30:2; 574 }; 575 uint32_t val; 576 } spi_slave_reg_t; 577 578 /** Type of slave1 register 579 * SPI slave control register 1 580 */ 581 typedef union { 582 struct { 583 /** slv_data_bitlen : R/W/SS; bitpos: [17:0]; default: 0; 584 * The transferred data bit length in SPI slave FD and HD mode. 585 */ 586 uint32_t slv_data_bitlen:18; 587 /** slv_last_command : R/W/SS; bitpos: [25:18]; default: 0; 588 * In the slave mode it is the value of command. 589 */ 590 uint32_t slv_last_command:8; 591 /** slv_last_addr : R/W/SS; bitpos: [31:26]; default: 0; 592 * In the slave mode it is the value of address. 593 */ 594 uint32_t slv_last_addr:6; 595 }; 596 uint32_t val; 597 } spi_slave1_reg_t; 598 599 600 /** Group: Clock control registers */ 601 /** Type of clock register 602 * SPI clock control register 603 */ 604 typedef union { 605 struct { 606 /** clkcnt_l : R/W; bitpos: [5:0]; default: 3; 607 * In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 608 * 0. Can be configured in CONF state. 609 */ 610 uint32_t clkcnt_l:6; 611 /** clkcnt_h : R/W; bitpos: [11:6]; default: 1; 612 * In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it 613 * must be 0. Can be configured in CONF state. 614 */ 615 uint32_t clkcnt_h:6; 616 /** clkcnt_n : R/W; bitpos: [17:12]; default: 3; 617 * In the master mode it is the divider of spi_clk. So spi_clk frequency is 618 * system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. 619 */ 620 uint32_t clkcnt_n:6; 621 /** clkdiv_pre : R/W; bitpos: [21:18]; default: 0; 622 * In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. 623 */ 624 uint32_t clkdiv_pre:4; 625 uint32_t reserved_22:9; 626 /** clk_equ_sysclk : R/W; bitpos: [31]; default: 1; 627 * In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system 628 * clock. Can be configured in CONF state. 629 */ 630 uint32_t clk_equ_sysclk:1; 631 }; 632 uint32_t val; 633 } spi_clock_reg_t; 634 635 /** Type of clk_gate register 636 * SPI module clock and register clock control 637 */ 638 typedef union { 639 struct { 640 /** clk_en : R/W; bitpos: [0]; default: 0; 641 * Set this bit to enable clk gate 642 */ 643 uint32_t clk_en:1; 644 /** mst_clk_active : R/W; bitpos: [1]; default: 0; 645 * Set this bit to power on the SPI module clock. 646 */ 647 uint32_t mst_clk_active:1; 648 /** mst_clk_sel : R/W; bitpos: [2]; default: 0; 649 * This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 650 * 0: XTAL CLK. 651 */ 652 uint32_t mst_clk_sel:1; 653 uint32_t reserved_3:29; 654 }; 655 uint32_t val; 656 } spi_clk_gate_reg_t; 657 658 659 /** Group: Timing registers */ 660 /** Type of din_mode register 661 * SPI input delay mode configuration 662 */ 663 typedef union { 664 struct { 665 /** din0_mode : R/W; bitpos: [1:0]; default: 0; 666 * the input signals are delayed by SPI module clock cycles, 0: input without delayed, 667 * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input 668 * with the spi_clk. Can be configured in CONF state. 669 */ 670 uint32_t din0_mode:2; 671 /** din1_mode : R/W; bitpos: [3:2]; default: 0; 672 * the input signals are delayed by SPI module clock cycles, 0: input without delayed, 673 * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input 674 * with the spi_clk. Can be configured in CONF state. 675 */ 676 uint32_t din1_mode:2; 677 /** din2_mode : R/W; bitpos: [5:4]; default: 0; 678 * the input signals are delayed by SPI module clock cycles, 0: input without delayed, 679 * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input 680 * with the spi_clk. Can be configured in CONF state. 681 */ 682 uint32_t din2_mode:2; 683 /** din3_mode : R/W; bitpos: [7:6]; default: 0; 684 * the input signals are delayed by SPI module clock cycles, 0: input without delayed, 685 * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input 686 * with the spi_clk. Can be configured in CONF state. 687 */ 688 uint32_t din3_mode:2; 689 /** din4_mode : HRO; bitpos: [9:8]; default: 0; 690 * the input signals are delayed by SPI module clock cycles, 0: input without delayed, 691 * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input 692 * with the spi_clk. Can be configured in CONF state. 693 */ 694 uint32_t din4_mode:2; 695 /** din5_mode : HRO; bitpos: [11:10]; default: 0; 696 * the input signals are delayed by SPI module clock cycles, 0: input without delayed, 697 * 1: input at the (SPI_DIN5_NUM+1)th falling edge of clk_spi_mst,2 input at the 698 * (SPI_DIN5_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle, 699 * 3: input at the (SPI_DIN5_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst 700 * falling edge cycle. Can be configured in CONF state. 701 */ 702 uint32_t din5_mode:2; 703 /** din6_mode : HRO; bitpos: [13:12]; default: 0; 704 * the input signals are delayed by SPI module clock cycles, 0: input without delayed, 705 * 1: input at the (SPI_DIN6_NUM+1)th falling edge of clk_spi_mst,2 input at the 706 * (SPI_DIN6_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle, 707 * 3: input at the (SPI_DIN6_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst 708 * falling edge cycle. Can be configured in CONF state. 709 */ 710 uint32_t din6_mode:2; 711 /** din7_mode : HRO; bitpos: [15:14]; default: 0; 712 * the input signals are delayed by SPI module clock cycles, 0: input without delayed, 713 * 1: input at the (SPI_DIN7_NUM+1)th falling edge of clk_spi_mst,2 input at the 714 * (SPI_DIN7_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle, 715 * 3: input at the (SPI_DIN7_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst 716 * falling edge cycle. Can be configured in CONF state. 717 */ 718 uint32_t din7_mode:2; 719 /** timing_hclk_active : R/W; bitpos: [16]; default: 0; 720 * 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF 721 * state. 722 */ 723 uint32_t timing_hclk_active:1; 724 uint32_t reserved_17:15; 725 }; 726 uint32_t val; 727 } spi_din_mode_reg_t; 728 729 /** Type of din_num register 730 * SPI input delay number configuration 731 */ 732 typedef union { 733 struct { 734 /** din0_num : R/W; bitpos: [1:0]; default: 0; 735 * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: 736 * delayed by 2 cycles,... Can be configured in CONF state. 737 */ 738 uint32_t din0_num:2; 739 /** din1_num : R/W; bitpos: [3:2]; default: 0; 740 * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: 741 * delayed by 2 cycles,... Can be configured in CONF state. 742 */ 743 uint32_t din1_num:2; 744 /** din2_num : R/W; bitpos: [5:4]; default: 0; 745 * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: 746 * delayed by 2 cycles,... Can be configured in CONF state. 747 */ 748 uint32_t din2_num:2; 749 /** din3_num : R/W; bitpos: [7:6]; default: 0; 750 * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: 751 * delayed by 2 cycles,... Can be configured in CONF state. 752 */ 753 uint32_t din3_num:2; 754 /** din4_num : HRO; bitpos: [9:8]; default: 0; 755 * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: 756 * delayed by 2 cycles,... Can be configured in CONF state. 757 */ 758 uint32_t din4_num:2; 759 /** din5_num : HRO; bitpos: [11:10]; default: 0; 760 * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: 761 * delayed by 2 cycles,... Can be configured in CONF state. 762 */ 763 uint32_t din5_num:2; 764 /** din6_num : HRO; bitpos: [13:12]; default: 0; 765 * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: 766 * delayed by 2 cycles,... Can be configured in CONF state. 767 */ 768 uint32_t din6_num:2; 769 /** din7_num : HRO; bitpos: [15:14]; default: 0; 770 * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: 771 * delayed by 2 cycles,... Can be configured in CONF state. 772 */ 773 uint32_t din7_num:2; 774 uint32_t reserved_16:16; 775 }; 776 uint32_t val; 777 } spi_din_num_reg_t; 778 779 /** Type of dout_mode register 780 * SPI output delay mode configuration 781 */ 782 typedef union { 783 struct { 784 /** dout0_mode : R/W; bitpos: [0]; default: 0; 785 * The output signal $n is delayed by the SPI module clock, 0: output without delayed, 786 * 1: output delay for a SPI module clock cycle at its negative edge. Can be 787 * configured in CONF state. 788 */ 789 uint32_t dout0_mode:1; 790 /** dout1_mode : R/W; bitpos: [1]; default: 0; 791 * The output signal $n is delayed by the SPI module clock, 0: output without delayed, 792 * 1: output delay for a SPI module clock cycle at its negative edge. Can be 793 * configured in CONF state. 794 */ 795 uint32_t dout1_mode:1; 796 /** dout2_mode : R/W; bitpos: [2]; default: 0; 797 * The output signal $n is delayed by the SPI module clock, 0: output without delayed, 798 * 1: output delay for a SPI module clock cycle at its negative edge. Can be 799 * configured in CONF state. 800 */ 801 uint32_t dout2_mode:1; 802 /** dout3_mode : R/W; bitpos: [3]; default: 0; 803 * The output signal $n is delayed by the SPI module clock, 0: output without delayed, 804 * 1: output delay for a SPI module clock cycle at its negative edge. Can be 805 * configured in CONF state. 806 */ 807 uint32_t dout3_mode:1; 808 /** dout4_mode : HRO; bitpos: [4]; default: 0; 809 * The output signal $n is delayed by the SPI module clock, 0: output without delayed, 810 * 1: output delay for a SPI module clock cycle at its negative edge. Can be 811 * configured in CONF state. 812 */ 813 uint32_t dout4_mode:1; 814 /** dout5_mode : HRO; bitpos: [5]; default: 0; 815 * The output signal $n is delayed by the SPI module clock, 0: output without delayed, 816 * 1: output delay for a SPI module clock cycle at its negative edge. Can be 817 * configured in CONF state. 818 */ 819 uint32_t dout5_mode:1; 820 /** dout6_mode : HRO; bitpos: [6]; default: 0; 821 * The output signal $n is delayed by the SPI module clock, 0: output without delayed, 822 * 1: output delay for a SPI module clock cycle at its negative edge. Can be 823 * configured in CONF state. 824 */ 825 uint32_t dout6_mode:1; 826 /** dout7_mode : HRO; bitpos: [7]; default: 0; 827 * The output signal $n is delayed by the SPI module clock, 0: output without delayed, 828 * 1: output delay for a SPI module clock cycle at its negative edge. Can be 829 * configured in CONF state. 830 */ 831 uint32_t dout7_mode:1; 832 /** d_dqs_mode : HRO; bitpos: [8]; default: 0; 833 * The output signal SPI_DQS is delayed by the SPI module clock, 0: output without 834 * delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be 835 * configured in CONF state. 836 */ 837 uint32_t d_dqs_mode:1; 838 uint32_t reserved_9:23; 839 }; 840 uint32_t val; 841 } spi_dout_mode_reg_t; 842 843 844 /** Group: Interrupt registers */ 845 /** Type of dma_int_ena register 846 * SPI interrupt enable register 847 */ 848 typedef union { 849 struct { 850 /** dma_infifo_full_err_int_ena : R/W; bitpos: [0]; default: 0; 851 * The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. 852 */ 853 uint32_t dma_infifo_full_err_int_ena:1; 854 /** dma_outfifo_empty_err_int_ena : R/W; bitpos: [1]; default: 0; 855 * The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. 856 */ 857 uint32_t dma_outfifo_empty_err_int_ena:1; 858 /** slv_ex_qpi_int_ena : R/W; bitpos: [2]; default: 0; 859 * The enable bit for SPI slave Ex_QPI interrupt. 860 */ 861 uint32_t slv_ex_qpi_int_ena:1; 862 /** slv_en_qpi_int_ena : R/W; bitpos: [3]; default: 0; 863 * The enable bit for SPI slave En_QPI interrupt. 864 */ 865 uint32_t slv_en_qpi_int_ena:1; 866 /** slv_cmd7_int_ena : R/W; bitpos: [4]; default: 0; 867 * The enable bit for SPI slave CMD7 interrupt. 868 */ 869 uint32_t slv_cmd7_int_ena:1; 870 /** slv_cmd8_int_ena : R/W; bitpos: [5]; default: 0; 871 * The enable bit for SPI slave CMD8 interrupt. 872 */ 873 uint32_t slv_cmd8_int_ena:1; 874 /** slv_cmd9_int_ena : R/W; bitpos: [6]; default: 0; 875 * The enable bit for SPI slave CMD9 interrupt. 876 */ 877 uint32_t slv_cmd9_int_ena:1; 878 /** slv_cmda_int_ena : R/W; bitpos: [7]; default: 0; 879 * The enable bit for SPI slave CMDA interrupt. 880 */ 881 uint32_t slv_cmda_int_ena:1; 882 /** slv_rd_dma_done_int_ena : R/W; bitpos: [8]; default: 0; 883 * The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 884 */ 885 uint32_t slv_rd_dma_done_int_ena:1; 886 /** slv_wr_dma_done_int_ena : R/W; bitpos: [9]; default: 0; 887 * The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 888 */ 889 uint32_t slv_wr_dma_done_int_ena:1; 890 /** slv_rd_buf_done_int_ena : R/W; bitpos: [10]; default: 0; 891 * The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 892 */ 893 uint32_t slv_rd_buf_done_int_ena:1; 894 /** slv_wr_buf_done_int_ena : R/W; bitpos: [11]; default: 0; 895 * The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 896 */ 897 uint32_t slv_wr_buf_done_int_ena:1; 898 /** trans_done_int_ena : R/W; bitpos: [12]; default: 0; 899 * The enable bit for SPI_TRANS_DONE_INT interrupt. 900 */ 901 uint32_t trans_done_int_ena:1; 902 /** dma_seg_trans_done_int_ena : R/W; bitpos: [13]; default: 0; 903 * The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 904 */ 905 uint32_t dma_seg_trans_done_int_ena:1; 906 /** seg_magic_err_int_ena : R/W; bitpos: [14]; default: 0; 907 * The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. 908 */ 909 uint32_t seg_magic_err_int_ena:1; 910 /** slv_buf_addr_err_int_ena : R/W; bitpos: [15]; default: 0; 911 * The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 912 */ 913 uint32_t slv_buf_addr_err_int_ena:1; 914 /** slv_cmd_err_int_ena : R/W; bitpos: [16]; default: 0; 915 * The enable bit for SPI_SLV_CMD_ERR_INT interrupt. 916 */ 917 uint32_t slv_cmd_err_int_ena:1; 918 /** mst_rx_afifo_wfull_err_int_ena : R/W; bitpos: [17]; default: 0; 919 * The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 920 */ 921 uint32_t mst_rx_afifo_wfull_err_int_ena:1; 922 /** mst_tx_afifo_rempty_err_int_ena : R/W; bitpos: [18]; default: 0; 923 * The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 924 */ 925 uint32_t mst_tx_afifo_rempty_err_int_ena:1; 926 /** app2_int_ena : R/W; bitpos: [19]; default: 0; 927 * The enable bit for SPI_APP2_INT interrupt. 928 */ 929 uint32_t app2_int_ena:1; 930 /** app1_int_ena : R/W; bitpos: [20]; default: 0; 931 * The enable bit for SPI_APP1_INT interrupt. 932 */ 933 uint32_t app1_int_ena:1; 934 uint32_t reserved_21:11; 935 }; 936 uint32_t val; 937 } spi_dma_int_ena_reg_t; 938 939 /** Type of dma_int_clr register 940 * SPI interrupt clear register 941 */ 942 typedef union { 943 struct { 944 /** dma_infifo_full_err_int_clr : WT; bitpos: [0]; default: 0; 945 * The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. 946 */ 947 uint32_t dma_infifo_full_err_int_clr:1; 948 /** dma_outfifo_empty_err_int_clr : WT; bitpos: [1]; default: 0; 949 * The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. 950 */ 951 uint32_t dma_outfifo_empty_err_int_clr:1; 952 /** slv_ex_qpi_int_clr : WT; bitpos: [2]; default: 0; 953 * The clear bit for SPI slave Ex_QPI interrupt. 954 */ 955 uint32_t slv_ex_qpi_int_clr:1; 956 /** slv_en_qpi_int_clr : WT; bitpos: [3]; default: 0; 957 * The clear bit for SPI slave En_QPI interrupt. 958 */ 959 uint32_t slv_en_qpi_int_clr:1; 960 /** slv_cmd7_int_clr : WT; bitpos: [4]; default: 0; 961 * The clear bit for SPI slave CMD7 interrupt. 962 */ 963 uint32_t slv_cmd7_int_clr:1; 964 /** slv_cmd8_int_clr : WT; bitpos: [5]; default: 0; 965 * The clear bit for SPI slave CMD8 interrupt. 966 */ 967 uint32_t slv_cmd8_int_clr:1; 968 /** slv_cmd9_int_clr : WT; bitpos: [6]; default: 0; 969 * The clear bit for SPI slave CMD9 interrupt. 970 */ 971 uint32_t slv_cmd9_int_clr:1; 972 /** slv_cmda_int_clr : WT; bitpos: [7]; default: 0; 973 * The clear bit for SPI slave CMDA interrupt. 974 */ 975 uint32_t slv_cmda_int_clr:1; 976 /** slv_rd_dma_done_int_clr : WT; bitpos: [8]; default: 0; 977 * The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 978 */ 979 uint32_t slv_rd_dma_done_int_clr:1; 980 /** slv_wr_dma_done_int_clr : WT; bitpos: [9]; default: 0; 981 * The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 982 */ 983 uint32_t slv_wr_dma_done_int_clr:1; 984 /** slv_rd_buf_done_int_clr : WT; bitpos: [10]; default: 0; 985 * The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 986 */ 987 uint32_t slv_rd_buf_done_int_clr:1; 988 /** slv_wr_buf_done_int_clr : WT; bitpos: [11]; default: 0; 989 * The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 990 */ 991 uint32_t slv_wr_buf_done_int_clr:1; 992 /** trans_done_int_clr : WT; bitpos: [12]; default: 0; 993 * The clear bit for SPI_TRANS_DONE_INT interrupt. 994 */ 995 uint32_t trans_done_int_clr:1; 996 /** dma_seg_trans_done_int_clr : WT; bitpos: [13]; default: 0; 997 * The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 998 */ 999 uint32_t dma_seg_trans_done_int_clr:1; 1000 /** seg_magic_err_int_clr : WT; bitpos: [14]; default: 0; 1001 * The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1002 */ 1003 uint32_t seg_magic_err_int_clr:1; 1004 /** slv_buf_addr_err_int_clr : WT; bitpos: [15]; default: 0; 1005 * The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1006 */ 1007 uint32_t slv_buf_addr_err_int_clr:1; 1008 /** slv_cmd_err_int_clr : WT; bitpos: [16]; default: 0; 1009 * The clear bit for SPI_SLV_CMD_ERR_INT interrupt. 1010 */ 1011 uint32_t slv_cmd_err_int_clr:1; 1012 /** mst_rx_afifo_wfull_err_int_clr : WT; bitpos: [17]; default: 0; 1013 * The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1014 */ 1015 uint32_t mst_rx_afifo_wfull_err_int_clr:1; 1016 /** mst_tx_afifo_rempty_err_int_clr : WT; bitpos: [18]; default: 0; 1017 * The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1018 */ 1019 uint32_t mst_tx_afifo_rempty_err_int_clr:1; 1020 /** app2_int_clr : WT; bitpos: [19]; default: 0; 1021 * The clear bit for SPI_APP2_INT interrupt. 1022 */ 1023 uint32_t app2_int_clr:1; 1024 /** app1_int_clr : WT; bitpos: [20]; default: 0; 1025 * The clear bit for SPI_APP1_INT interrupt. 1026 */ 1027 uint32_t app1_int_clr:1; 1028 uint32_t reserved_21:11; 1029 }; 1030 uint32_t val; 1031 } spi_dma_int_clr_reg_t; 1032 1033 /** Type of dma_int_raw register 1034 * SPI interrupt raw register 1035 */ 1036 typedef union { 1037 struct { 1038 /** dma_infifo_full_err_int_raw : R/WTC/SS; bitpos: [0]; default: 0; 1039 * 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the 1040 * receive data. 0: Others. 1041 */ 1042 uint32_t dma_infifo_full_err_int_raw:1; 1043 /** dma_outfifo_empty_err_int_raw : R/WTC/SS; bitpos: [1]; default: 0; 1044 * 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in 1045 * master mode and send out all 0 in slave mode. 0: Others. 1046 */ 1047 uint32_t dma_outfifo_empty_err_int_raw:1; 1048 /** slv_ex_qpi_int_raw : R/WTC/SS; bitpos: [2]; default: 0; 1049 * The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission 1050 * is ended. 0: Others. 1051 */ 1052 uint32_t slv_ex_qpi_int_raw:1; 1053 /** slv_en_qpi_int_raw : R/WTC/SS; bitpos: [3]; default: 0; 1054 * The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission 1055 * is ended. 0: Others. 1056 */ 1057 uint32_t slv_en_qpi_int_raw:1; 1058 /** slv_cmd7_int_raw : R/WTC/SS; bitpos: [4]; default: 0; 1059 * The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is 1060 * ended. 0: Others. 1061 */ 1062 uint32_t slv_cmd7_int_raw:1; 1063 /** slv_cmd8_int_raw : R/WTC/SS; bitpos: [5]; default: 0; 1064 * The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is 1065 * ended. 0: Others. 1066 */ 1067 uint32_t slv_cmd8_int_raw:1; 1068 /** slv_cmd9_int_raw : R/WTC/SS; bitpos: [6]; default: 0; 1069 * The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is 1070 * ended. 0: Others. 1071 */ 1072 uint32_t slv_cmd9_int_raw:1; 1073 /** slv_cmda_int_raw : R/WTC/SS; bitpos: [7]; default: 0; 1074 * The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is 1075 * ended. 0: Others. 1076 */ 1077 uint32_t slv_cmda_int_raw:1; 1078 /** slv_rd_dma_done_int_raw : R/WTC/SS; bitpos: [8]; default: 0; 1079 * The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA 1080 * transmission is ended. 0: Others. 1081 */ 1082 uint32_t slv_rd_dma_done_int_raw:1; 1083 /** slv_wr_dma_done_int_raw : R/WTC/SS; bitpos: [9]; default: 0; 1084 * The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA 1085 * transmission is ended. 0: Others. 1086 */ 1087 uint32_t slv_wr_dma_done_int_raw:1; 1088 /** slv_rd_buf_done_int_raw : R/WTC/SS; bitpos: [10]; default: 0; 1089 * The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF 1090 * transmission is ended. 0: Others. 1091 */ 1092 uint32_t slv_rd_buf_done_int_raw:1; 1093 /** slv_wr_buf_done_int_raw : R/WTC/SS; bitpos: [11]; default: 0; 1094 * The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF 1095 * transmission is ended. 0: Others. 1096 */ 1097 uint32_t slv_wr_buf_done_int_raw:1; 1098 /** trans_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0; 1099 * The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is 1100 * ended. 0: others. 1101 */ 1102 uint32_t trans_done_int_raw:1; 1103 /** dma_seg_trans_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0; 1104 * The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA 1105 * full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. 1106 * And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans 1107 * is not ended or not occurred. 1108 */ 1109 uint32_t dma_seg_trans_done_int_raw:1; 1110 /** seg_magic_err_int_raw : R/WTC/SS; bitpos: [14]; default: 0; 1111 * The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer 1112 * is error in the DMA seg-conf-trans. 0: others. 1113 */ 1114 uint32_t seg_magic_err_int_raw:1; 1115 /** slv_buf_addr_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0; 1116 * The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address 1117 * of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is 1118 * bigger than 63. 0: Others. 1119 */ 1120 uint32_t slv_buf_addr_err_int_raw:1; 1121 /** slv_cmd_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0; 1122 * The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the 1123 * current SPI slave HD mode transmission is not supported. 0: Others. 1124 */ 1125 uint32_t slv_cmd_err_int_raw:1; 1126 /** mst_rx_afifo_wfull_err_int_raw : R/WTC/SS; bitpos: [17]; default: 0; 1127 * The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO 1128 * write-full error when SPI inputs data in master mode. 0: Others. 1129 */ 1130 uint32_t mst_rx_afifo_wfull_err_int_raw:1; 1131 /** mst_tx_afifo_rempty_err_int_raw : R/WTC/SS; bitpos: [18]; default: 0; 1132 * The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF 1133 * AFIFO read-empty error when SPI outputs data in master mode. 0: Others. 1134 */ 1135 uint32_t mst_tx_afifo_rempty_err_int_raw:1; 1136 /** app2_int_raw : R/WTC/SS; bitpos: [19]; default: 0; 1137 * The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. 1138 */ 1139 uint32_t app2_int_raw:1; 1140 /** app1_int_raw : R/WTC/SS; bitpos: [20]; default: 0; 1141 * The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. 1142 */ 1143 uint32_t app1_int_raw:1; 1144 uint32_t reserved_21:11; 1145 }; 1146 uint32_t val; 1147 } spi_dma_int_raw_reg_t; 1148 1149 /** Type of dma_int_st register 1150 * SPI interrupt status register 1151 */ 1152 typedef union { 1153 struct { 1154 /** dma_infifo_full_err_int_st : RO; bitpos: [0]; default: 0; 1155 * The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. 1156 */ 1157 uint32_t dma_infifo_full_err_int_st:1; 1158 /** dma_outfifo_empty_err_int_st : RO; bitpos: [1]; default: 0; 1159 * The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. 1160 */ 1161 uint32_t dma_outfifo_empty_err_int_st:1; 1162 /** slv_ex_qpi_int_st : RO; bitpos: [2]; default: 0; 1163 * The status bit for SPI slave Ex_QPI interrupt. 1164 */ 1165 uint32_t slv_ex_qpi_int_st:1; 1166 /** slv_en_qpi_int_st : RO; bitpos: [3]; default: 0; 1167 * The status bit for SPI slave En_QPI interrupt. 1168 */ 1169 uint32_t slv_en_qpi_int_st:1; 1170 /** slv_cmd7_int_st : RO; bitpos: [4]; default: 0; 1171 * The status bit for SPI slave CMD7 interrupt. 1172 */ 1173 uint32_t slv_cmd7_int_st:1; 1174 /** slv_cmd8_int_st : RO; bitpos: [5]; default: 0; 1175 * The status bit for SPI slave CMD8 interrupt. 1176 */ 1177 uint32_t slv_cmd8_int_st:1; 1178 /** slv_cmd9_int_st : RO; bitpos: [6]; default: 0; 1179 * The status bit for SPI slave CMD9 interrupt. 1180 */ 1181 uint32_t slv_cmd9_int_st:1; 1182 /** slv_cmda_int_st : RO; bitpos: [7]; default: 0; 1183 * The status bit for SPI slave CMDA interrupt. 1184 */ 1185 uint32_t slv_cmda_int_st:1; 1186 /** slv_rd_dma_done_int_st : RO; bitpos: [8]; default: 0; 1187 * The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1188 */ 1189 uint32_t slv_rd_dma_done_int_st:1; 1190 /** slv_wr_dma_done_int_st : RO; bitpos: [9]; default: 0; 1191 * The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1192 */ 1193 uint32_t slv_wr_dma_done_int_st:1; 1194 /** slv_rd_buf_done_int_st : RO; bitpos: [10]; default: 0; 1195 * The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1196 */ 1197 uint32_t slv_rd_buf_done_int_st:1; 1198 /** slv_wr_buf_done_int_st : RO; bitpos: [11]; default: 0; 1199 * The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1200 */ 1201 uint32_t slv_wr_buf_done_int_st:1; 1202 /** trans_done_int_st : RO; bitpos: [12]; default: 0; 1203 * The status bit for SPI_TRANS_DONE_INT interrupt. 1204 */ 1205 uint32_t trans_done_int_st:1; 1206 /** dma_seg_trans_done_int_st : RO; bitpos: [13]; default: 0; 1207 * The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1208 */ 1209 uint32_t dma_seg_trans_done_int_st:1; 1210 /** seg_magic_err_int_st : RO; bitpos: [14]; default: 0; 1211 * The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1212 */ 1213 uint32_t seg_magic_err_int_st:1; 1214 /** slv_buf_addr_err_int_st : RO; bitpos: [15]; default: 0; 1215 * The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1216 */ 1217 uint32_t slv_buf_addr_err_int_st:1; 1218 /** slv_cmd_err_int_st : RO; bitpos: [16]; default: 0; 1219 * The status bit for SPI_SLV_CMD_ERR_INT interrupt. 1220 */ 1221 uint32_t slv_cmd_err_int_st:1; 1222 /** mst_rx_afifo_wfull_err_int_st : RO; bitpos: [17]; default: 0; 1223 * The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1224 */ 1225 uint32_t mst_rx_afifo_wfull_err_int_st:1; 1226 /** mst_tx_afifo_rempty_err_int_st : RO; bitpos: [18]; default: 0; 1227 * The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1228 */ 1229 uint32_t mst_tx_afifo_rempty_err_int_st:1; 1230 /** app2_int_st : RO; bitpos: [19]; default: 0; 1231 * The status bit for SPI_APP2_INT interrupt. 1232 */ 1233 uint32_t app2_int_st:1; 1234 /** app1_int_st : RO; bitpos: [20]; default: 0; 1235 * The status bit for SPI_APP1_INT interrupt. 1236 */ 1237 uint32_t app1_int_st:1; 1238 uint32_t reserved_21:11; 1239 }; 1240 uint32_t val; 1241 } spi_dma_int_st_reg_t; 1242 1243 /** Type of dma_int_set register 1244 * SPI interrupt software set register 1245 */ 1246 typedef union { 1247 struct { 1248 /** dma_infifo_full_err_int_set : WT; bitpos: [0]; default: 0; 1249 * The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. 1250 */ 1251 uint32_t dma_infifo_full_err_int_set:1; 1252 /** dma_outfifo_empty_err_int_set : WT; bitpos: [1]; default: 0; 1253 * The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. 1254 */ 1255 uint32_t dma_outfifo_empty_err_int_set:1; 1256 /** slv_ex_qpi_int_set : WT; bitpos: [2]; default: 0; 1257 * The software set bit for SPI slave Ex_QPI interrupt. 1258 */ 1259 uint32_t slv_ex_qpi_int_set:1; 1260 /** slv_en_qpi_int_set : WT; bitpos: [3]; default: 0; 1261 * The software set bit for SPI slave En_QPI interrupt. 1262 */ 1263 uint32_t slv_en_qpi_int_set:1; 1264 /** slv_cmd7_int_set : WT; bitpos: [4]; default: 0; 1265 * The software set bit for SPI slave CMD7 interrupt. 1266 */ 1267 uint32_t slv_cmd7_int_set:1; 1268 /** slv_cmd8_int_set : WT; bitpos: [5]; default: 0; 1269 * The software set bit for SPI slave CMD8 interrupt. 1270 */ 1271 uint32_t slv_cmd8_int_set:1; 1272 /** slv_cmd9_int_set : WT; bitpos: [6]; default: 0; 1273 * The software set bit for SPI slave CMD9 interrupt. 1274 */ 1275 uint32_t slv_cmd9_int_set:1; 1276 /** slv_cmda_int_set : WT; bitpos: [7]; default: 0; 1277 * The software set bit for SPI slave CMDA interrupt. 1278 */ 1279 uint32_t slv_cmda_int_set:1; 1280 /** slv_rd_dma_done_int_set : WT; bitpos: [8]; default: 0; 1281 * The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1282 */ 1283 uint32_t slv_rd_dma_done_int_set:1; 1284 /** slv_wr_dma_done_int_set : WT; bitpos: [9]; default: 0; 1285 * The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1286 */ 1287 uint32_t slv_wr_dma_done_int_set:1; 1288 /** slv_rd_buf_done_int_set : WT; bitpos: [10]; default: 0; 1289 * The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1290 */ 1291 uint32_t slv_rd_buf_done_int_set:1; 1292 /** slv_wr_buf_done_int_set : WT; bitpos: [11]; default: 0; 1293 * The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1294 */ 1295 uint32_t slv_wr_buf_done_int_set:1; 1296 /** trans_done_int_set : WT; bitpos: [12]; default: 0; 1297 * The software set bit for SPI_TRANS_DONE_INT interrupt. 1298 */ 1299 uint32_t trans_done_int_set:1; 1300 /** dma_seg_trans_done_int_set : WT; bitpos: [13]; default: 0; 1301 * The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1302 */ 1303 uint32_t dma_seg_trans_done_int_set:1; 1304 /** seg_magic_err_int_set : WT; bitpos: [14]; default: 0; 1305 * The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1306 */ 1307 uint32_t seg_magic_err_int_set:1; 1308 /** slv_buf_addr_err_int_set : WT; bitpos: [15]; default: 0; 1309 * The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1310 */ 1311 uint32_t slv_buf_addr_err_int_set:1; 1312 /** slv_cmd_err_int_set : WT; bitpos: [16]; default: 0; 1313 * The software set bit for SPI_SLV_CMD_ERR_INT interrupt. 1314 */ 1315 uint32_t slv_cmd_err_int_set:1; 1316 /** mst_rx_afifo_wfull_err_int_set : WT; bitpos: [17]; default: 0; 1317 * The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1318 */ 1319 uint32_t mst_rx_afifo_wfull_err_int_set:1; 1320 /** mst_tx_afifo_rempty_err_int_set : WT; bitpos: [18]; default: 0; 1321 * The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1322 */ 1323 uint32_t mst_tx_afifo_rempty_err_int_set:1; 1324 /** app2_int_set : WT; bitpos: [19]; default: 0; 1325 * The software set bit for SPI_APP2_INT interrupt. 1326 */ 1327 uint32_t app2_int_set:1; 1328 /** app1_int_set : WT; bitpos: [20]; default: 0; 1329 * The software set bit for SPI_APP1_INT interrupt. 1330 */ 1331 uint32_t app1_int_set:1; 1332 uint32_t reserved_21:11; 1333 }; 1334 uint32_t val; 1335 } spi_dma_int_set_reg_t; 1336 1337 1338 /** Group: CPU-controlled data buffer */ 1339 /** Type of w0 register 1340 * SPI CPU-controlled buffer0 1341 */ 1342 typedef union { 1343 struct { 1344 /** buf0 : R/W/SS; bitpos: [31:0]; default: 0; 1345 * data buffer 1346 */ 1347 uint32_t buf0:32; 1348 }; 1349 uint32_t val; 1350 } spi_wn_reg_t; 1351 1352 1353 /** Group: Version register */ 1354 /** Type of date register 1355 * Version control 1356 */ 1357 typedef union { 1358 struct { 1359 /** date : R/W; bitpos: [27:0]; default: 35656448; 1360 * SPI register version. 1361 */ 1362 uint32_t date:28; 1363 uint32_t reserved_28:4; 1364 }; 1365 uint32_t val; 1366 } spi_date_reg_t; 1367 1368 1369 typedef struct { 1370 volatile spi_cmd_reg_t cmd; 1371 volatile spi_addr_reg_t addr; 1372 volatile spi_ctrl_reg_t ctrl; 1373 volatile spi_clock_reg_t clock; 1374 volatile spi_user_reg_t user; 1375 volatile spi_user1_reg_t user1; 1376 volatile spi_user2_reg_t user2; 1377 volatile spi_ms_dlen_reg_t ms_dlen; 1378 volatile spi_misc_reg_t misc; 1379 volatile spi_din_mode_reg_t din_mode; 1380 volatile spi_din_num_reg_t din_num; 1381 volatile spi_dout_mode_reg_t dout_mode; 1382 volatile spi_dma_conf_reg_t dma_conf; 1383 volatile spi_dma_int_ena_reg_t dma_int_ena; 1384 volatile spi_dma_int_clr_reg_t dma_int_clr; 1385 volatile spi_dma_int_raw_reg_t dma_int_raw; 1386 volatile spi_dma_int_st_reg_t dma_int_st; 1387 volatile spi_dma_int_set_reg_t dma_int_set; 1388 uint32_t reserved_048[20]; 1389 volatile spi_wn_reg_t data_buf[16]; 1390 uint32_t reserved_0d8[2]; 1391 volatile spi_slave_reg_t slave; 1392 volatile spi_slave1_reg_t slave1; 1393 volatile spi_clk_gate_reg_t clk_gate; 1394 uint32_t reserved_0ec; 1395 volatile spi_date_reg_t date; 1396 } spi_dev_t; 1397 1398 extern spi_dev_t GPSPI2; 1399 1400 #ifndef __cplusplus 1401 _Static_assert(sizeof(spi_dev_t) == 0xf4, "Invalid size of spi_dev_t structure"); 1402 #endif 1403 1404 #ifdef __cplusplus 1405 } 1406 #endif 1407
