1 /** 2 * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #ifdef __cplusplus 10 extern "C" { 11 #endif 12 13 /** Group: Configuration registers */ 14 /** Type of slcconf0 register 15 * ******* Description *********** 16 */ 17 typedef union { 18 struct { 19 /** slc0_tx_rst : R/W; bitpos: [0]; default: 0; 20 * Set 1 to reset tx fsm in dma slc0. 21 */ 22 uint32_t slc0_tx_rst:1; 23 /** slc0_rx_rst : R/W; bitpos: [1]; default: 0; 24 * Set 1 to reset rx fsm in dma slc0. 25 */ 26 uint32_t slc0_rx_rst:1; 27 /** slc_ahbm_fifo_rst : R/W; bitpos: [2]; default: 0; 28 * reset the command fifo of AHB bus of sdio slave 29 */ 30 uint32_t slc_ahbm_fifo_rst:1; 31 /** slc_ahbm_rst : R/W; bitpos: [3]; default: 0; 32 * reset the AHB bus of sdio slave 33 */ 34 uint32_t slc_ahbm_rst:1; 35 /** slc0_tx_loop_test : R/W; bitpos: [4]; default: 0; 36 * owner control when slc1 writes back tx descriptor: 0- cpu is owner, 1-dma is owner. 37 */ 38 uint32_t slc0_tx_loop_test:1; 39 /** slc0_rx_loop_test : R/W; bitpos: [5]; default: 0; 40 * owner control when slc1 writes back rx descriptor: 0- cpu is owner, 1-dma is owner. 41 */ 42 uint32_t slc0_rx_loop_test:1; 43 /** slc0_rx_auto_wrback : R/W; bitpos: [6]; default: 0; 44 * Set 1 to enable change the owner bit of rx link descriptor 45 */ 46 uint32_t slc0_rx_auto_wrback:1; 47 /** slc0_rx_no_restart_clr : R/W; bitpos: [7]; default: 0; 48 * reserved 49 */ 50 uint32_t slc0_rx_no_restart_clr:1; 51 /** slc0_rxdscr_burst_en : R/W; bitpos: [8]; default: 1; 52 * 0- AHB burst type is single when slave read rx-descriptor from memory through 53 * slc0,1-AHB burst type is not single when slave read rx-descriptor from memory 54 * through slc0 55 */ 56 uint32_t slc0_rxdscr_burst_en:1; 57 /** slc0_rxdata_burst_en : R/W; bitpos: [9]; default: 1; 58 * 0- AHB burst type is single when slave receives data from memory,1-AHB burst type 59 * is not single when slave receives data from memory 60 */ 61 uint32_t slc0_rxdata_burst_en:1; 62 /** slc0_rxlink_auto_ret : R/W; bitpos: [10]; default: 1; 63 * enable the function that when host reading packet retries, slc1 will automatically 64 * jump to the start descriptor of the previous packet. 65 */ 66 uint32_t slc0_rxlink_auto_ret:1; 67 /** slc0_txlink_auto_ret : R/W; bitpos: [11]; default: 1; 68 * enable the function that when host sending packet retries, slc1 will automatically 69 * jump to the start descriptor of the previous packet. 70 */ 71 uint32_t slc0_txlink_auto_ret:1; 72 /** slc0_txdscr_burst_en : R/W; bitpos: [12]; default: 1; 73 * 0- AHB burst type is single when slave read tx-descriptor from memory through 74 * slc0,1-AHB burst type is not single when slave read tx-descriptor from memory 75 * through slc0 76 */ 77 uint32_t slc0_txdscr_burst_en:1; 78 /** slc0_txdata_burst_en : R/W; bitpos: [13]; default: 1; 79 * 0- AHB burst type is single when slave send data to memory,1-AHB burst type is not 80 * single when slave send data to memory 81 */ 82 uint32_t slc0_txdata_burst_en:1; 83 /** slc0_token_auto_clr : R/W; bitpos: [14]; default: 1; 84 * auto clear slc0_token1 enable 85 */ 86 uint32_t slc0_token_auto_clr:1; 87 /** slc0_token_sel : R/W; bitpos: [15]; default: 1; 88 * reserved 89 */ 90 uint32_t slc0_token_sel:1; 91 /** slc1_tx_rst : R/W; bitpos: [16]; default: 0; 92 * Set 1 to reset tx fsm in dma slc0. 93 */ 94 uint32_t slc1_tx_rst:1; 95 /** slc1_rx_rst : R/W; bitpos: [17]; default: 0; 96 * Set 1 to reset rx fsm in dma slc0. 97 */ 98 uint32_t slc1_rx_rst:1; 99 /** slc0_wr_retry_mask_en : R/W; bitpos: [18]; default: 1; 100 * reserved 101 */ 102 uint32_t slc0_wr_retry_mask_en:1; 103 /** slc1_wr_retry_mask_en : R/W; bitpos: [19]; default: 1; 104 * reserved 105 */ 106 uint32_t slc1_wr_retry_mask_en:1; 107 /** slc1_tx_loop_test : R/W; bitpos: [20]; default: 1; 108 * owner control when slc1 writes back tx descriptor: 0- cpu is owner, 1-dma is owner. 109 */ 110 uint32_t slc1_tx_loop_test:1; 111 /** slc1_rx_loop_test : R/W; bitpos: [21]; default: 1; 112 * owner control when slc1 writes back rx descriptor: 0- cpu is owner, 1-dma is owner. 113 */ 114 uint32_t slc1_rx_loop_test:1; 115 /** slc1_rx_auto_wrback : R/W; bitpos: [22]; default: 0; 116 * Set 1 to enable change the owner bit of rx link descriptor 117 */ 118 uint32_t slc1_rx_auto_wrback:1; 119 /** slc1_rx_no_restart_clr : R/W; bitpos: [23]; default: 0; 120 * ******* Description *********** 121 */ 122 uint32_t slc1_rx_no_restart_clr:1; 123 /** slc1_rxdscr_burst_en : R/W; bitpos: [24]; default: 1; 124 * 0- AHB burst type is single when slave read rx-descriptor from memory through 125 * slc1,1-AHB burst type is not single when slave read rx-descriptor from memory 126 * through slc1 127 */ 128 uint32_t slc1_rxdscr_burst_en:1; 129 /** slc1_rxdata_burst_en : R/W; bitpos: [25]; default: 1; 130 * 0- AHB burst type is single when slave receives data from memory,1-AHB burst type 131 * is not single when slave receives data from memory 132 */ 133 uint32_t slc1_rxdata_burst_en:1; 134 /** slc1_rxlink_auto_ret : R/W; bitpos: [26]; default: 1; 135 * enable the function that when host reading packet retries, slc1 will automatically 136 * jump to the start descriptor of the previous packet. 137 */ 138 uint32_t slc1_rxlink_auto_ret:1; 139 /** slc1_txlink_auto_ret : R/W; bitpos: [27]; default: 1; 140 * enable the function that when host sending packet retries, slc1 will automatically 141 * jump to the start descriptor of the previous packet. 142 */ 143 uint32_t slc1_txlink_auto_ret:1; 144 /** slc1_txdscr_burst_en : R/W; bitpos: [28]; default: 1; 145 * 0- AHB burst type is single when slave read tx-descriptor from memory through 146 * slc1,1-AHB burst type is not single when slave read tx-descriptor from memory 147 * through slc1 148 */ 149 uint32_t slc1_txdscr_burst_en:1; 150 /** slc1_txdata_burst_en : R/W; bitpos: [29]; default: 1; 151 * 0- AHB burst type is single when slave send data to memory,1-AHB burst type is not 152 * single when slave send data to memory 153 */ 154 uint32_t slc1_txdata_burst_en:1; 155 /** slc1_token_auto_clr : R/W; bitpos: [30]; default: 1; 156 * auto clear slc1_token1 enable 157 */ 158 uint32_t slc1_token_auto_clr:1; 159 /** slc1_token_sel : R/W; bitpos: [31]; default: 1; 160 * reserved 161 */ 162 uint32_t slc1_token_sel:1; 163 }; 164 uint32_t val; 165 } sdio_slcconf0_reg_t; 166 167 /** Type of slc0rxfifo_push register 168 * ******* Description *********** 169 */ 170 typedef union { 171 struct { 172 /** slc0_rxfifo_wdata : R/W; bitpos: [8:0]; default: 0; 173 * reserved 174 */ 175 uint32_t slc0_rxfifo_wdata:9; 176 uint32_t reserved_9:7; 177 /** slc0_rxfifo_push : R/W/SC; bitpos: [16]; default: 0; 178 * reserved 179 */ 180 uint32_t slc0_rxfifo_push:1; 181 uint32_t reserved_17:15; 182 }; 183 uint32_t val; 184 } sdio_slc0rxfifo_push_reg_t; 185 186 /** Type of slc1rxfifo_push register 187 * reserved 188 */ 189 typedef union { 190 struct { 191 /** slc1_rxfifo_wdata : R/W; bitpos: [8:0]; default: 0; 192 * reserved 193 */ 194 uint32_t slc1_rxfifo_wdata:9; 195 uint32_t reserved_9:7; 196 /** slc1_rxfifo_push : R/W/SC; bitpos: [16]; default: 0; 197 * reserved 198 */ 199 uint32_t slc1_rxfifo_push:1; 200 uint32_t reserved_17:15; 201 }; 202 uint32_t val; 203 } sdio_slc1rxfifo_push_reg_t; 204 205 /** Type of slc0rx_link register 206 * reserved 207 */ 208 typedef union { 209 struct { 210 uint32_t reserved_0:28; 211 /** slc0_rxlink_stop : R/W/SC; bitpos: [28]; default: 0; 212 * reserved 213 */ 214 uint32_t slc0_rxlink_stop:1; 215 /** slc0_rxlink_start : R/W/SC; bitpos: [29]; default: 0; 216 * reserved 217 */ 218 uint32_t slc0_rxlink_start:1; 219 /** slc0_rxlink_restart : R/W/SC; bitpos: [30]; default: 0; 220 * reserved 221 */ 222 uint32_t slc0_rxlink_restart:1; 223 /** slc0_rxlink_park : RO; bitpos: [31]; default: 1; 224 * reserved 225 */ 226 uint32_t slc0_rxlink_park:1; 227 }; 228 uint32_t val; 229 } sdio_slc0rx_link_reg_t; 230 231 /** Type of slc0rx_link_addr register 232 * reserved 233 */ 234 typedef union { 235 struct { 236 /** slc0_rxlink_addr : R/W; bitpos: [31:0]; default: 0; 237 * reserved 238 */ 239 uint32_t slc0_rxlink_addr:32; 240 }; 241 uint32_t val; 242 } sdio_slc0rx_link_addr_reg_t; 243 244 /** Type of slc0tx_link register 245 * reserved 246 */ 247 typedef union { 248 struct { 249 uint32_t reserved_0:28; 250 /** slc0_txlink_stop : R/W/SC; bitpos: [28]; default: 0; 251 * reserved 252 */ 253 uint32_t slc0_txlink_stop:1; 254 /** slc0_txlink_start : R/W/SC; bitpos: [29]; default: 0; 255 * reserved 256 */ 257 uint32_t slc0_txlink_start:1; 258 /** slc0_txlink_restart : R/W/SC; bitpos: [30]; default: 0; 259 * reserved 260 */ 261 uint32_t slc0_txlink_restart:1; 262 /** slc0_txlink_park : RO; bitpos: [31]; default: 1; 263 * reserved 264 */ 265 uint32_t slc0_txlink_park:1; 266 }; 267 uint32_t val; 268 } sdio_slc0tx_link_reg_t; 269 270 /** Type of slc0tx_link_addr register 271 * reserved 272 */ 273 typedef union { 274 struct { 275 /** slc0_txlink_addr : R/W; bitpos: [31:0]; default: 0; 276 * reserved 277 */ 278 uint32_t slc0_txlink_addr:32; 279 }; 280 uint32_t val; 281 } sdio_slc0tx_link_addr_reg_t; 282 283 /** Type of slc1rx_link register 284 * reserved 285 */ 286 typedef union { 287 struct { 288 uint32_t reserved_0:20; 289 /** slc1_bt_packet : R/W; bitpos: [20]; default: 1; 290 * reserved 291 */ 292 uint32_t slc1_bt_packet:1; 293 uint32_t reserved_21:7; 294 /** slc1_rxlink_stop : R/W/SC; bitpos: [28]; default: 0; 295 * reserved 296 */ 297 uint32_t slc1_rxlink_stop:1; 298 /** slc1_rxlink_start : R/W/SC; bitpos: [29]; default: 0; 299 * reserved 300 */ 301 uint32_t slc1_rxlink_start:1; 302 /** slc1_rxlink_restart : R/W/SC; bitpos: [30]; default: 0; 303 * reserved 304 */ 305 uint32_t slc1_rxlink_restart:1; 306 /** slc1_rxlink_park : RO; bitpos: [31]; default: 1; 307 * reserved 308 */ 309 uint32_t slc1_rxlink_park:1; 310 }; 311 uint32_t val; 312 } sdio_slc1rx_link_reg_t; 313 314 /** Type of slc1rx_link_addr register 315 * reserved 316 */ 317 typedef union { 318 struct { 319 /** slc1_rxlink_addr : R/W; bitpos: [31:0]; default: 0; 320 * reserved 321 */ 322 uint32_t slc1_rxlink_addr:32; 323 }; 324 uint32_t val; 325 } sdio_slc1rx_link_addr_reg_t; 326 327 /** Type of slc1tx_link register 328 * reserved 329 */ 330 typedef union { 331 struct { 332 uint32_t reserved_0:28; 333 /** slc1_txlink_stop : R/W/SC; bitpos: [28]; default: 0; 334 * reserved 335 */ 336 uint32_t slc1_txlink_stop:1; 337 /** slc1_txlink_start : R/W/SC; bitpos: [29]; default: 0; 338 * reserved 339 */ 340 uint32_t slc1_txlink_start:1; 341 /** slc1_txlink_restart : R/W/SC; bitpos: [30]; default: 0; 342 * reserved 343 */ 344 uint32_t slc1_txlink_restart:1; 345 /** slc1_txlink_park : RO; bitpos: [31]; default: 1; 346 * reserved 347 */ 348 uint32_t slc1_txlink_park:1; 349 }; 350 uint32_t val; 351 } sdio_slc1tx_link_reg_t; 352 353 /** Type of slc1tx_link_addr register 354 * reserved 355 */ 356 typedef union { 357 struct { 358 /** slc1_txlink_addr : R/W; bitpos: [31:0]; default: 0; 359 * reserved 360 */ 361 uint32_t slc1_txlink_addr:32; 362 }; 363 uint32_t val; 364 } sdio_slc1tx_link_addr_reg_t; 365 366 /** Type of slcintvec_tohost register 367 * reserved 368 */ 369 typedef union { 370 struct { 371 /** slc0_tohost_intvec : WT; bitpos: [7:0]; default: 0; 372 * reserved 373 */ 374 uint32_t slc0_tohost_intvec:8; 375 uint32_t reserved_8:8; 376 /** slc1_tohost_intvec : WT; bitpos: [23:16]; default: 0; 377 * reserved 378 */ 379 uint32_t slc1_tohost_intvec:8; 380 uint32_t reserved_24:8; 381 }; 382 uint32_t val; 383 } sdio_slcintvec_tohost_reg_t; 384 385 /** Type of slc0token0 register 386 * reserved 387 */ 388 typedef union { 389 struct { 390 /** slc0_token0_wdata : WT; bitpos: [11:0]; default: 0; 391 * reserved 392 */ 393 uint32_t slc0_token0_wdata:12; 394 /** slc0_token0_wr : WT; bitpos: [12]; default: 0; 395 * reserved 396 */ 397 uint32_t slc0_token0_wr:1; 398 /** slc0_token0_inc : WT; bitpos: [13]; default: 0; 399 * reserved 400 */ 401 uint32_t slc0_token0_inc:1; 402 /** slc0_token0_inc_more : WT; bitpos: [14]; default: 0; 403 * reserved 404 */ 405 uint32_t slc0_token0_inc_more:1; 406 uint32_t reserved_15:1; 407 /** slc0_token0 : RO; bitpos: [27:16]; default: 0; 408 * reserved 409 */ 410 uint32_t slc0_token0:12; 411 uint32_t reserved_28:4; 412 }; 413 uint32_t val; 414 } sdio_slc0token0_reg_t; 415 416 /** Type of slc0token1 register 417 * reserved 418 */ 419 typedef union { 420 struct { 421 /** slc0_token1_wdata : WT; bitpos: [11:0]; default: 0; 422 * slc0 token1 wdata 423 */ 424 uint32_t slc0_token1_wdata:12; 425 /** slc0_token1_wr : WT; bitpos: [12]; default: 0; 426 * update slc0_token1_wdata into slc0 token1 427 */ 428 uint32_t slc0_token1_wr:1; 429 /** slc0_token1_inc : WT; bitpos: [13]; default: 0; 430 * slc0_token1 becomes to 1 when auto clear slc0_token1, else add 1 to slc0_token1 431 */ 432 uint32_t slc0_token1_inc:1; 433 /** slc0_token1_inc_more : WT; bitpos: [14]; default: 0; 434 * slc0_token1 becomes to slc0_token1_wdata when auto clear slc0_token1, else add 435 * slc0_token1_wdata to slc0_token1 436 */ 437 uint32_t slc0_token1_inc_more:1; 438 uint32_t reserved_15:1; 439 /** slc0_token1 : RO; bitpos: [27:16]; default: 0; 440 * reserved 441 */ 442 uint32_t slc0_token1:12; 443 uint32_t reserved_28:4; 444 }; 445 uint32_t val; 446 } sdio_slc0token1_reg_t; 447 448 /** Type of slc1token0 register 449 * ******* Description *********** 450 */ 451 typedef union { 452 struct { 453 /** slc1_token0_wdata : WT; bitpos: [11:0]; default: 0; 454 * reserved 455 */ 456 uint32_t slc1_token0_wdata:12; 457 /** slc1_token0_wr : WT; bitpos: [12]; default: 0; 458 * reserved 459 */ 460 uint32_t slc1_token0_wr:1; 461 /** slc1_token0_inc : WT; bitpos: [13]; default: 0; 462 * Add 1 to slc1_token0 463 */ 464 uint32_t slc1_token0_inc:1; 465 /** slc1_token0_inc_more : WT; bitpos: [14]; default: 0; 466 * Add slc1_token0_wdata to slc1_token0 467 */ 468 uint32_t slc1_token0_inc_more:1; 469 uint32_t reserved_15:1; 470 /** slc1_token0 : RO; bitpos: [27:16]; default: 0; 471 * reserved 472 */ 473 uint32_t slc1_token0:12; 474 uint32_t reserved_28:4; 475 }; 476 uint32_t val; 477 } sdio_slc1token0_reg_t; 478 479 /** Type of slc1token1 register 480 * reserved 481 */ 482 typedef union { 483 struct { 484 /** slc1_token1_wdata : WT; bitpos: [11:0]; default: 0; 485 * reserved 486 */ 487 uint32_t slc1_token1_wdata:12; 488 /** slc1_token1_wr : WT; bitpos: [12]; default: 0; 489 * update slc1_token1_wdata into slc1 token1 490 */ 491 uint32_t slc1_token1_wr:1; 492 /** slc1_token1_inc : WT; bitpos: [13]; default: 0; 493 * reserved 494 */ 495 uint32_t slc1_token1_inc:1; 496 /** slc1_token1_inc_more : WT; bitpos: [14]; default: 0; 497 * reserved 498 */ 499 uint32_t slc1_token1_inc_more:1; 500 uint32_t reserved_15:1; 501 /** slc1_token1 : RO; bitpos: [27:16]; default: 0; 502 * reserved 503 */ 504 uint32_t slc1_token1:12; 505 uint32_t reserved_28:4; 506 }; 507 uint32_t val; 508 } sdio_slc1token1_reg_t; 509 510 /** Type of slcconf1 register 511 * reserved 512 */ 513 typedef union { 514 struct { 515 /** slc0_check_owner : R/W; bitpos: [0]; default: 0; 516 * reserved 517 */ 518 uint32_t slc0_check_owner:1; 519 /** slc0_tx_check_sum_en : R/W; bitpos: [1]; default: 0; 520 * reserved 521 */ 522 uint32_t slc0_tx_check_sum_en:1; 523 /** slc0_rx_check_sum_en : R/W; bitpos: [2]; default: 0; 524 * reserved 525 */ 526 uint32_t slc0_rx_check_sum_en:1; 527 /** sdio_cmd_hold_en : R/W; bitpos: [3]; default: 1; 528 * reserved 529 */ 530 uint32_t sdio_cmd_hold_en:1; 531 /** slc0_len_auto_clr : R/W; bitpos: [4]; default: 1; 532 * reserved 533 */ 534 uint32_t slc0_len_auto_clr:1; 535 /** slc0_tx_stitch_en : R/W; bitpos: [5]; default: 1; 536 * reserved 537 */ 538 uint32_t slc0_tx_stitch_en:1; 539 /** slc0_rx_stitch_en : R/W; bitpos: [6]; default: 1; 540 * reserved 541 */ 542 uint32_t slc0_rx_stitch_en:1; 543 uint32_t reserved_7:9; 544 /** slc1_check_owner : R/W; bitpos: [16]; default: 0; 545 * reserved 546 */ 547 uint32_t slc1_check_owner:1; 548 /** slc1_tx_check_sum_en : R/W; bitpos: [17]; default: 0; 549 * reserved 550 */ 551 uint32_t slc1_tx_check_sum_en:1; 552 /** slc1_rx_check_sum_en : R/W; bitpos: [18]; default: 0; 553 * reserved 554 */ 555 uint32_t slc1_rx_check_sum_en:1; 556 /** host_int_level_sel : R/W; bitpos: [19]; default: 0; 557 * reserved 558 */ 559 uint32_t host_int_level_sel:1; 560 /** slc1_tx_stitch_en : R/W; bitpos: [20]; default: 1; 561 * reserved 562 */ 563 uint32_t slc1_tx_stitch_en:1; 564 /** slc1_rx_stitch_en : R/W; bitpos: [21]; default: 1; 565 * reserved 566 */ 567 uint32_t slc1_rx_stitch_en:1; 568 /** sdio_clk_en : R/W; bitpos: [22]; default: 0; 569 * reserved 570 */ 571 uint32_t sdio_clk_en:1; 572 uint32_t reserved_23:9; 573 }; 574 uint32_t val; 575 } sdio_slcconf1_reg_t; 576 577 /** Type of slcbridge_conf register 578 * ******* Description *********** 579 */ 580 typedef union { 581 struct { 582 /** slc_txeof_ena : R/W; bitpos: [5:0]; default: 32; 583 * reserved 584 */ 585 uint32_t slc_txeof_ena:6; 586 uint32_t reserved_6:2; 587 /** slc_fifo_map_ena : R/W; bitpos: [11:8]; default: 7; 588 * reserved 589 */ 590 uint32_t slc_fifo_map_ena:4; 591 /** slc0_tx_dummy_mode : R/W; bitpos: [12]; default: 1; 592 * reserved 593 */ 594 uint32_t slc0_tx_dummy_mode:1; 595 /** slc_hda_map_128k : R/W; bitpos: [13]; default: 1; 596 * reserved 597 */ 598 uint32_t slc_hda_map_128k:1; 599 /** slc1_tx_dummy_mode : R/W; bitpos: [14]; default: 1; 600 * reserved 601 */ 602 uint32_t slc1_tx_dummy_mode:1; 603 uint32_t reserved_15:1; 604 /** slc_tx_push_idle_num : R/W; bitpos: [31:16]; default: 10; 605 * reserved 606 */ 607 uint32_t slc_tx_push_idle_num:16; 608 }; 609 uint32_t val; 610 } sdio_slcbridge_conf_reg_t; 611 612 /** Type of slc0_to_eof_des_addr register 613 * reserved 614 */ 615 typedef union { 616 struct { 617 /** slc0_to_eof_des_addr : RO; bitpos: [31:0]; default: 0; 618 * reserved 619 */ 620 uint32_t slc0_to_eof_des_addr:32; 621 }; 622 uint32_t val; 623 } sdio_slc0_to_eof_des_addr_reg_t; 624 625 /** Type of slc0_tx_eof_des_addr register 626 * reserved 627 */ 628 typedef union { 629 struct { 630 /** slc0_tx_suc_eof_des_addr : RO; bitpos: [31:0]; default: 0; 631 * reserved 632 */ 633 uint32_t slc0_tx_suc_eof_des_addr:32; 634 }; 635 uint32_t val; 636 } sdio_slc0_tx_eof_des_addr_reg_t; 637 638 /** Type of slc0_to_eof_bfr_des_addr register 639 * reserved 640 */ 641 typedef union { 642 struct { 643 /** slc0_to_eof_bfr_des_addr : RO; bitpos: [31:0]; default: 0; 644 * reserved 645 */ 646 uint32_t slc0_to_eof_bfr_des_addr:32; 647 }; 648 uint32_t val; 649 } sdio_slc0_to_eof_bfr_des_addr_reg_t; 650 651 /** Type of slc1_to_eof_des_addr register 652 * reserved 653 */ 654 typedef union { 655 struct { 656 /** slc1_to_eof_des_addr : RO; bitpos: [31:0]; default: 0; 657 * reserved 658 */ 659 uint32_t slc1_to_eof_des_addr:32; 660 }; 661 uint32_t val; 662 } sdio_slc1_to_eof_des_addr_reg_t; 663 664 /** Type of slc1_tx_eof_des_addr register 665 * reserved 666 */ 667 typedef union { 668 struct { 669 /** slc1_tx_suc_eof_des_addr : RO; bitpos: [31:0]; default: 0; 670 * reserved 671 */ 672 uint32_t slc1_tx_suc_eof_des_addr:32; 673 }; 674 uint32_t val; 675 } sdio_slc1_tx_eof_des_addr_reg_t; 676 677 /** Type of slc1_to_eof_bfr_des_addr register 678 * reserved 679 */ 680 typedef union { 681 struct { 682 /** slc1_to_eof_bfr_des_addr : RO; bitpos: [31:0]; default: 0; 683 * reserved 684 */ 685 uint32_t slc1_to_eof_bfr_des_addr:32; 686 }; 687 uint32_t val; 688 } sdio_slc1_to_eof_bfr_des_addr_reg_t; 689 690 /** Type of slc_rx_dscr_conf register 691 * reserved 692 */ 693 typedef union { 694 struct { 695 /** slc0_token_no_replace : R/W; bitpos: [0]; default: 0; 696 * reserved 697 */ 698 uint32_t slc0_token_no_replace:1; 699 /** slc0_infor_no_replace : R/W; bitpos: [1]; default: 1; 700 * reserved 701 */ 702 uint32_t slc0_infor_no_replace:1; 703 /** slc0_rx_fill_mode : R/W; bitpos: [2]; default: 0; 704 * slc0 rx pop end control: 0-automatically end when pop finish, 1- end when the next 705 * pop doesn't occur after 255 cycles since the current pop 706 */ 707 uint32_t slc0_rx_fill_mode:1; 708 /** slc0_rx_eof_mode : R/W; bitpos: [3]; default: 1; 709 * 0-slc0 rx_push_eof, 1-slc0 rx_pop_eof 710 */ 711 uint32_t slc0_rx_eof_mode:1; 712 /** slc0_rx_fill_en : R/W; bitpos: [4]; default: 1; 713 * reserved 714 */ 715 uint32_t slc0_rx_fill_en:1; 716 /** slc0_rd_retry_threshold : R/W; bitpos: [15:5]; default: 128; 717 * reserved 718 */ 719 uint32_t slc0_rd_retry_threshold:11; 720 /** slc1_token_no_replace : R/W; bitpos: [16]; default: 1; 721 * reserved 722 */ 723 uint32_t slc1_token_no_replace:1; 724 /** slc1_infor_no_replace : R/W; bitpos: [17]; default: 1; 725 * reserved 726 */ 727 uint32_t slc1_infor_no_replace:1; 728 /** slc1_rx_fill_mode : R/W; bitpos: [18]; default: 0; 729 * slc1 rx pop end control: 0-automatically end when pop finish, 1- end when the next 730 * pop doesn't occur after 255 cycles since the current pop 731 */ 732 uint32_t slc1_rx_fill_mode:1; 733 /** slc1_rx_eof_mode : R/W; bitpos: [19]; default: 1; 734 * 0-slc1 rx_push_eof, 1-slc1 rx_pop_eof 735 */ 736 uint32_t slc1_rx_eof_mode:1; 737 /** slc1_rx_fill_en : R/W; bitpos: [20]; default: 1; 738 * reserved 739 */ 740 uint32_t slc1_rx_fill_en:1; 741 /** slc1_rd_retry_threshold : R/W; bitpos: [31:21]; default: 128; 742 * reserved 743 */ 744 uint32_t slc1_rd_retry_threshold:11; 745 }; 746 uint32_t val; 747 } sdio_slc_rx_dscr_conf_reg_t; 748 749 /** Type of slc_tx_dscr_conf register 750 * reserved 751 */ 752 typedef union { 753 struct { 754 /** slc_wr_retry_threshold : R/W; bitpos: [10:0]; default: 128; 755 * reserved 756 */ 757 uint32_t slc_wr_retry_threshold:11; 758 uint32_t reserved_11:21; 759 }; 760 uint32_t val; 761 } sdio_slc_tx_dscr_conf_reg_t; 762 763 /** Type of slc0_len_conf register 764 * reserved 765 */ 766 typedef union { 767 struct { 768 /** slc0_len_wdata : WT; bitpos: [19:0]; default: 0; 769 * reserved 770 */ 771 uint32_t slc0_len_wdata:20; 772 /** slc0_len_wr : WT; bitpos: [20]; default: 0; 773 * reserved 774 */ 775 uint32_t slc0_len_wr:1; 776 /** slc0_len_inc : WT; bitpos: [21]; default: 0; 777 * reserved 778 */ 779 uint32_t slc0_len_inc:1; 780 /** slc0_len_inc_more : WT; bitpos: [22]; default: 0; 781 * reserved 782 */ 783 uint32_t slc0_len_inc_more:1; 784 /** slc0_rx_packet_load_en : WT; bitpos: [23]; default: 0; 785 * reserved 786 */ 787 uint32_t slc0_rx_packet_load_en:1; 788 /** slc0_tx_packet_load_en : WT; bitpos: [24]; default: 0; 789 * reserved 790 */ 791 uint32_t slc0_tx_packet_load_en:1; 792 /** slc0_rx_get_used_dscr : WT; bitpos: [25]; default: 0; 793 * reserved 794 */ 795 uint32_t slc0_rx_get_used_dscr:1; 796 /** slc0_tx_get_used_dscr : WT; bitpos: [26]; default: 0; 797 * reserved 798 */ 799 uint32_t slc0_tx_get_used_dscr:1; 800 /** slc0_rx_new_pkt_ind : RO; bitpos: [27]; default: 0; 801 * reserved 802 */ 803 uint32_t slc0_rx_new_pkt_ind:1; 804 /** slc0_tx_new_pkt_ind : RO; bitpos: [28]; default: 1; 805 * reserved 806 */ 807 uint32_t slc0_tx_new_pkt_ind:1; 808 /** slc0_rx_packet_load_en_st : R/WTC/SC; bitpos: [29]; default: 0; 809 * reserved 810 */ 811 uint32_t slc0_rx_packet_load_en_st:1; 812 /** slc0_tx_packet_load_en_st : R/WTC/SC; bitpos: [30]; default: 0; 813 * reserved 814 */ 815 uint32_t slc0_tx_packet_load_en_st:1; 816 uint32_t reserved_31:1; 817 }; 818 uint32_t val; 819 } sdio_slc0_len_conf_reg_t; 820 821 /** Type of slc0_txpkt_h_dscr register 822 * reserved 823 */ 824 typedef union { 825 struct { 826 /** slc0_tx_pkt_h_dscr_addr : R/W; bitpos: [31:0]; default: 0; 827 * reserved 828 */ 829 uint32_t slc0_tx_pkt_h_dscr_addr:32; 830 }; 831 uint32_t val; 832 } sdio_slc0_txpkt_h_dscr_reg_t; 833 834 /** Type of slc0_txpkt_e_dscr register 835 * reserved 836 */ 837 typedef union { 838 struct { 839 /** slc0_tx_pkt_e_dscr_addr : R/W; bitpos: [31:0]; default: 0; 840 * reserved 841 */ 842 uint32_t slc0_tx_pkt_e_dscr_addr:32; 843 }; 844 uint32_t val; 845 } sdio_slc0_txpkt_e_dscr_reg_t; 846 847 /** Type of slc0_rxpkt_h_dscr register 848 * reserved 849 */ 850 typedef union { 851 struct { 852 /** slc0_rx_pkt_h_dscr_addr : R/W; bitpos: [31:0]; default: 0; 853 * reserved 854 */ 855 uint32_t slc0_rx_pkt_h_dscr_addr:32; 856 }; 857 uint32_t val; 858 } sdio_slc0_rxpkt_h_dscr_reg_t; 859 860 /** Type of slc0_rxpkt_e_dscr register 861 * reserved 862 */ 863 typedef union { 864 struct { 865 /** slc0_rx_pkt_e_dscr_addr : R/W; bitpos: [31:0]; default: 0; 866 * reserved 867 */ 868 uint32_t slc0_rx_pkt_e_dscr_addr:32; 869 }; 870 uint32_t val; 871 } sdio_slc0_rxpkt_e_dscr_reg_t; 872 873 /** Type of slc0_txpktu_h_dscr register 874 * reserved 875 */ 876 typedef union { 877 struct { 878 /** slc0_tx_pkt_start_dscr_addr : RO; bitpos: [31:0]; default: 0; 879 * reserved 880 */ 881 uint32_t slc0_tx_pkt_start_dscr_addr:32; 882 }; 883 uint32_t val; 884 } sdio_slc0_txpktu_h_dscr_reg_t; 885 886 /** Type of slc0_txpktu_e_dscr register 887 * reserved 888 */ 889 typedef union { 890 struct { 891 /** slc0_tx_pkt_end_dscr_addr : RO; bitpos: [31:0]; default: 0; 892 * reserved 893 */ 894 uint32_t slc0_tx_pkt_end_dscr_addr:32; 895 }; 896 uint32_t val; 897 } sdio_slc0_txpktu_e_dscr_reg_t; 898 899 /** Type of slc0_rxpktu_h_dscr register 900 * reserved 901 */ 902 typedef union { 903 struct { 904 /** slc0_rx_pkt_start_dscr_addr : RO; bitpos: [31:0]; default: 0; 905 * reserved 906 */ 907 uint32_t slc0_rx_pkt_start_dscr_addr:32; 908 }; 909 uint32_t val; 910 } sdio_slc0_rxpktu_h_dscr_reg_t; 911 912 /** Type of slc0_rxpktu_e_dscr register 913 * reserved 914 */ 915 typedef union { 916 struct { 917 /** slc0_rx_pkt_end_dscr_addr : RO; bitpos: [31:0]; default: 0; 918 * reserved 919 */ 920 uint32_t slc0_rx_pkt_end_dscr_addr:32; 921 }; 922 uint32_t val; 923 } sdio_slc0_rxpktu_e_dscr_reg_t; 924 925 /** Type of slc_seq_position register 926 * reserved 927 */ 928 typedef union { 929 struct { 930 /** slc0_seq_position : R/W; bitpos: [7:0]; default: 9; 931 * reserved 932 */ 933 uint32_t slc0_seq_position:8; 934 /** slc1_seq_position : R/W; bitpos: [15:8]; default: 5; 935 * reserved 936 */ 937 uint32_t slc1_seq_position:8; 938 uint32_t reserved_16:16; 939 }; 940 uint32_t val; 941 } sdio_slc_seq_position_reg_t; 942 943 /** Type of slc0_dscr_rec_conf register 944 * reserved 945 */ 946 typedef union { 947 struct { 948 /** slc0_rx_dscr_rec_lim : R/W; bitpos: [9:0]; default: 1023; 949 * reserved 950 */ 951 uint32_t slc0_rx_dscr_rec_lim:10; 952 uint32_t reserved_10:22; 953 }; 954 uint32_t val; 955 } sdio_slc0_dscr_rec_conf_reg_t; 956 957 /** Type of slc_sdio_crc_st1 register 958 * reserved 959 */ 960 typedef union { 961 struct { 962 /** cmd_crc_err_cnt : RO; bitpos: [7:0]; default: 0; 963 * reserved 964 */ 965 uint32_t cmd_crc_err_cnt:8; 966 uint32_t reserved_8:23; 967 /** err_cnt_clr : R/W; bitpos: [31]; default: 0; 968 * reserved 969 */ 970 uint32_t err_cnt_clr:1; 971 }; 972 uint32_t val; 973 } sdio_slc_sdio_crc_st1_reg_t; 974 975 /** Type of slc0_len_lim_conf register 976 * ******* Description *********** 977 */ 978 typedef union { 979 struct { 980 /** slc0_len_lim : R/W; bitpos: [19:0]; default: 21504; 981 * reserved 982 */ 983 uint32_t slc0_len_lim:20; 984 uint32_t reserved_20:12; 985 }; 986 uint32_t val; 987 } sdio_slc0_len_lim_conf_reg_t; 988 989 /** Type of slc0_tx_sharemem_start register 990 * reserved 991 */ 992 typedef union { 993 struct { 994 /** sdio_slc0_tx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; 995 * reserved 996 */ 997 uint32_t sdio_slc0_tx_sharemem_start_addr:32; 998 }; 999 uint32_t val; 1000 } sdio_slc0_tx_sharemem_start_reg_t; 1001 1002 /** Type of slc0_tx_sharemem_end register 1003 * reserved 1004 */ 1005 typedef union { 1006 struct { 1007 /** sdio_slc0_tx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; 1008 * reserved 1009 */ 1010 uint32_t sdio_slc0_tx_sharemem_end_addr:32; 1011 }; 1012 uint32_t val; 1013 } sdio_slc0_tx_sharemem_end_reg_t; 1014 1015 /** Type of slc0_rx_sharemem_start register 1016 * reserved 1017 */ 1018 typedef union { 1019 struct { 1020 /** sdio_slc0_rx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; 1021 * reserved 1022 */ 1023 uint32_t sdio_slc0_rx_sharemem_start_addr:32; 1024 }; 1025 uint32_t val; 1026 } sdio_slc0_rx_sharemem_start_reg_t; 1027 1028 /** Type of slc0_rx_sharemem_end register 1029 * reserved 1030 */ 1031 typedef union { 1032 struct { 1033 /** sdio_slc0_rx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; 1034 * reserved 1035 */ 1036 uint32_t sdio_slc0_rx_sharemem_end_addr:32; 1037 }; 1038 uint32_t val; 1039 } sdio_slc0_rx_sharemem_end_reg_t; 1040 1041 /** Type of slc1_tx_sharemem_start register 1042 * reserved 1043 */ 1044 typedef union { 1045 struct { 1046 /** sdio_slc1_tx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; 1047 * reserved 1048 */ 1049 uint32_t sdio_slc1_tx_sharemem_start_addr:32; 1050 }; 1051 uint32_t val; 1052 } sdio_slc1_tx_sharemem_start_reg_t; 1053 1054 /** Type of slc1_tx_sharemem_end register 1055 * reserved 1056 */ 1057 typedef union { 1058 struct { 1059 /** sdio_slc1_tx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; 1060 * reserved 1061 */ 1062 uint32_t sdio_slc1_tx_sharemem_end_addr:32; 1063 }; 1064 uint32_t val; 1065 } sdio_slc1_tx_sharemem_end_reg_t; 1066 1067 /** Type of slc1_rx_sharemem_start register 1068 * reserved 1069 */ 1070 typedef union { 1071 struct { 1072 /** sdio_slc1_rx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; 1073 * reserved 1074 */ 1075 uint32_t sdio_slc1_rx_sharemem_start_addr:32; 1076 }; 1077 uint32_t val; 1078 } sdio_slc1_rx_sharemem_start_reg_t; 1079 1080 /** Type of slc1_rx_sharemem_end register 1081 * reserved 1082 */ 1083 typedef union { 1084 struct { 1085 /** sdio_slc1_rx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; 1086 * reserved 1087 */ 1088 uint32_t sdio_slc1_rx_sharemem_end_addr:32; 1089 }; 1090 uint32_t val; 1091 } sdio_slc1_rx_sharemem_end_reg_t; 1092 1093 /** Type of hda_tx_sharemem_start register 1094 * reserved 1095 */ 1096 typedef union { 1097 struct { 1098 /** sdio_hda_tx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; 1099 * reserved 1100 */ 1101 uint32_t sdio_hda_tx_sharemem_start_addr:32; 1102 }; 1103 uint32_t val; 1104 } sdio_hda_tx_sharemem_start_reg_t; 1105 1106 /** Type of hda_rx_sharemem_start register 1107 * reserved 1108 */ 1109 typedef union { 1110 struct { 1111 /** sdio_hda_rx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; 1112 * reserved 1113 */ 1114 uint32_t sdio_hda_rx_sharemem_start_addr:32; 1115 }; 1116 uint32_t val; 1117 } sdio_hda_rx_sharemem_start_reg_t; 1118 1119 /** Type of slc_burst_len register 1120 * reserved 1121 */ 1122 typedef union { 1123 struct { 1124 /** slc0_txdata_burst_len : R/W; bitpos: [0]; default: 1; 1125 * 0-incr4,1-incr8 1126 */ 1127 uint32_t slc0_txdata_burst_len:1; 1128 /** slc0_rxdata_burst_len : R/W; bitpos: [1]; default: 1; 1129 * 0-incr4,1-incr8 1130 */ 1131 uint32_t slc0_rxdata_burst_len:1; 1132 /** slc1_txdata_burst_len : R/W; bitpos: [2]; default: 1; 1133 * 0-incr4,1-incr8 1134 */ 1135 uint32_t slc1_txdata_burst_len:1; 1136 /** slc1_rxdata_burst_len : R/W; bitpos: [3]; default: 1; 1137 * 0-incr4,1-incr8 1138 */ 1139 uint32_t slc1_rxdata_burst_len:1; 1140 uint32_t reserved_4:28; 1141 }; 1142 uint32_t val; 1143 } sdio_slc_burst_len_reg_t; 1144 1145 /** Type of slcid register 1146 * ******* Description *********** 1147 */ 1148 typedef union { 1149 struct { 1150 /** slc_id : R/W; bitpos: [31:0]; default: 256; 1151 * reserved 1152 */ 1153 uint32_t slc_id:32; 1154 }; 1155 uint32_t val; 1156 } sdio_slcid_reg_t; 1157 1158 1159 /** Group: Interrupt registers */ 1160 /** Type of slc0int_raw register 1161 * ******* Description *********** 1162 */ 1163 typedef union { 1164 struct { 1165 /** slc_frhost_bit0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; 1166 * reserved 1167 */ 1168 uint32_t slc_frhost_bit0_int_raw:1; 1169 /** slc_frhost_bit1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; 1170 * reserved 1171 */ 1172 uint32_t slc_frhost_bit1_int_raw:1; 1173 /** slc_frhost_bit2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; 1174 * reserved 1175 */ 1176 uint32_t slc_frhost_bit2_int_raw:1; 1177 /** slc_frhost_bit3_int_raw : R/WTC/SS; bitpos: [3]; default: 0; 1178 * reserved 1179 */ 1180 uint32_t slc_frhost_bit3_int_raw:1; 1181 /** slc_frhost_bit4_int_raw : R/WTC/SS; bitpos: [4]; default: 0; 1182 * reserved 1183 */ 1184 uint32_t slc_frhost_bit4_int_raw:1; 1185 /** slc_frhost_bit5_int_raw : R/WTC/SS; bitpos: [5]; default: 0; 1186 * reserved 1187 */ 1188 uint32_t slc_frhost_bit5_int_raw:1; 1189 /** slc_frhost_bit6_int_raw : R/WTC/SS; bitpos: [6]; default: 0; 1190 * reserved 1191 */ 1192 uint32_t slc_frhost_bit6_int_raw:1; 1193 /** slc_frhost_bit7_int_raw : R/WTC/SS; bitpos: [7]; default: 0; 1194 * reserved 1195 */ 1196 uint32_t slc_frhost_bit7_int_raw:1; 1197 /** slc0_rx_start_int_raw : R/WTC/SS; bitpos: [8]; default: 0; 1198 * reserved 1199 */ 1200 uint32_t slc0_rx_start_int_raw:1; 1201 /** slc0_tx_start_int_raw : R/WTC/SS; bitpos: [9]; default: 0; 1202 * reserved 1203 */ 1204 uint32_t slc0_tx_start_int_raw:1; 1205 /** slc0_rx_udf_int_raw : R/WTC/SS; bitpos: [10]; default: 0; 1206 * reserved 1207 */ 1208 uint32_t slc0_rx_udf_int_raw:1; 1209 /** slc0_tx_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0; 1210 * reserved 1211 */ 1212 uint32_t slc0_tx_ovf_int_raw:1; 1213 /** slc0_token0_1to0_int_raw : R/WTC/SS; bitpos: [12]; default: 0; 1214 * reserved 1215 */ 1216 uint32_t slc0_token0_1to0_int_raw:1; 1217 /** slc0_token1_1to0_int_raw : R/WTC/SS; bitpos: [13]; default: 0; 1218 * reserved 1219 */ 1220 uint32_t slc0_token1_1to0_int_raw:1; 1221 /** slc0_tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0; 1222 * The raw interrupt bit of slc0 finishing receiving data to one buffer 1223 */ 1224 uint32_t slc0_tx_done_int_raw:1; 1225 /** slc0_tx_suc_eof_int_raw : R/WTC/SS; bitpos: [15]; default: 0; 1226 * The raw interrupt bit of slc0 finishing receiving data 1227 */ 1228 uint32_t slc0_tx_suc_eof_int_raw:1; 1229 /** slc0_rx_done_int_raw : R/WTC/SS; bitpos: [16]; default: 0; 1230 * The raw interrupt bit of slc0 finishing sending data from one buffer 1231 */ 1232 uint32_t slc0_rx_done_int_raw:1; 1233 /** slc0_rx_eof_int_raw : R/WTC/SS; bitpos: [17]; default: 0; 1234 * The raw interrupt bit of slc0 finishing sending data 1235 */ 1236 uint32_t slc0_rx_eof_int_raw:1; 1237 /** slc0_tohost_int_raw : R/WTC/SS; bitpos: [18]; default: 0; 1238 * reserved 1239 */ 1240 uint32_t slc0_tohost_int_raw:1; 1241 /** slc0_tx_dscr_err_int_raw : R/WTC/SS; bitpos: [19]; default: 0; 1242 * The raw interrupt bit of slc0 tx link descriptor error 1243 */ 1244 uint32_t slc0_tx_dscr_err_int_raw:1; 1245 /** slc0_rx_dscr_err_int_raw : R/WTC/SS; bitpos: [20]; default: 0; 1246 * The raw interrupt bit of slc0 rx link descriptor error 1247 */ 1248 uint32_t slc0_rx_dscr_err_int_raw:1; 1249 /** slc0_tx_dscr_empty_int_raw : R/WTC/SS; bitpos: [21]; default: 0; 1250 * reserved 1251 */ 1252 uint32_t slc0_tx_dscr_empty_int_raw:1; 1253 /** slc0_host_rd_ack_int_raw : R/WTC/SS; bitpos: [22]; default: 0; 1254 * reserved 1255 */ 1256 uint32_t slc0_host_rd_ack_int_raw:1; 1257 /** slc0_wr_retry_done_int_raw : R/WTC/SS; bitpos: [23]; default: 0; 1258 * reserved 1259 */ 1260 uint32_t slc0_wr_retry_done_int_raw:1; 1261 /** slc0_tx_err_eof_int_raw : R/WTC/SS; bitpos: [24]; default: 0; 1262 * reserved 1263 */ 1264 uint32_t slc0_tx_err_eof_int_raw:1; 1265 /** cmd_dtc_int_raw : R/WTC/SS; bitpos: [25]; default: 0; 1266 * reserved 1267 */ 1268 uint32_t cmd_dtc_int_raw:1; 1269 /** slc0_rx_quick_eof_int_raw : R/WTC/SS; bitpos: [26]; default: 0; 1270 * reserved 1271 */ 1272 uint32_t slc0_rx_quick_eof_int_raw:1; 1273 /** slc0_host_pop_eof_err_int_raw : R/WTC/SS; bitpos: [27]; default: 0; 1274 * reserved 1275 */ 1276 uint32_t slc0_host_pop_eof_err_int_raw:1; 1277 /** hda_recv_done_int_raw : R/WTC/SS; bitpos: [28]; default: 0; 1278 * reserved 1279 */ 1280 uint32_t hda_recv_done_int_raw:1; 1281 uint32_t reserved_29:3; 1282 }; 1283 uint32_t val; 1284 } sdio_slc0int_raw_reg_t; 1285 1286 /** Type of slc0int_st register 1287 * ******* Description *********** 1288 */ 1289 typedef union { 1290 struct { 1291 /** slc_frhost_bit0_int_st : RO; bitpos: [0]; default: 0; 1292 * reserved 1293 */ 1294 uint32_t slc_frhost_bit0_int_st:1; 1295 /** slc_frhost_bit1_int_st : RO; bitpos: [1]; default: 0; 1296 * reserved 1297 */ 1298 uint32_t slc_frhost_bit1_int_st:1; 1299 /** slc_frhost_bit2_int_st : RO; bitpos: [2]; default: 0; 1300 * reserved 1301 */ 1302 uint32_t slc_frhost_bit2_int_st:1; 1303 /** slc_frhost_bit3_int_st : RO; bitpos: [3]; default: 0; 1304 * reserved 1305 */ 1306 uint32_t slc_frhost_bit3_int_st:1; 1307 /** slc_frhost_bit4_int_st : RO; bitpos: [4]; default: 0; 1308 * reserved 1309 */ 1310 uint32_t slc_frhost_bit4_int_st:1; 1311 /** slc_frhost_bit5_int_st : RO; bitpos: [5]; default: 0; 1312 * reserved 1313 */ 1314 uint32_t slc_frhost_bit5_int_st:1; 1315 /** slc_frhost_bit6_int_st : RO; bitpos: [6]; default: 0; 1316 * reserved 1317 */ 1318 uint32_t slc_frhost_bit6_int_st:1; 1319 /** slc_frhost_bit7_int_st : RO; bitpos: [7]; default: 0; 1320 * reserved 1321 */ 1322 uint32_t slc_frhost_bit7_int_st:1; 1323 /** slc0_rx_start_int_st : RO; bitpos: [8]; default: 0; 1324 * reserved 1325 */ 1326 uint32_t slc0_rx_start_int_st:1; 1327 /** slc0_tx_start_int_st : RO; bitpos: [9]; default: 0; 1328 * reserved 1329 */ 1330 uint32_t slc0_tx_start_int_st:1; 1331 /** slc0_rx_udf_int_st : RO; bitpos: [10]; default: 0; 1332 * reserved 1333 */ 1334 uint32_t slc0_rx_udf_int_st:1; 1335 /** slc0_tx_ovf_int_st : RO; bitpos: [11]; default: 0; 1336 * reserved 1337 */ 1338 uint32_t slc0_tx_ovf_int_st:1; 1339 /** slc0_token0_1to0_int_st : RO; bitpos: [12]; default: 0; 1340 * reserved 1341 */ 1342 uint32_t slc0_token0_1to0_int_st:1; 1343 /** slc0_token1_1to0_int_st : RO; bitpos: [13]; default: 0; 1344 * reserved 1345 */ 1346 uint32_t slc0_token1_1to0_int_st:1; 1347 /** slc0_tx_done_int_st : RO; bitpos: [14]; default: 0; 1348 * reserved 1349 */ 1350 uint32_t slc0_tx_done_int_st:1; 1351 /** slc0_tx_suc_eof_int_st : RO; bitpos: [15]; default: 0; 1352 * reserved 1353 */ 1354 uint32_t slc0_tx_suc_eof_int_st:1; 1355 /** slc0_rx_done_int_st : RO; bitpos: [16]; default: 0; 1356 * reserved 1357 */ 1358 uint32_t slc0_rx_done_int_st:1; 1359 /** slc0_rx_eof_int_st : RO; bitpos: [17]; default: 0; 1360 * reserved 1361 */ 1362 uint32_t slc0_rx_eof_int_st:1; 1363 /** slc0_tohost_int_st : RO; bitpos: [18]; default: 0; 1364 * reserved 1365 */ 1366 uint32_t slc0_tohost_int_st:1; 1367 /** slc0_tx_dscr_err_int_st : RO; bitpos: [19]; default: 0; 1368 * reserved 1369 */ 1370 uint32_t slc0_tx_dscr_err_int_st:1; 1371 /** slc0_rx_dscr_err_int_st : RO; bitpos: [20]; default: 0; 1372 * reserved 1373 */ 1374 uint32_t slc0_rx_dscr_err_int_st:1; 1375 /** slc0_tx_dscr_empty_int_st : RO; bitpos: [21]; default: 0; 1376 * reserved 1377 */ 1378 uint32_t slc0_tx_dscr_empty_int_st:1; 1379 /** slc0_host_rd_ack_int_st : RO; bitpos: [22]; default: 0; 1380 * reserved 1381 */ 1382 uint32_t slc0_host_rd_ack_int_st:1; 1383 /** slc0_wr_retry_done_int_st : RO; bitpos: [23]; default: 0; 1384 * reserved 1385 */ 1386 uint32_t slc0_wr_retry_done_int_st:1; 1387 /** slc0_tx_err_eof_int_st : RO; bitpos: [24]; default: 0; 1388 * reserved 1389 */ 1390 uint32_t slc0_tx_err_eof_int_st:1; 1391 /** cmd_dtc_int_st : RO; bitpos: [25]; default: 0; 1392 * reserved 1393 */ 1394 uint32_t cmd_dtc_int_st:1; 1395 /** slc0_rx_quick_eof_int_st : RO; bitpos: [26]; default: 0; 1396 * reserved 1397 */ 1398 uint32_t slc0_rx_quick_eof_int_st:1; 1399 /** slc0_host_pop_eof_err_int_st : RO; bitpos: [27]; default: 0; 1400 * reserved 1401 */ 1402 uint32_t slc0_host_pop_eof_err_int_st:1; 1403 /** hda_recv_done_int_st : RO; bitpos: [28]; default: 0; 1404 * reserved 1405 */ 1406 uint32_t hda_recv_done_int_st:1; 1407 uint32_t reserved_29:3; 1408 }; 1409 uint32_t val; 1410 } sdio_slc0int_st_reg_t; 1411 1412 /** Type of slc0int_ena register 1413 * ******* Description *********** 1414 */ 1415 typedef union { 1416 struct { 1417 /** slc_frhost_bit0_int_ena : R/W; bitpos: [0]; default: 0; 1418 * reserved 1419 */ 1420 uint32_t slc_frhost_bit0_int_ena:1; 1421 /** slc_frhost_bit1_int_ena : R/W; bitpos: [1]; default: 0; 1422 * reserved 1423 */ 1424 uint32_t slc_frhost_bit1_int_ena:1; 1425 /** slc_frhost_bit2_int_ena : R/W; bitpos: [2]; default: 0; 1426 * reserved 1427 */ 1428 uint32_t slc_frhost_bit2_int_ena:1; 1429 /** slc_frhost_bit3_int_ena : R/W; bitpos: [3]; default: 0; 1430 * reserved 1431 */ 1432 uint32_t slc_frhost_bit3_int_ena:1; 1433 /** slc_frhost_bit4_int_ena : R/W; bitpos: [4]; default: 0; 1434 * reserved 1435 */ 1436 uint32_t slc_frhost_bit4_int_ena:1; 1437 /** slc_frhost_bit5_int_ena : R/W; bitpos: [5]; default: 0; 1438 * reserved 1439 */ 1440 uint32_t slc_frhost_bit5_int_ena:1; 1441 /** slc_frhost_bit6_int_ena : R/W; bitpos: [6]; default: 0; 1442 * reserved 1443 */ 1444 uint32_t slc_frhost_bit6_int_ena:1; 1445 /** slc_frhost_bit7_int_ena : R/W; bitpos: [7]; default: 0; 1446 * reserved 1447 */ 1448 uint32_t slc_frhost_bit7_int_ena:1; 1449 /** slc0_rx_start_int_ena : R/W; bitpos: [8]; default: 0; 1450 * reserved 1451 */ 1452 uint32_t slc0_rx_start_int_ena:1; 1453 /** slc0_tx_start_int_ena : R/W; bitpos: [9]; default: 0; 1454 * reserved 1455 */ 1456 uint32_t slc0_tx_start_int_ena:1; 1457 /** slc0_rx_udf_int_ena : R/W; bitpos: [10]; default: 0; 1458 * reserved 1459 */ 1460 uint32_t slc0_rx_udf_int_ena:1; 1461 /** slc0_tx_ovf_int_ena : R/W; bitpos: [11]; default: 0; 1462 * reserved 1463 */ 1464 uint32_t slc0_tx_ovf_int_ena:1; 1465 /** slc0_token0_1to0_int_ena : R/W; bitpos: [12]; default: 0; 1466 * reserved 1467 */ 1468 uint32_t slc0_token0_1to0_int_ena:1; 1469 /** slc0_token1_1to0_int_ena : R/W; bitpos: [13]; default: 0; 1470 * reserved 1471 */ 1472 uint32_t slc0_token1_1to0_int_ena:1; 1473 /** slc0_tx_done_int_ena : R/W; bitpos: [14]; default: 0; 1474 * reserved 1475 */ 1476 uint32_t slc0_tx_done_int_ena:1; 1477 /** slc0_tx_suc_eof_int_ena : R/W; bitpos: [15]; default: 0; 1478 * reserved 1479 */ 1480 uint32_t slc0_tx_suc_eof_int_ena:1; 1481 /** slc0_rx_done_int_ena : R/W; bitpos: [16]; default: 0; 1482 * reserved 1483 */ 1484 uint32_t slc0_rx_done_int_ena:1; 1485 /** slc0_rx_eof_int_ena : R/W; bitpos: [17]; default: 0; 1486 * reserved 1487 */ 1488 uint32_t slc0_rx_eof_int_ena:1; 1489 /** slc0_tohost_int_ena : R/W; bitpos: [18]; default: 0; 1490 * reserved 1491 */ 1492 uint32_t slc0_tohost_int_ena:1; 1493 /** slc0_tx_dscr_err_int_ena : R/W; bitpos: [19]; default: 0; 1494 * reserved 1495 */ 1496 uint32_t slc0_tx_dscr_err_int_ena:1; 1497 /** slc0_rx_dscr_err_int_ena : R/W; bitpos: [20]; default: 0; 1498 * reserved 1499 */ 1500 uint32_t slc0_rx_dscr_err_int_ena:1; 1501 /** slc0_tx_dscr_empty_int_ena : R/W; bitpos: [21]; default: 0; 1502 * reserved 1503 */ 1504 uint32_t slc0_tx_dscr_empty_int_ena:1; 1505 /** slc0_host_rd_ack_int_ena : R/W; bitpos: [22]; default: 0; 1506 * reserved 1507 */ 1508 uint32_t slc0_host_rd_ack_int_ena:1; 1509 /** slc0_wr_retry_done_int_ena : R/W; bitpos: [23]; default: 0; 1510 * reserved 1511 */ 1512 uint32_t slc0_wr_retry_done_int_ena:1; 1513 /** slc0_tx_err_eof_int_ena : R/W; bitpos: [24]; default: 0; 1514 * reserved 1515 */ 1516 uint32_t slc0_tx_err_eof_int_ena:1; 1517 /** cmd_dtc_int_ena : R/W; bitpos: [25]; default: 0; 1518 * reserved 1519 */ 1520 uint32_t cmd_dtc_int_ena:1; 1521 /** slc0_rx_quick_eof_int_ena : R/W; bitpos: [26]; default: 0; 1522 * reserved 1523 */ 1524 uint32_t slc0_rx_quick_eof_int_ena:1; 1525 /** slc0_host_pop_eof_err_int_ena : R/W; bitpos: [27]; default: 0; 1526 * reserved 1527 */ 1528 uint32_t slc0_host_pop_eof_err_int_ena:1; 1529 /** hda_recv_done_int_ena : R/W; bitpos: [28]; default: 0; 1530 * reserved 1531 */ 1532 uint32_t hda_recv_done_int_ena:1; 1533 uint32_t reserved_29:3; 1534 }; 1535 uint32_t val; 1536 } sdio_slc0int_ena_reg_t; 1537 1538 /** Type of slc0int_clr register 1539 * ******* Description *********** 1540 */ 1541 typedef union { 1542 struct { 1543 /** slc_frhost_bit0_int_clr : WT; bitpos: [0]; default: 0; 1544 * reserved 1545 */ 1546 uint32_t slc_frhost_bit0_int_clr:1; 1547 /** slc_frhost_bit1_int_clr : WT; bitpos: [1]; default: 0; 1548 * reserved 1549 */ 1550 uint32_t slc_frhost_bit1_int_clr:1; 1551 /** slc_frhost_bit2_int_clr : WT; bitpos: [2]; default: 0; 1552 * reserved 1553 */ 1554 uint32_t slc_frhost_bit2_int_clr:1; 1555 /** slc_frhost_bit3_int_clr : WT; bitpos: [3]; default: 0; 1556 * reserved 1557 */ 1558 uint32_t slc_frhost_bit3_int_clr:1; 1559 /** slc_frhost_bit4_int_clr : WT; bitpos: [4]; default: 0; 1560 * reserved 1561 */ 1562 uint32_t slc_frhost_bit4_int_clr:1; 1563 /** slc_frhost_bit5_int_clr : WT; bitpos: [5]; default: 0; 1564 * reserved 1565 */ 1566 uint32_t slc_frhost_bit5_int_clr:1; 1567 /** slc_frhost_bit6_int_clr : WT; bitpos: [6]; default: 0; 1568 * reserved 1569 */ 1570 uint32_t slc_frhost_bit6_int_clr:1; 1571 /** slc_frhost_bit7_int_clr : WT; bitpos: [7]; default: 0; 1572 * reserved 1573 */ 1574 uint32_t slc_frhost_bit7_int_clr:1; 1575 /** slc0_rx_start_int_clr : WT; bitpos: [8]; default: 0; 1576 * reserved 1577 */ 1578 uint32_t slc0_rx_start_int_clr:1; 1579 /** slc0_tx_start_int_clr : WT; bitpos: [9]; default: 0; 1580 * reserved 1581 */ 1582 uint32_t slc0_tx_start_int_clr:1; 1583 /** slc0_rx_udf_int_clr : WT; bitpos: [10]; default: 0; 1584 * reserved 1585 */ 1586 uint32_t slc0_rx_udf_int_clr:1; 1587 /** slc0_tx_ovf_int_clr : WT; bitpos: [11]; default: 0; 1588 * reserved 1589 */ 1590 uint32_t slc0_tx_ovf_int_clr:1; 1591 /** slc0_token0_1to0_int_clr : WT; bitpos: [12]; default: 0; 1592 * reserved 1593 */ 1594 uint32_t slc0_token0_1to0_int_clr:1; 1595 /** slc0_token1_1to0_int_clr : WT; bitpos: [13]; default: 0; 1596 * reserved 1597 */ 1598 uint32_t slc0_token1_1to0_int_clr:1; 1599 /** slc0_tx_done_int_clr : WT; bitpos: [14]; default: 0; 1600 * reserved 1601 */ 1602 uint32_t slc0_tx_done_int_clr:1; 1603 /** slc0_tx_suc_eof_int_clr : WT; bitpos: [15]; default: 0; 1604 * reserved 1605 */ 1606 uint32_t slc0_tx_suc_eof_int_clr:1; 1607 /** slc0_rx_done_int_clr : WT; bitpos: [16]; default: 0; 1608 * reserved 1609 */ 1610 uint32_t slc0_rx_done_int_clr:1; 1611 /** slc0_rx_eof_int_clr : WT; bitpos: [17]; default: 0; 1612 * reserved 1613 */ 1614 uint32_t slc0_rx_eof_int_clr:1; 1615 /** slc0_tohost_int_clr : WT; bitpos: [18]; default: 0; 1616 * reserved 1617 */ 1618 uint32_t slc0_tohost_int_clr:1; 1619 /** slc0_tx_dscr_err_int_clr : WT; bitpos: [19]; default: 0; 1620 * reserved 1621 */ 1622 uint32_t slc0_tx_dscr_err_int_clr:1; 1623 /** slc0_rx_dscr_err_int_clr : WT; bitpos: [20]; default: 0; 1624 * reserved 1625 */ 1626 uint32_t slc0_rx_dscr_err_int_clr:1; 1627 /** slc0_tx_dscr_empty_int_clr : WT; bitpos: [21]; default: 0; 1628 * reserved 1629 */ 1630 uint32_t slc0_tx_dscr_empty_int_clr:1; 1631 /** slc0_host_rd_ack_int_clr : WT; bitpos: [22]; default: 0; 1632 * reserved 1633 */ 1634 uint32_t slc0_host_rd_ack_int_clr:1; 1635 /** slc0_wr_retry_done_int_clr : WT; bitpos: [23]; default: 0; 1636 * reserved 1637 */ 1638 uint32_t slc0_wr_retry_done_int_clr:1; 1639 /** slc0_tx_err_eof_int_clr : WT; bitpos: [24]; default: 0; 1640 * reserved 1641 */ 1642 uint32_t slc0_tx_err_eof_int_clr:1; 1643 /** cmd_dtc_int_clr : WT; bitpos: [25]; default: 0; 1644 * reserved 1645 */ 1646 uint32_t cmd_dtc_int_clr:1; 1647 /** slc0_rx_quick_eof_int_clr : WT; bitpos: [26]; default: 0; 1648 * reserved 1649 */ 1650 uint32_t slc0_rx_quick_eof_int_clr:1; 1651 /** slc0_host_pop_eof_err_int_clr : WT; bitpos: [27]; default: 0; 1652 * reserved 1653 */ 1654 uint32_t slc0_host_pop_eof_err_int_clr:1; 1655 /** hda_recv_done_int_clr : WT; bitpos: [28]; default: 0; 1656 * reserved 1657 */ 1658 uint32_t hda_recv_done_int_clr:1; 1659 uint32_t reserved_29:3; 1660 }; 1661 uint32_t val; 1662 } sdio_slc0int_clr_reg_t; 1663 1664 /** Type of slc1int_raw register 1665 * reserved 1666 */ 1667 typedef union { 1668 struct { 1669 /** slc_frhost_bit8_int_raw : R/WTC/SS; bitpos: [0]; default: 0; 1670 * reserved 1671 */ 1672 uint32_t slc_frhost_bit8_int_raw:1; 1673 /** slc_frhost_bit9_int_raw : R/WTC/SS; bitpos: [1]; default: 0; 1674 * reserved 1675 */ 1676 uint32_t slc_frhost_bit9_int_raw:1; 1677 /** slc_frhost_bit10_int_raw : R/WTC/SS; bitpos: [2]; default: 0; 1678 * reserved 1679 */ 1680 uint32_t slc_frhost_bit10_int_raw:1; 1681 /** slc_frhost_bit11_int_raw : R/WTC/SS; bitpos: [3]; default: 0; 1682 * reserved 1683 */ 1684 uint32_t slc_frhost_bit11_int_raw:1; 1685 /** slc_frhost_bit12_int_raw : R/WTC/SS; bitpos: [4]; default: 0; 1686 * reserved 1687 */ 1688 uint32_t slc_frhost_bit12_int_raw:1; 1689 /** slc_frhost_bit13_int_raw : R/WTC/SS; bitpos: [5]; default: 0; 1690 * reserved 1691 */ 1692 uint32_t slc_frhost_bit13_int_raw:1; 1693 /** slc_frhost_bit14_int_raw : R/WTC/SS; bitpos: [6]; default: 0; 1694 * reserved 1695 */ 1696 uint32_t slc_frhost_bit14_int_raw:1; 1697 /** slc_frhost_bit15_int_raw : R/WTC/SS; bitpos: [7]; default: 0; 1698 * reserved 1699 */ 1700 uint32_t slc_frhost_bit15_int_raw:1; 1701 /** slc1_rx_start_int_raw : R/WTC/SS; bitpos: [8]; default: 0; 1702 * reserved 1703 */ 1704 uint32_t slc1_rx_start_int_raw:1; 1705 /** slc1_tx_start_int_raw : R/WTC/SS; bitpos: [9]; default: 0; 1706 * reserved 1707 */ 1708 uint32_t slc1_tx_start_int_raw:1; 1709 /** slc1_rx_udf_int_raw : R/WTC/SS; bitpos: [10]; default: 0; 1710 * reserved 1711 */ 1712 uint32_t slc1_rx_udf_int_raw:1; 1713 /** slc1_tx_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0; 1714 * reserved 1715 */ 1716 uint32_t slc1_tx_ovf_int_raw:1; 1717 /** slc1_token0_1to0_int_raw : R/WTC/SS; bitpos: [12]; default: 0; 1718 * reserved 1719 */ 1720 uint32_t slc1_token0_1to0_int_raw:1; 1721 /** slc1_token1_1to0_int_raw : R/WTC/SS; bitpos: [13]; default: 0; 1722 * reserved 1723 */ 1724 uint32_t slc1_token1_1to0_int_raw:1; 1725 /** slc1_tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0; 1726 * reserved 1727 */ 1728 uint32_t slc1_tx_done_int_raw:1; 1729 /** slc1_tx_suc_eof_int_raw : R/WTC/SS; bitpos: [15]; default: 0; 1730 * reserved 1731 */ 1732 uint32_t slc1_tx_suc_eof_int_raw:1; 1733 /** slc1_rx_done_int_raw : R/WTC/SS; bitpos: [16]; default: 0; 1734 * reserved 1735 */ 1736 uint32_t slc1_rx_done_int_raw:1; 1737 /** slc1_rx_eof_int_raw : R/WTC/SS; bitpos: [17]; default: 0; 1738 * reserved 1739 */ 1740 uint32_t slc1_rx_eof_int_raw:1; 1741 /** slc1_tohost_int_raw : R/WTC/SS; bitpos: [18]; default: 0; 1742 * reserved 1743 */ 1744 uint32_t slc1_tohost_int_raw:1; 1745 /** slc1_tx_dscr_err_int_raw : R/WTC/SS; bitpos: [19]; default: 0; 1746 * reserved 1747 */ 1748 uint32_t slc1_tx_dscr_err_int_raw:1; 1749 /** slc1_rx_dscr_err_int_raw : R/WTC/SS; bitpos: [20]; default: 0; 1750 * reserved 1751 */ 1752 uint32_t slc1_rx_dscr_err_int_raw:1; 1753 /** slc1_tx_dscr_empty_int_raw : R/WTC/SS; bitpos: [21]; default: 0; 1754 * reserved 1755 */ 1756 uint32_t slc1_tx_dscr_empty_int_raw:1; 1757 /** slc1_host_rd_ack_int_raw : R/WTC/SS; bitpos: [22]; default: 0; 1758 * reserved 1759 */ 1760 uint32_t slc1_host_rd_ack_int_raw:1; 1761 /** slc1_wr_retry_done_int_raw : R/WTC/SS; bitpos: [23]; default: 0; 1762 * reserved 1763 */ 1764 uint32_t slc1_wr_retry_done_int_raw:1; 1765 /** slc1_tx_err_eof_int_raw : R/WTC/SS; bitpos: [24]; default: 0; 1766 * reserved 1767 */ 1768 uint32_t slc1_tx_err_eof_int_raw:1; 1769 uint32_t reserved_25:7; 1770 }; 1771 uint32_t val; 1772 } sdio_slc1int_raw_reg_t; 1773 1774 /** Type of slc1int_st register 1775 * reserved 1776 */ 1777 typedef union { 1778 struct { 1779 /** slc_frhost_bit8_int_st : RO; bitpos: [0]; default: 0; 1780 * reserved 1781 */ 1782 uint32_t slc_frhost_bit8_int_st:1; 1783 /** slc_frhost_bit9_int_st : RO; bitpos: [1]; default: 0; 1784 * reserved 1785 */ 1786 uint32_t slc_frhost_bit9_int_st:1; 1787 /** slc_frhost_bit10_int_st : RO; bitpos: [2]; default: 0; 1788 * reserved 1789 */ 1790 uint32_t slc_frhost_bit10_int_st:1; 1791 /** slc_frhost_bit11_int_st : RO; bitpos: [3]; default: 0; 1792 * reserved 1793 */ 1794 uint32_t slc_frhost_bit11_int_st:1; 1795 /** slc_frhost_bit12_int_st : RO; bitpos: [4]; default: 0; 1796 * reserved 1797 */ 1798 uint32_t slc_frhost_bit12_int_st:1; 1799 /** slc_frhost_bit13_int_st : RO; bitpos: [5]; default: 0; 1800 * reserved 1801 */ 1802 uint32_t slc_frhost_bit13_int_st:1; 1803 /** slc_frhost_bit14_int_st : RO; bitpos: [6]; default: 0; 1804 * reserved 1805 */ 1806 uint32_t slc_frhost_bit14_int_st:1; 1807 /** slc_frhost_bit15_int_st : RO; bitpos: [7]; default: 0; 1808 * reserved 1809 */ 1810 uint32_t slc_frhost_bit15_int_st:1; 1811 /** slc1_rx_start_int_st : RO; bitpos: [8]; default: 0; 1812 * reserved 1813 */ 1814 uint32_t slc1_rx_start_int_st:1; 1815 /** slc1_tx_start_int_st : RO; bitpos: [9]; default: 0; 1816 * reserved 1817 */ 1818 uint32_t slc1_tx_start_int_st:1; 1819 /** slc1_rx_udf_int_st : RO; bitpos: [10]; default: 0; 1820 * reserved 1821 */ 1822 uint32_t slc1_rx_udf_int_st:1; 1823 /** slc1_tx_ovf_int_st : RO; bitpos: [11]; default: 0; 1824 * reserved 1825 */ 1826 uint32_t slc1_tx_ovf_int_st:1; 1827 /** slc1_token0_1to0_int_st : RO; bitpos: [12]; default: 0; 1828 * reserved 1829 */ 1830 uint32_t slc1_token0_1to0_int_st:1; 1831 /** slc1_token1_1to0_int_st : RO; bitpos: [13]; default: 0; 1832 * reserved 1833 */ 1834 uint32_t slc1_token1_1to0_int_st:1; 1835 /** slc1_tx_done_int_st : RO; bitpos: [14]; default: 0; 1836 * reserved 1837 */ 1838 uint32_t slc1_tx_done_int_st:1; 1839 /** slc1_tx_suc_eof_int_st : RO; bitpos: [15]; default: 0; 1840 * reserved 1841 */ 1842 uint32_t slc1_tx_suc_eof_int_st:1; 1843 /** slc1_rx_done_int_st : RO; bitpos: [16]; default: 0; 1844 * reserved 1845 */ 1846 uint32_t slc1_rx_done_int_st:1; 1847 /** slc1_rx_eof_int_st : RO; bitpos: [17]; default: 0; 1848 * reserved 1849 */ 1850 uint32_t slc1_rx_eof_int_st:1; 1851 /** slc1_tohost_int_st : RO; bitpos: [18]; default: 0; 1852 * reserved 1853 */ 1854 uint32_t slc1_tohost_int_st:1; 1855 /** slc1_tx_dscr_err_int_st : RO; bitpos: [19]; default: 0; 1856 * reserved 1857 */ 1858 uint32_t slc1_tx_dscr_err_int_st:1; 1859 /** slc1_rx_dscr_err_int_st : RO; bitpos: [20]; default: 0; 1860 * reserved 1861 */ 1862 uint32_t slc1_rx_dscr_err_int_st:1; 1863 /** slc1_tx_dscr_empty_int_st : RO; bitpos: [21]; default: 0; 1864 * reserved 1865 */ 1866 uint32_t slc1_tx_dscr_empty_int_st:1; 1867 /** slc1_host_rd_ack_int_st : RO; bitpos: [22]; default: 0; 1868 * reserved 1869 */ 1870 uint32_t slc1_host_rd_ack_int_st:1; 1871 /** slc1_wr_retry_done_int_st : RO; bitpos: [23]; default: 0; 1872 * reserved 1873 */ 1874 uint32_t slc1_wr_retry_done_int_st:1; 1875 /** slc1_tx_err_eof_int_st : RO; bitpos: [24]; default: 0; 1876 * reserved 1877 */ 1878 uint32_t slc1_tx_err_eof_int_st:1; 1879 uint32_t reserved_25:7; 1880 }; 1881 uint32_t val; 1882 } sdio_slc1int_st_reg_t; 1883 1884 /** Type of slc1int_ena register 1885 * reserved 1886 */ 1887 typedef union { 1888 struct { 1889 /** slc_frhost_bit8_int_ena : R/W; bitpos: [0]; default: 0; 1890 * reserved 1891 */ 1892 uint32_t slc_frhost_bit8_int_ena:1; 1893 /** slc_frhost_bit9_int_ena : R/W; bitpos: [1]; default: 0; 1894 * reserved 1895 */ 1896 uint32_t slc_frhost_bit9_int_ena:1; 1897 /** slc_frhost_bit10_int_ena : R/W; bitpos: [2]; default: 0; 1898 * reserved 1899 */ 1900 uint32_t slc_frhost_bit10_int_ena:1; 1901 /** slc_frhost_bit11_int_ena : R/W; bitpos: [3]; default: 0; 1902 * reserved 1903 */ 1904 uint32_t slc_frhost_bit11_int_ena:1; 1905 /** slc_frhost_bit12_int_ena : R/W; bitpos: [4]; default: 0; 1906 * reserved 1907 */ 1908 uint32_t slc_frhost_bit12_int_ena:1; 1909 /** slc_frhost_bit13_int_ena : R/W; bitpos: [5]; default: 0; 1910 * reserved 1911 */ 1912 uint32_t slc_frhost_bit13_int_ena:1; 1913 /** slc_frhost_bit14_int_ena : R/W; bitpos: [6]; default: 0; 1914 * reserved 1915 */ 1916 uint32_t slc_frhost_bit14_int_ena:1; 1917 /** slc_frhost_bit15_int_ena : R/W; bitpos: [7]; default: 0; 1918 * reserved 1919 */ 1920 uint32_t slc_frhost_bit15_int_ena:1; 1921 /** slc1_rx_start_int_ena : R/W; bitpos: [8]; default: 0; 1922 * reserved 1923 */ 1924 uint32_t slc1_rx_start_int_ena:1; 1925 /** slc1_tx_start_int_ena : R/W; bitpos: [9]; default: 0; 1926 * reserved 1927 */ 1928 uint32_t slc1_tx_start_int_ena:1; 1929 /** slc1_rx_udf_int_ena : R/W; bitpos: [10]; default: 0; 1930 * reserved 1931 */ 1932 uint32_t slc1_rx_udf_int_ena:1; 1933 /** slc1_tx_ovf_int_ena : R/W; bitpos: [11]; default: 0; 1934 * reserved 1935 */ 1936 uint32_t slc1_tx_ovf_int_ena:1; 1937 /** slc1_token0_1to0_int_ena : R/W; bitpos: [12]; default: 0; 1938 * reserved 1939 */ 1940 uint32_t slc1_token0_1to0_int_ena:1; 1941 /** slc1_token1_1to0_int_ena : R/W; bitpos: [13]; default: 0; 1942 * reserved 1943 */ 1944 uint32_t slc1_token1_1to0_int_ena:1; 1945 /** slc1_tx_done_int_ena : R/W; bitpos: [14]; default: 0; 1946 * reserved 1947 */ 1948 uint32_t slc1_tx_done_int_ena:1; 1949 /** slc1_tx_suc_eof_int_ena : R/W; bitpos: [15]; default: 0; 1950 * reserved 1951 */ 1952 uint32_t slc1_tx_suc_eof_int_ena:1; 1953 /** slc1_rx_done_int_ena : R/W; bitpos: [16]; default: 0; 1954 * reserved 1955 */ 1956 uint32_t slc1_rx_done_int_ena:1; 1957 /** slc1_rx_eof_int_ena : R/W; bitpos: [17]; default: 0; 1958 * reserved 1959 */ 1960 uint32_t slc1_rx_eof_int_ena:1; 1961 /** slc1_tohost_int_ena : R/W; bitpos: [18]; default: 0; 1962 * reserved 1963 */ 1964 uint32_t slc1_tohost_int_ena:1; 1965 /** slc1_tx_dscr_err_int_ena : R/W; bitpos: [19]; default: 0; 1966 * reserved 1967 */ 1968 uint32_t slc1_tx_dscr_err_int_ena:1; 1969 /** slc1_rx_dscr_err_int_ena : R/W; bitpos: [20]; default: 0; 1970 * reserved 1971 */ 1972 uint32_t slc1_rx_dscr_err_int_ena:1; 1973 /** slc1_tx_dscr_empty_int_ena : R/W; bitpos: [21]; default: 0; 1974 * reserved 1975 */ 1976 uint32_t slc1_tx_dscr_empty_int_ena:1; 1977 /** slc1_host_rd_ack_int_ena : R/W; bitpos: [22]; default: 0; 1978 * reserved 1979 */ 1980 uint32_t slc1_host_rd_ack_int_ena:1; 1981 /** slc1_wr_retry_done_int_ena : R/W; bitpos: [23]; default: 0; 1982 * reserved 1983 */ 1984 uint32_t slc1_wr_retry_done_int_ena:1; 1985 /** slc1_tx_err_eof_int_ena : R/W; bitpos: [24]; default: 0; 1986 * reserved 1987 */ 1988 uint32_t slc1_tx_err_eof_int_ena:1; 1989 uint32_t reserved_25:7; 1990 }; 1991 uint32_t val; 1992 } sdio_slc1int_ena_reg_t; 1993 1994 /** Type of slc1int_clr register 1995 * reserved 1996 */ 1997 typedef union { 1998 struct { 1999 /** slc_frhost_bit8_int_clr : WT; bitpos: [0]; default: 0; 2000 * reserved 2001 */ 2002 uint32_t slc_frhost_bit8_int_clr:1; 2003 /** slc_frhost_bit9_int_clr : WT; bitpos: [1]; default: 0; 2004 * reserved 2005 */ 2006 uint32_t slc_frhost_bit9_int_clr:1; 2007 /** slc_frhost_bit10_int_clr : WT; bitpos: [2]; default: 0; 2008 * reserved 2009 */ 2010 uint32_t slc_frhost_bit10_int_clr:1; 2011 /** slc_frhost_bit11_int_clr : WT; bitpos: [3]; default: 0; 2012 * reserved 2013 */ 2014 uint32_t slc_frhost_bit11_int_clr:1; 2015 /** slc_frhost_bit12_int_clr : WT; bitpos: [4]; default: 0; 2016 * reserved 2017 */ 2018 uint32_t slc_frhost_bit12_int_clr:1; 2019 /** slc_frhost_bit13_int_clr : WT; bitpos: [5]; default: 0; 2020 * reserved 2021 */ 2022 uint32_t slc_frhost_bit13_int_clr:1; 2023 /** slc_frhost_bit14_int_clr : WT; bitpos: [6]; default: 0; 2024 * reserved 2025 */ 2026 uint32_t slc_frhost_bit14_int_clr:1; 2027 /** slc_frhost_bit15_int_clr : WT; bitpos: [7]; default: 0; 2028 * reserved 2029 */ 2030 uint32_t slc_frhost_bit15_int_clr:1; 2031 /** slc1_rx_start_int_clr : WT; bitpos: [8]; default: 0; 2032 * reserved 2033 */ 2034 uint32_t slc1_rx_start_int_clr:1; 2035 /** slc1_tx_start_int_clr : WT; bitpos: [9]; default: 0; 2036 * reserved 2037 */ 2038 uint32_t slc1_tx_start_int_clr:1; 2039 /** slc1_rx_udf_int_clr : WT; bitpos: [10]; default: 0; 2040 * reserved 2041 */ 2042 uint32_t slc1_rx_udf_int_clr:1; 2043 /** slc1_tx_ovf_int_clr : WT; bitpos: [11]; default: 0; 2044 * reserved 2045 */ 2046 uint32_t slc1_tx_ovf_int_clr:1; 2047 /** slc1_token0_1to0_int_clr : WT; bitpos: [12]; default: 0; 2048 * reserved 2049 */ 2050 uint32_t slc1_token0_1to0_int_clr:1; 2051 /** slc1_token1_1to0_int_clr : WT; bitpos: [13]; default: 0; 2052 * reserved 2053 */ 2054 uint32_t slc1_token1_1to0_int_clr:1; 2055 /** slc1_tx_done_int_clr : WT; bitpos: [14]; default: 0; 2056 * reserved 2057 */ 2058 uint32_t slc1_tx_done_int_clr:1; 2059 /** slc1_tx_suc_eof_int_clr : WT; bitpos: [15]; default: 0; 2060 * reserved 2061 */ 2062 uint32_t slc1_tx_suc_eof_int_clr:1; 2063 /** slc1_rx_done_int_clr : WT; bitpos: [16]; default: 0; 2064 * reserved 2065 */ 2066 uint32_t slc1_rx_done_int_clr:1; 2067 /** slc1_rx_eof_int_clr : WT; bitpos: [17]; default: 0; 2068 * reserved 2069 */ 2070 uint32_t slc1_rx_eof_int_clr:1; 2071 /** slc1_tohost_int_clr : WT; bitpos: [18]; default: 0; 2072 * reserved 2073 */ 2074 uint32_t slc1_tohost_int_clr:1; 2075 /** slc1_tx_dscr_err_int_clr : WT; bitpos: [19]; default: 0; 2076 * reserved 2077 */ 2078 uint32_t slc1_tx_dscr_err_int_clr:1; 2079 /** slc1_rx_dscr_err_int_clr : WT; bitpos: [20]; default: 0; 2080 * reserved 2081 */ 2082 uint32_t slc1_rx_dscr_err_int_clr:1; 2083 /** slc1_tx_dscr_empty_int_clr : WT; bitpos: [21]; default: 0; 2084 * reserved 2085 */ 2086 uint32_t slc1_tx_dscr_empty_int_clr:1; 2087 /** slc1_host_rd_ack_int_clr : WT; bitpos: [22]; default: 0; 2088 * reserved 2089 */ 2090 uint32_t slc1_host_rd_ack_int_clr:1; 2091 /** slc1_wr_retry_done_int_clr : WT; bitpos: [23]; default: 0; 2092 * reserved 2093 */ 2094 uint32_t slc1_wr_retry_done_int_clr:1; 2095 /** slc1_tx_err_eof_int_clr : WT; bitpos: [24]; default: 0; 2096 * reserved 2097 */ 2098 uint32_t slc1_tx_err_eof_int_clr:1; 2099 uint32_t reserved_25:7; 2100 }; 2101 uint32_t val; 2102 } sdio_slc1int_clr_reg_t; 2103 2104 /** Type of slc0int_st1 register 2105 * reserved 2106 */ 2107 typedef union { 2108 struct { 2109 /** slc_frhost_bit0_int_st1 : RO; bitpos: [0]; default: 0; 2110 * reserved 2111 */ 2112 uint32_t slc_frhost_bit0_int_st1:1; 2113 /** slc_frhost_bit1_int_st1 : RO; bitpos: [1]; default: 0; 2114 * reserved 2115 */ 2116 uint32_t slc_frhost_bit1_int_st1:1; 2117 /** slc_frhost_bit2_int_st1 : RO; bitpos: [2]; default: 0; 2118 * reserved 2119 */ 2120 uint32_t slc_frhost_bit2_int_st1:1; 2121 /** slc_frhost_bit3_int_st1 : RO; bitpos: [3]; default: 0; 2122 * reserved 2123 */ 2124 uint32_t slc_frhost_bit3_int_st1:1; 2125 /** slc_frhost_bit4_int_st1 : RO; bitpos: [4]; default: 0; 2126 * reserved 2127 */ 2128 uint32_t slc_frhost_bit4_int_st1:1; 2129 /** slc_frhost_bit5_int_st1 : RO; bitpos: [5]; default: 0; 2130 * reserved 2131 */ 2132 uint32_t slc_frhost_bit5_int_st1:1; 2133 /** slc_frhost_bit6_int_st1 : RO; bitpos: [6]; default: 0; 2134 * reserved 2135 */ 2136 uint32_t slc_frhost_bit6_int_st1:1; 2137 /** slc_frhost_bit7_int_st1 : RO; bitpos: [7]; default: 0; 2138 * reserved 2139 */ 2140 uint32_t slc_frhost_bit7_int_st1:1; 2141 /** slc0_rx_start_int_st1 : RO; bitpos: [8]; default: 0; 2142 * reserved 2143 */ 2144 uint32_t slc0_rx_start_int_st1:1; 2145 /** slc0_tx_start_int_st1 : RO; bitpos: [9]; default: 0; 2146 * reserved 2147 */ 2148 uint32_t slc0_tx_start_int_st1:1; 2149 /** slc0_rx_udf_int_st1 : RO; bitpos: [10]; default: 0; 2150 * reserved 2151 */ 2152 uint32_t slc0_rx_udf_int_st1:1; 2153 /** slc0_tx_ovf_int_st1 : RO; bitpos: [11]; default: 0; 2154 * reserved 2155 */ 2156 uint32_t slc0_tx_ovf_int_st1:1; 2157 /** slc0_token0_1to0_int_st1 : RO; bitpos: [12]; default: 0; 2158 * reserved 2159 */ 2160 uint32_t slc0_token0_1to0_int_st1:1; 2161 /** slc0_token1_1to0_int_st1 : RO; bitpos: [13]; default: 0; 2162 * reserved 2163 */ 2164 uint32_t slc0_token1_1to0_int_st1:1; 2165 /** slc0_tx_done_int_st1 : RO; bitpos: [14]; default: 0; 2166 * reserved 2167 */ 2168 uint32_t slc0_tx_done_int_st1:1; 2169 /** slc0_tx_suc_eof_int_st1 : RO; bitpos: [15]; default: 0; 2170 * reserved 2171 */ 2172 uint32_t slc0_tx_suc_eof_int_st1:1; 2173 /** slc0_rx_done_int_st1 : RO; bitpos: [16]; default: 0; 2174 * reserved 2175 */ 2176 uint32_t slc0_rx_done_int_st1:1; 2177 /** slc0_rx_eof_int_st1 : RO; bitpos: [17]; default: 0; 2178 * reserved 2179 */ 2180 uint32_t slc0_rx_eof_int_st1:1; 2181 /** slc0_tohost_int_st1 : RO; bitpos: [18]; default: 0; 2182 * reserved 2183 */ 2184 uint32_t slc0_tohost_int_st1:1; 2185 /** slc0_tx_dscr_err_int_st1 : RO; bitpos: [19]; default: 0; 2186 * reserved 2187 */ 2188 uint32_t slc0_tx_dscr_err_int_st1:1; 2189 /** slc0_rx_dscr_err_int_st1 : RO; bitpos: [20]; default: 0; 2190 * reserved 2191 */ 2192 uint32_t slc0_rx_dscr_err_int_st1:1; 2193 /** slc0_tx_dscr_empty_int_st1 : RO; bitpos: [21]; default: 0; 2194 * reserved 2195 */ 2196 uint32_t slc0_tx_dscr_empty_int_st1:1; 2197 /** slc0_host_rd_ack_int_st1 : RO; bitpos: [22]; default: 0; 2198 * reserved 2199 */ 2200 uint32_t slc0_host_rd_ack_int_st1:1; 2201 /** slc0_wr_retry_done_int_st1 : RO; bitpos: [23]; default: 0; 2202 * reserved 2203 */ 2204 uint32_t slc0_wr_retry_done_int_st1:1; 2205 /** slc0_tx_err_eof_int_st1 : RO; bitpos: [24]; default: 0; 2206 * reserved 2207 */ 2208 uint32_t slc0_tx_err_eof_int_st1:1; 2209 /** cmd_dtc_int_st1 : RO; bitpos: [25]; default: 0; 2210 * reserved 2211 */ 2212 uint32_t cmd_dtc_int_st1:1; 2213 /** slc0_rx_quick_eof_int_st1 : RO; bitpos: [26]; default: 0; 2214 * reserved 2215 */ 2216 uint32_t slc0_rx_quick_eof_int_st1:1; 2217 /** slc0_host_pop_eof_err_int_st1 : RO; bitpos: [27]; default: 0; 2218 * reserved 2219 */ 2220 uint32_t slc0_host_pop_eof_err_int_st1:1; 2221 /** hda_recv_done_int_st1 : RO; bitpos: [28]; default: 0; 2222 * reserved 2223 */ 2224 uint32_t hda_recv_done_int_st1:1; 2225 uint32_t reserved_29:3; 2226 }; 2227 uint32_t val; 2228 } sdio_slc0int_st1_reg_t; 2229 2230 /** Type of slc0int_ena1 register 2231 * reserved 2232 */ 2233 typedef union { 2234 struct { 2235 /** slc_frhost_bit0_int_ena1 : R/W; bitpos: [0]; default: 0; 2236 * reserved 2237 */ 2238 uint32_t slc_frhost_bit0_int_ena1:1; 2239 /** slc_frhost_bit1_int_ena1 : R/W; bitpos: [1]; default: 0; 2240 * reserved 2241 */ 2242 uint32_t slc_frhost_bit1_int_ena1:1; 2243 /** slc_frhost_bit2_int_ena1 : R/W; bitpos: [2]; default: 0; 2244 * reserved 2245 */ 2246 uint32_t slc_frhost_bit2_int_ena1:1; 2247 /** slc_frhost_bit3_int_ena1 : R/W; bitpos: [3]; default: 0; 2248 * reserved 2249 */ 2250 uint32_t slc_frhost_bit3_int_ena1:1; 2251 /** slc_frhost_bit4_int_ena1 : R/W; bitpos: [4]; default: 0; 2252 * reserved 2253 */ 2254 uint32_t slc_frhost_bit4_int_ena1:1; 2255 /** slc_frhost_bit5_int_ena1 : R/W; bitpos: [5]; default: 0; 2256 * reserved 2257 */ 2258 uint32_t slc_frhost_bit5_int_ena1:1; 2259 /** slc_frhost_bit6_int_ena1 : R/W; bitpos: [6]; default: 0; 2260 * reserved 2261 */ 2262 uint32_t slc_frhost_bit6_int_ena1:1; 2263 /** slc_frhost_bit7_int_ena1 : R/W; bitpos: [7]; default: 0; 2264 * reserved 2265 */ 2266 uint32_t slc_frhost_bit7_int_ena1:1; 2267 /** slc0_rx_start_int_ena1 : R/W; bitpos: [8]; default: 0; 2268 * reserved 2269 */ 2270 uint32_t slc0_rx_start_int_ena1:1; 2271 /** slc0_tx_start_int_ena1 : R/W; bitpos: [9]; default: 0; 2272 * reserved 2273 */ 2274 uint32_t slc0_tx_start_int_ena1:1; 2275 /** slc0_rx_udf_int_ena1 : R/W; bitpos: [10]; default: 0; 2276 * reserved 2277 */ 2278 uint32_t slc0_rx_udf_int_ena1:1; 2279 /** slc0_tx_ovf_int_ena1 : R/W; bitpos: [11]; default: 0; 2280 * reserved 2281 */ 2282 uint32_t slc0_tx_ovf_int_ena1:1; 2283 /** slc0_token0_1to0_int_ena1 : R/W; bitpos: [12]; default: 0; 2284 * reserved 2285 */ 2286 uint32_t slc0_token0_1to0_int_ena1:1; 2287 /** slc0_token1_1to0_int_ena1 : R/W; bitpos: [13]; default: 0; 2288 * reserved 2289 */ 2290 uint32_t slc0_token1_1to0_int_ena1:1; 2291 /** slc0_tx_done_int_ena1 : R/W; bitpos: [14]; default: 0; 2292 * reserved 2293 */ 2294 uint32_t slc0_tx_done_int_ena1:1; 2295 /** slc0_tx_suc_eof_int_ena1 : R/W; bitpos: [15]; default: 0; 2296 * reserved 2297 */ 2298 uint32_t slc0_tx_suc_eof_int_ena1:1; 2299 /** slc0_rx_done_int_ena1 : R/W; bitpos: [16]; default: 0; 2300 * reserved 2301 */ 2302 uint32_t slc0_rx_done_int_ena1:1; 2303 /** slc0_rx_eof_int_ena1 : R/W; bitpos: [17]; default: 0; 2304 * reserved 2305 */ 2306 uint32_t slc0_rx_eof_int_ena1:1; 2307 /** slc0_tohost_int_ena1 : R/W; bitpos: [18]; default: 0; 2308 * reserved 2309 */ 2310 uint32_t slc0_tohost_int_ena1:1; 2311 /** slc0_tx_dscr_err_int_ena1 : R/W; bitpos: [19]; default: 0; 2312 * reserved 2313 */ 2314 uint32_t slc0_tx_dscr_err_int_ena1:1; 2315 /** slc0_rx_dscr_err_int_ena1 : R/W; bitpos: [20]; default: 0; 2316 * reserved 2317 */ 2318 uint32_t slc0_rx_dscr_err_int_ena1:1; 2319 /** slc0_tx_dscr_empty_int_ena1 : R/W; bitpos: [21]; default: 0; 2320 * reserved 2321 */ 2322 uint32_t slc0_tx_dscr_empty_int_ena1:1; 2323 /** slc0_host_rd_ack_int_ena1 : R/W; bitpos: [22]; default: 0; 2324 * reserved 2325 */ 2326 uint32_t slc0_host_rd_ack_int_ena1:1; 2327 /** slc0_wr_retry_done_int_ena1 : R/W; bitpos: [23]; default: 0; 2328 * reserved 2329 */ 2330 uint32_t slc0_wr_retry_done_int_ena1:1; 2331 /** slc0_tx_err_eof_int_ena1 : R/W; bitpos: [24]; default: 0; 2332 * reserved 2333 */ 2334 uint32_t slc0_tx_err_eof_int_ena1:1; 2335 /** cmd_dtc_int_ena1 : R/W; bitpos: [25]; default: 0; 2336 * reserved 2337 */ 2338 uint32_t cmd_dtc_int_ena1:1; 2339 /** slc0_rx_quick_eof_int_ena1 : R/W; bitpos: [26]; default: 0; 2340 * reserved 2341 */ 2342 uint32_t slc0_rx_quick_eof_int_ena1:1; 2343 /** slc0_host_pop_eof_err_int_ena1 : R/W; bitpos: [27]; default: 0; 2344 * reserved 2345 */ 2346 uint32_t slc0_host_pop_eof_err_int_ena1:1; 2347 /** hda_recv_done_int_ena1 : R/W; bitpos: [28]; default: 0; 2348 * reserved 2349 */ 2350 uint32_t hda_recv_done_int_ena1:1; 2351 uint32_t reserved_29:3; 2352 }; 2353 uint32_t val; 2354 } sdio_slc0int_ena1_reg_t; 2355 2356 /** Type of slc1int_st1 register 2357 * reserved 2358 */ 2359 typedef union { 2360 struct { 2361 /** slc_frhost_bit8_int_st1 : RO; bitpos: [0]; default: 0; 2362 * reserved 2363 */ 2364 uint32_t slc_frhost_bit8_int_st1:1; 2365 /** slc_frhost_bit9_int_st1 : RO; bitpos: [1]; default: 0; 2366 * reserved 2367 */ 2368 uint32_t slc_frhost_bit9_int_st1:1; 2369 /** slc_frhost_bit10_int_st1 : RO; bitpos: [2]; default: 0; 2370 * reserved 2371 */ 2372 uint32_t slc_frhost_bit10_int_st1:1; 2373 /** slc_frhost_bit11_int_st1 : RO; bitpos: [3]; default: 0; 2374 * reserved 2375 */ 2376 uint32_t slc_frhost_bit11_int_st1:1; 2377 /** slc_frhost_bit12_int_st1 : RO; bitpos: [4]; default: 0; 2378 * reserved 2379 */ 2380 uint32_t slc_frhost_bit12_int_st1:1; 2381 /** slc_frhost_bit13_int_st1 : RO; bitpos: [5]; default: 0; 2382 * reserved 2383 */ 2384 uint32_t slc_frhost_bit13_int_st1:1; 2385 /** slc_frhost_bit14_int_st1 : RO; bitpos: [6]; default: 0; 2386 * reserved 2387 */ 2388 uint32_t slc_frhost_bit14_int_st1:1; 2389 /** slc_frhost_bit15_int_st1 : RO; bitpos: [7]; default: 0; 2390 * reserved 2391 */ 2392 uint32_t slc_frhost_bit15_int_st1:1; 2393 /** slc1_rx_start_int_st1 : RO; bitpos: [8]; default: 0; 2394 * reserved 2395 */ 2396 uint32_t slc1_rx_start_int_st1:1; 2397 /** slc1_tx_start_int_st1 : RO; bitpos: [9]; default: 0; 2398 * reserved 2399 */ 2400 uint32_t slc1_tx_start_int_st1:1; 2401 /** slc1_rx_udf_int_st1 : RO; bitpos: [10]; default: 0; 2402 * reserved 2403 */ 2404 uint32_t slc1_rx_udf_int_st1:1; 2405 /** slc1_tx_ovf_int_st1 : RO; bitpos: [11]; default: 0; 2406 * reserved 2407 */ 2408 uint32_t slc1_tx_ovf_int_st1:1; 2409 /** slc1_token0_1to0_int_st1 : RO; bitpos: [12]; default: 0; 2410 * reserved 2411 */ 2412 uint32_t slc1_token0_1to0_int_st1:1; 2413 /** slc1_token1_1to0_int_st1 : RO; bitpos: [13]; default: 0; 2414 * reserved 2415 */ 2416 uint32_t slc1_token1_1to0_int_st1:1; 2417 /** slc1_tx_done_int_st1 : RO; bitpos: [14]; default: 0; 2418 * reserved 2419 */ 2420 uint32_t slc1_tx_done_int_st1:1; 2421 /** slc1_tx_suc_eof_int_st1 : RO; bitpos: [15]; default: 0; 2422 * reserved 2423 */ 2424 uint32_t slc1_tx_suc_eof_int_st1:1; 2425 /** slc1_rx_done_int_st1 : RO; bitpos: [16]; default: 0; 2426 * reserved 2427 */ 2428 uint32_t slc1_rx_done_int_st1:1; 2429 /** slc1_rx_eof_int_st1 : RO; bitpos: [17]; default: 0; 2430 * reserved 2431 */ 2432 uint32_t slc1_rx_eof_int_st1:1; 2433 /** slc1_tohost_int_st1 : RO; bitpos: [18]; default: 0; 2434 * reserved 2435 */ 2436 uint32_t slc1_tohost_int_st1:1; 2437 /** slc1_tx_dscr_err_int_st1 : RO; bitpos: [19]; default: 0; 2438 * reserved 2439 */ 2440 uint32_t slc1_tx_dscr_err_int_st1:1; 2441 /** slc1_rx_dscr_err_int_st1 : RO; bitpos: [20]; default: 0; 2442 * reserved 2443 */ 2444 uint32_t slc1_rx_dscr_err_int_st1:1; 2445 /** slc1_tx_dscr_empty_int_st1 : RO; bitpos: [21]; default: 0; 2446 * reserved 2447 */ 2448 uint32_t slc1_tx_dscr_empty_int_st1:1; 2449 /** slc1_host_rd_ack_int_st1 : RO; bitpos: [22]; default: 0; 2450 * reserved 2451 */ 2452 uint32_t slc1_host_rd_ack_int_st1:1; 2453 /** slc1_wr_retry_done_int_st1 : RO; bitpos: [23]; default: 0; 2454 * reserved 2455 */ 2456 uint32_t slc1_wr_retry_done_int_st1:1; 2457 /** slc1_tx_err_eof_int_st1 : RO; bitpos: [24]; default: 0; 2458 * reserved 2459 */ 2460 uint32_t slc1_tx_err_eof_int_st1:1; 2461 uint32_t reserved_25:7; 2462 }; 2463 uint32_t val; 2464 } sdio_slc1int_st1_reg_t; 2465 2466 /** Type of slc1int_ena1 register 2467 * reserved 2468 */ 2469 typedef union { 2470 struct { 2471 /** slc_frhost_bit8_int_ena1 : R/W; bitpos: [0]; default: 0; 2472 * reserved 2473 */ 2474 uint32_t slc_frhost_bit8_int_ena1:1; 2475 /** slc_frhost_bit9_int_ena1 : R/W; bitpos: [1]; default: 0; 2476 * reserved 2477 */ 2478 uint32_t slc_frhost_bit9_int_ena1:1; 2479 /** slc_frhost_bit10_int_ena1 : R/W; bitpos: [2]; default: 0; 2480 * reserved 2481 */ 2482 uint32_t slc_frhost_bit10_int_ena1:1; 2483 /** slc_frhost_bit11_int_ena1 : R/W; bitpos: [3]; default: 0; 2484 * reserved 2485 */ 2486 uint32_t slc_frhost_bit11_int_ena1:1; 2487 /** slc_frhost_bit12_int_ena1 : R/W; bitpos: [4]; default: 0; 2488 * reserved 2489 */ 2490 uint32_t slc_frhost_bit12_int_ena1:1; 2491 /** slc_frhost_bit13_int_ena1 : R/W; bitpos: [5]; default: 0; 2492 * reserved 2493 */ 2494 uint32_t slc_frhost_bit13_int_ena1:1; 2495 /** slc_frhost_bit14_int_ena1 : R/W; bitpos: [6]; default: 0; 2496 * reserved 2497 */ 2498 uint32_t slc_frhost_bit14_int_ena1:1; 2499 /** slc_frhost_bit15_int_ena1 : R/W; bitpos: [7]; default: 0; 2500 * reserved 2501 */ 2502 uint32_t slc_frhost_bit15_int_ena1:1; 2503 /** slc1_rx_start_int_ena1 : R/W; bitpos: [8]; default: 0; 2504 * reserved 2505 */ 2506 uint32_t slc1_rx_start_int_ena1:1; 2507 /** slc1_tx_start_int_ena1 : R/W; bitpos: [9]; default: 0; 2508 * reserved 2509 */ 2510 uint32_t slc1_tx_start_int_ena1:1; 2511 /** slc1_rx_udf_int_ena1 : R/W; bitpos: [10]; default: 0; 2512 * reserved 2513 */ 2514 uint32_t slc1_rx_udf_int_ena1:1; 2515 /** slc1_tx_ovf_int_ena1 : R/W; bitpos: [11]; default: 0; 2516 * reserved 2517 */ 2518 uint32_t slc1_tx_ovf_int_ena1:1; 2519 /** slc1_token0_1to0_int_ena1 : R/W; bitpos: [12]; default: 0; 2520 * reserved 2521 */ 2522 uint32_t slc1_token0_1to0_int_ena1:1; 2523 /** slc1_token1_1to0_int_ena1 : R/W; bitpos: [13]; default: 0; 2524 * reserved 2525 */ 2526 uint32_t slc1_token1_1to0_int_ena1:1; 2527 /** slc1_tx_done_int_ena1 : R/W; bitpos: [14]; default: 0; 2528 * reserved 2529 */ 2530 uint32_t slc1_tx_done_int_ena1:1; 2531 /** slc1_tx_suc_eof_int_ena1 : R/W; bitpos: [15]; default: 0; 2532 * reserved 2533 */ 2534 uint32_t slc1_tx_suc_eof_int_ena1:1; 2535 /** slc1_rx_done_int_ena1 : R/W; bitpos: [16]; default: 0; 2536 * reserved 2537 */ 2538 uint32_t slc1_rx_done_int_ena1:1; 2539 /** slc1_rx_eof_int_ena1 : R/W; bitpos: [17]; default: 0; 2540 * reserved 2541 */ 2542 uint32_t slc1_rx_eof_int_ena1:1; 2543 /** slc1_tohost_int_ena1 : R/W; bitpos: [18]; default: 0; 2544 * reserved 2545 */ 2546 uint32_t slc1_tohost_int_ena1:1; 2547 /** slc1_tx_dscr_err_int_ena1 : R/W; bitpos: [19]; default: 0; 2548 * reserved 2549 */ 2550 uint32_t slc1_tx_dscr_err_int_ena1:1; 2551 /** slc1_rx_dscr_err_int_ena1 : R/W; bitpos: [20]; default: 0; 2552 * reserved 2553 */ 2554 uint32_t slc1_rx_dscr_err_int_ena1:1; 2555 /** slc1_tx_dscr_empty_int_ena1 : R/W; bitpos: [21]; default: 0; 2556 * reserved 2557 */ 2558 uint32_t slc1_tx_dscr_empty_int_ena1:1; 2559 /** slc1_host_rd_ack_int_ena1 : R/W; bitpos: [22]; default: 0; 2560 * reserved 2561 */ 2562 uint32_t slc1_host_rd_ack_int_ena1:1; 2563 /** slc1_wr_retry_done_int_ena1 : R/W; bitpos: [23]; default: 0; 2564 * reserved 2565 */ 2566 uint32_t slc1_wr_retry_done_int_ena1:1; 2567 /** slc1_tx_err_eof_int_ena1 : R/W; bitpos: [24]; default: 0; 2568 * reserved 2569 */ 2570 uint32_t slc1_tx_err_eof_int_ena1:1; 2571 uint32_t reserved_25:7; 2572 }; 2573 uint32_t val; 2574 } sdio_slc1int_ena1_reg_t; 2575 2576 2577 /** Group: Status registers */ 2578 /** Type of slcrx_status register 2579 * ******* Description *********** 2580 */ 2581 typedef union { 2582 struct { 2583 /** slc0_rx_full : RO; bitpos: [0]; default: 0; 2584 * reserved 2585 */ 2586 uint32_t slc0_rx_full:1; 2587 /** slc0_rx_empty : RO; bitpos: [1]; default: 1; 2588 * reserved 2589 */ 2590 uint32_t slc0_rx_empty:1; 2591 /** slc0_rx_buf_len : RO; bitpos: [15:2]; default: 0; 2592 * the current buffer length when slc0 reads data from rx link 2593 */ 2594 uint32_t slc0_rx_buf_len:14; 2595 /** slc1_rx_full : RO; bitpos: [16]; default: 0; 2596 * reserved 2597 */ 2598 uint32_t slc1_rx_full:1; 2599 /** slc1_rx_empty : RO; bitpos: [17]; default: 1; 2600 * reserved 2601 */ 2602 uint32_t slc1_rx_empty:1; 2603 /** slc1_rx_buf_len : RO; bitpos: [31:18]; default: 0; 2604 * the current buffer length when slc1 reads data from rx link 2605 */ 2606 uint32_t slc1_rx_buf_len:14; 2607 }; 2608 uint32_t val; 2609 } sdio_slcrx_status_reg_t; 2610 2611 /** Type of slctx_status register 2612 * ******* Description *********** 2613 */ 2614 typedef union { 2615 struct { 2616 /** slc0_tx_full : RO; bitpos: [0]; default: 0; 2617 * reserved 2618 */ 2619 uint32_t slc0_tx_full:1; 2620 /** slc0_tx_empty : RO; bitpos: [1]; default: 1; 2621 * reserved 2622 */ 2623 uint32_t slc0_tx_empty:1; 2624 uint32_t reserved_2:14; 2625 /** slc1_tx_full : RO; bitpos: [16]; default: 0; 2626 * reserved 2627 */ 2628 uint32_t slc1_tx_full:1; 2629 /** slc1_tx_empty : RO; bitpos: [17]; default: 1; 2630 * reserved 2631 */ 2632 uint32_t slc1_tx_empty:1; 2633 uint32_t reserved_18:14; 2634 }; 2635 uint32_t val; 2636 } sdio_slctx_status_reg_t; 2637 2638 /** Type of slc0_state0 register 2639 * reserved 2640 */ 2641 typedef union { 2642 struct { 2643 /** slc0_state0 : RO; bitpos: [31:0]; default: 0; 2644 * reserved 2645 */ 2646 uint32_t slc0_state0:32; 2647 }; 2648 uint32_t val; 2649 } sdio_slc0_state0_reg_t; 2650 2651 /** Type of slc0_state1 register 2652 * ******* Description *********** 2653 */ 2654 typedef union { 2655 struct { 2656 /** slc0_state1 : RO; bitpos: [31:0]; default: 0; 2657 * [18:0] the current rx descriptor address, [20:19] rx_dscr fsm state, [23:21] 2658 * rx_link fsm state, [30:24] rx_fifo_cnt 2659 */ 2660 uint32_t slc0_state1:32; 2661 }; 2662 uint32_t val; 2663 } sdio_slc0_state1_reg_t; 2664 2665 /** Type of slc1_state0 register 2666 * ******* Description *********** 2667 */ 2668 typedef union { 2669 struct { 2670 /** slc1_state0 : RO; bitpos: [31:0]; default: 0; 2671 * reserved 2672 */ 2673 uint32_t slc1_state0:32; 2674 }; 2675 uint32_t val; 2676 } sdio_slc1_state0_reg_t; 2677 2678 /** Type of slc1_state1 register 2679 * ******* Description *********** 2680 */ 2681 typedef union { 2682 struct { 2683 /** slc1_state1 : RO; bitpos: [31:0]; default: 0; 2684 * [18:0] the current rx descriptor address, [20:19] rx_dscr fsm state, [23:21] 2685 * rx_link fsm state, [30:24] rx_fifo_cnt 2686 */ 2687 uint32_t slc1_state1:32; 2688 }; 2689 uint32_t val; 2690 } sdio_slc1_state1_reg_t; 2691 2692 /** Type of slc_sdio_st register 2693 * reserved 2694 */ 2695 typedef union { 2696 struct { 2697 /** cmd_st : RO; bitpos: [2:0]; default: 0; 2698 * reserved 2699 */ 2700 uint32_t cmd_st:3; 2701 uint32_t reserved_3:1; 2702 /** func_st : RO; bitpos: [7:4]; default: 0; 2703 * reserved 2704 */ 2705 uint32_t func_st:4; 2706 /** sdio_wakeup : RO; bitpos: [8]; default: 0; 2707 * reserved 2708 */ 2709 uint32_t sdio_wakeup:1; 2710 uint32_t reserved_9:3; 2711 /** bus_st : RO; bitpos: [14:12]; default: 0; 2712 * reserved 2713 */ 2714 uint32_t bus_st:3; 2715 uint32_t reserved_15:1; 2716 /** func1_acc_state : RO; bitpos: [20:16]; default: 0; 2717 * reserved 2718 */ 2719 uint32_t func1_acc_state:5; 2720 uint32_t reserved_21:3; 2721 /** func2_acc_state : RO; bitpos: [28:24]; default: 0; 2722 * reserved 2723 */ 2724 uint32_t func2_acc_state:5; 2725 uint32_t reserved_29:3; 2726 }; 2727 uint32_t val; 2728 } sdio_slc_sdio_st_reg_t; 2729 2730 /** Type of slc0_txlink_dscr register 2731 * ******* Description *********** 2732 */ 2733 typedef union { 2734 struct { 2735 /** slc0_txlink_dscr : RO; bitpos: [31:0]; default: 0; 2736 * reserved 2737 */ 2738 uint32_t slc0_txlink_dscr:32; 2739 }; 2740 uint32_t val; 2741 } sdio_slc0_txlink_dscr_reg_t; 2742 2743 /** Type of slc0_txlink_dscr_bf0 register 2744 * ******* Description *********** 2745 */ 2746 typedef union { 2747 struct { 2748 /** slc0_txlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; 2749 * reserved 2750 */ 2751 uint32_t slc0_txlink_dscr_bf0:32; 2752 }; 2753 uint32_t val; 2754 } sdio_slc0_txlink_dscr_bf0_reg_t; 2755 2756 /** Type of slc0_txlink_dscr_bf1 register 2757 * reserved 2758 */ 2759 typedef union { 2760 struct { 2761 /** slc0_txlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; 2762 * reserved 2763 */ 2764 uint32_t slc0_txlink_dscr_bf1:32; 2765 }; 2766 uint32_t val; 2767 } sdio_slc0_txlink_dscr_bf1_reg_t; 2768 2769 /** Type of slc0_rxlink_dscr register 2770 * ******* Description *********** 2771 */ 2772 typedef union { 2773 struct { 2774 /** slc0_rxlink_dscr : RO; bitpos: [31:0]; default: 0; 2775 * the third word of slc0 link descriptor, or known as the next descriptor address 2776 */ 2777 uint32_t slc0_rxlink_dscr:32; 2778 }; 2779 uint32_t val; 2780 } sdio_slc0_rxlink_dscr_reg_t; 2781 2782 /** Type of slc0_rxlink_dscr_bf0 register 2783 * ******* Description *********** 2784 */ 2785 typedef union { 2786 struct { 2787 /** slc0_rxlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; 2788 * reserved 2789 */ 2790 uint32_t slc0_rxlink_dscr_bf0:32; 2791 }; 2792 uint32_t val; 2793 } sdio_slc0_rxlink_dscr_bf0_reg_t; 2794 2795 /** Type of slc0_rxlink_dscr_bf1 register 2796 * reserved 2797 */ 2798 typedef union { 2799 struct { 2800 /** slc0_rxlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; 2801 * reserved 2802 */ 2803 uint32_t slc0_rxlink_dscr_bf1:32; 2804 }; 2805 uint32_t val; 2806 } sdio_slc0_rxlink_dscr_bf1_reg_t; 2807 2808 /** Type of slc1_txlink_dscr register 2809 * reserved 2810 */ 2811 typedef union { 2812 struct { 2813 /** slc1_txlink_dscr : RO; bitpos: [31:0]; default: 0; 2814 * reserved 2815 */ 2816 uint32_t slc1_txlink_dscr:32; 2817 }; 2818 uint32_t val; 2819 } sdio_slc1_txlink_dscr_reg_t; 2820 2821 /** Type of slc1_txlink_dscr_bf0 register 2822 * reserved 2823 */ 2824 typedef union { 2825 struct { 2826 /** slc1_txlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; 2827 * reserved 2828 */ 2829 uint32_t slc1_txlink_dscr_bf0:32; 2830 }; 2831 uint32_t val; 2832 } sdio_slc1_txlink_dscr_bf0_reg_t; 2833 2834 /** Type of slc1_txlink_dscr_bf1 register 2835 * reserved 2836 */ 2837 typedef union { 2838 struct { 2839 /** slc1_txlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; 2840 * reserved 2841 */ 2842 uint32_t slc1_txlink_dscr_bf1:32; 2843 }; 2844 uint32_t val; 2845 } sdio_slc1_txlink_dscr_bf1_reg_t; 2846 2847 /** Type of slc1_rxlink_dscr register 2848 * ******* Description *********** 2849 */ 2850 typedef union { 2851 struct { 2852 /** slc1_rxlink_dscr : RO; bitpos: [31:0]; default: 0; 2853 * the third word of slc1 link descriptor, or known as the next descriptor address 2854 */ 2855 uint32_t slc1_rxlink_dscr:32; 2856 }; 2857 uint32_t val; 2858 } sdio_slc1_rxlink_dscr_reg_t; 2859 2860 /** Type of slc1_rxlink_dscr_bf0 register 2861 * ******* Description *********** 2862 */ 2863 typedef union { 2864 struct { 2865 /** slc1_rxlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; 2866 * reserved 2867 */ 2868 uint32_t slc1_rxlink_dscr_bf0:32; 2869 }; 2870 uint32_t val; 2871 } sdio_slc1_rxlink_dscr_bf0_reg_t; 2872 2873 /** Type of slc1_rxlink_dscr_bf1 register 2874 * reserved 2875 */ 2876 typedef union { 2877 struct { 2878 /** slc1_rxlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; 2879 * reserved 2880 */ 2881 uint32_t slc1_rxlink_dscr_bf1:32; 2882 }; 2883 uint32_t val; 2884 } sdio_slc1_rxlink_dscr_bf1_reg_t; 2885 2886 /** Type of slc0_tx_erreof_des_addr register 2887 * reserved 2888 */ 2889 typedef union { 2890 struct { 2891 /** slc0_tx_err_eof_des_addr : RO; bitpos: [31:0]; default: 0; 2892 * reserved 2893 */ 2894 uint32_t slc0_tx_err_eof_des_addr:32; 2895 }; 2896 uint32_t val; 2897 } sdio_slc0_tx_erreof_des_addr_reg_t; 2898 2899 /** Type of slc1_tx_erreof_des_addr register 2900 * reserved 2901 */ 2902 typedef union { 2903 struct { 2904 /** slc1_tx_err_eof_des_addr : RO; bitpos: [31:0]; default: 0; 2905 * reserved 2906 */ 2907 uint32_t slc1_tx_err_eof_des_addr:32; 2908 }; 2909 uint32_t val; 2910 } sdio_slc1_tx_erreof_des_addr_reg_t; 2911 2912 /** Type of slc_token_lat register 2913 * reserved 2914 */ 2915 typedef union { 2916 struct { 2917 /** slc0_token : RO; bitpos: [11:0]; default: 0; 2918 * reserved 2919 */ 2920 uint32_t slc0_token:12; 2921 uint32_t reserved_12:4; 2922 /** slc1_token : RO; bitpos: [27:16]; default: 0; 2923 * reserved 2924 */ 2925 uint32_t slc1_token:12; 2926 uint32_t reserved_28:4; 2927 }; 2928 uint32_t val; 2929 } sdio_slc_token_lat_reg_t; 2930 2931 /** Type of slc_cmd_infor0 register 2932 * reserved 2933 */ 2934 typedef union { 2935 struct { 2936 /** cmd_content0 : RO; bitpos: [31:0]; default: 0; 2937 * reserved 2938 */ 2939 uint32_t cmd_content0:32; 2940 }; 2941 uint32_t val; 2942 } sdio_slc_cmd_infor0_reg_t; 2943 2944 /** Type of slc_cmd_infor1 register 2945 * reserved 2946 */ 2947 typedef union { 2948 struct { 2949 /** cmd_content1 : RO; bitpos: [31:0]; default: 0; 2950 * reserved 2951 */ 2952 uint32_t cmd_content1:32; 2953 }; 2954 uint32_t val; 2955 } sdio_slc_cmd_infor1_reg_t; 2956 2957 /** Type of slc0_length register 2958 * reserved 2959 */ 2960 typedef union { 2961 struct { 2962 /** slc0_len : RO; bitpos: [19:0]; default: 0; 2963 * reserved 2964 */ 2965 uint32_t slc0_len:20; 2966 uint32_t reserved_20:12; 2967 }; 2968 uint32_t val; 2969 } sdio_slc0_length_reg_t; 2970 2971 /** Type of slc_sdio_crc_st0 register 2972 * reserved 2973 */ 2974 typedef union { 2975 struct { 2976 /** dat0_crc_err_cnt : RO; bitpos: [7:0]; default: 0; 2977 * reserved 2978 */ 2979 uint32_t dat0_crc_err_cnt:8; 2980 /** dat1_crc_err_cnt : RO; bitpos: [15:8]; default: 0; 2981 * reserved 2982 */ 2983 uint32_t dat1_crc_err_cnt:8; 2984 /** dat2_crc_err_cnt : RO; bitpos: [23:16]; default: 0; 2985 * reserved 2986 */ 2987 uint32_t dat2_crc_err_cnt:8; 2988 /** dat3_crc_err_cnt : RO; bitpos: [31:24]; default: 0; 2989 * reserved 2990 */ 2991 uint32_t dat3_crc_err_cnt:8; 2992 }; 2993 uint32_t val; 2994 } sdio_slc_sdio_crc_st0_reg_t; 2995 2996 /** Type of slc0_eof_start_des register 2997 * reserved 2998 */ 2999 typedef union { 3000 struct { 3001 /** slc0_eof_start_des_addr : RO; bitpos: [31:0]; default: 0; 3002 * reserved 3003 */ 3004 uint32_t slc0_eof_start_des_addr:32; 3005 }; 3006 uint32_t val; 3007 } sdio_slc0_eof_start_des_reg_t; 3008 3009 /** Type of slc0_push_dscr_addr register 3010 * ******* Description *********** 3011 */ 3012 typedef union { 3013 struct { 3014 /** slc0_rx_push_dscr_addr : RO; bitpos: [31:0]; default: 0; 3015 * the current descriptor address when slc0 gets a link descriptor, aligned with word 3016 */ 3017 uint32_t slc0_rx_push_dscr_addr:32; 3018 }; 3019 uint32_t val; 3020 } sdio_slc0_push_dscr_addr_reg_t; 3021 3022 /** Type of slc0_done_dscr_addr register 3023 * ******* Description *********** 3024 */ 3025 typedef union { 3026 struct { 3027 /** slc0_rx_done_dscr_addr : RO; bitpos: [31:0]; default: 0; 3028 * the current descriptor address when slc0 finishes reading data from one buffer, 3029 * aligned with word 3030 */ 3031 uint32_t slc0_rx_done_dscr_addr:32; 3032 }; 3033 uint32_t val; 3034 } sdio_slc0_done_dscr_addr_reg_t; 3035 3036 /** Type of slc0_sub_start_des register 3037 * ******* Description *********** 3038 */ 3039 typedef union { 3040 struct { 3041 /** slc0_sub_pac_start_dscr_addr : RO; bitpos: [31:0]; default: 0; 3042 * the current descriptor address when slc0 gets a link descriptor, aligned with word 3043 */ 3044 uint32_t slc0_sub_pac_start_dscr_addr:32; 3045 }; 3046 uint32_t val; 3047 } sdio_slc0_sub_start_des_reg_t; 3048 3049 /** Type of slc0_dscr_cnt register 3050 * ******* Description *********** 3051 */ 3052 typedef union { 3053 struct { 3054 /** slc0_rx_dscr_cnt_lat : RO; bitpos: [9:0]; default: 0; 3055 * the number of descriptors got by slc0 when it tries to read data from memory 3056 */ 3057 uint32_t slc0_rx_dscr_cnt_lat:10; 3058 uint32_t reserved_10:6; 3059 /** slc0_rx_get_eof_occ : RO; bitpos: [16]; default: 0; 3060 * reserved 3061 */ 3062 uint32_t slc0_rx_get_eof_occ:1; 3063 uint32_t reserved_17:15; 3064 }; 3065 uint32_t val; 3066 } sdio_slc0_dscr_cnt_reg_t; 3067 3068 3069 /** Group: Debud registers */ 3070 /** Type of slc0txfifo_pop register 3071 * reserved 3072 */ 3073 typedef union { 3074 struct { 3075 /** slc0_txfifo_rdata : RO; bitpos: [10:0]; default: 1024; 3076 * reserved 3077 */ 3078 uint32_t slc0_txfifo_rdata:11; 3079 uint32_t reserved_11:5; 3080 /** slc0_txfifo_pop : R/W/SC; bitpos: [16]; default: 0; 3081 * reserved 3082 */ 3083 uint32_t slc0_txfifo_pop:1; 3084 uint32_t reserved_17:15; 3085 }; 3086 uint32_t val; 3087 } sdio_slc0txfifo_pop_reg_t; 3088 3089 /** Type of slc1txfifo_pop register 3090 * reserved 3091 */ 3092 typedef union { 3093 struct { 3094 /** slc1_txfifo_rdata : RO; bitpos: [10:0]; default: 1024; 3095 * reserved 3096 */ 3097 uint32_t slc1_txfifo_rdata:11; 3098 uint32_t reserved_11:5; 3099 /** slc1_txfifo_pop : R/W/SC; bitpos: [16]; default: 0; 3100 * reserved 3101 */ 3102 uint32_t slc1_txfifo_pop:1; 3103 uint32_t reserved_17:15; 3104 }; 3105 uint32_t val; 3106 } sdio_slc1txfifo_pop_reg_t; 3107 3108 /** Type of slc_ahb_test register 3109 * reserved 3110 */ 3111 typedef union { 3112 struct { 3113 /** slc_ahb_testmode : R/W; bitpos: [2:0]; default: 0; 3114 * reserved 3115 */ 3116 uint32_t slc_ahb_testmode:3; 3117 uint32_t reserved_3:1; 3118 /** slc_ahb_testaddr : R/W; bitpos: [5:4]; default: 0; 3119 * reserved 3120 */ 3121 uint32_t slc_ahb_testaddr:2; 3122 uint32_t reserved_6:26; 3123 }; 3124 uint32_t val; 3125 } sdio_slc_ahb_test_reg_t; 3126 3127 3128 /** Group: Version registers */ 3129 /** Type of slcdate register 3130 * ******* Description *********** 3131 */ 3132 typedef union { 3133 struct { 3134 /** slc_date : R/W; bitpos: [31:0]; default: 554182400; 3135 * reserved 3136 */ 3137 uint32_t slc_date:32; 3138 }; 3139 uint32_t val; 3140 } sdio_slcdate_reg_t; 3141 3142 3143 typedef struct slc_dev_t { 3144 volatile sdio_slcconf0_reg_t slcconf0; 3145 volatile sdio_slc0int_raw_reg_t slc0int_raw; 3146 volatile sdio_slc0int_st_reg_t slc0int_st; 3147 volatile sdio_slc0int_ena_reg_t slc0int_ena; 3148 volatile sdio_slc0int_clr_reg_t slc0int_clr; 3149 volatile sdio_slc1int_raw_reg_t slc1int_raw; 3150 volatile sdio_slc1int_st_reg_t slc1int_st; 3151 volatile sdio_slc1int_ena_reg_t slc1int_ena; 3152 volatile sdio_slc1int_clr_reg_t slc1int_clr; 3153 volatile sdio_slcrx_status_reg_t slcrx_status; 3154 volatile sdio_slc0rxfifo_push_reg_t slc0rxfifo_push; 3155 volatile sdio_slc1rxfifo_push_reg_t slc1rxfifo_push; 3156 volatile sdio_slctx_status_reg_t slctx_status; 3157 volatile sdio_slc0txfifo_pop_reg_t slc0txfifo_pop; 3158 volatile sdio_slc1txfifo_pop_reg_t slc1txfifo_pop; 3159 volatile sdio_slc0rx_link_reg_t slc0rx_link; 3160 volatile sdio_slc0rx_link_addr_reg_t slc0rx_link_addr; 3161 volatile sdio_slc0tx_link_reg_t slc0tx_link; 3162 volatile sdio_slc0tx_link_addr_reg_t slc0tx_link_addr; 3163 volatile sdio_slc1rx_link_reg_t slc1rx_link; 3164 volatile sdio_slc1rx_link_addr_reg_t slc1rx_link_addr; 3165 volatile sdio_slc1tx_link_reg_t slc1tx_link; 3166 volatile sdio_slc1tx_link_addr_reg_t slc1tx_link_addr; 3167 volatile sdio_slcintvec_tohost_reg_t slcintvec_tohost; 3168 volatile sdio_slc0token0_reg_t slc0token0; 3169 volatile sdio_slc0token1_reg_t slc0token1; 3170 volatile sdio_slc1token0_reg_t slc1token0; 3171 volatile sdio_slc1token1_reg_t slc1token1; 3172 volatile sdio_slcconf1_reg_t slcconf1; 3173 volatile sdio_slc0_state0_reg_t slc0_state0; 3174 volatile sdio_slc0_state1_reg_t slc0_state1; 3175 volatile sdio_slc1_state0_reg_t slc1_state0; 3176 volatile sdio_slc1_state1_reg_t slc1_state1; 3177 volatile sdio_slcbridge_conf_reg_t slcbridge_conf; 3178 volatile sdio_slc0_to_eof_des_addr_reg_t slc0_to_eof_des_addr; 3179 volatile sdio_slc0_tx_eof_des_addr_reg_t slc0_tx_eof_des_addr; 3180 volatile sdio_slc0_to_eof_bfr_des_addr_reg_t slc0_to_eof_bfr_des_addr; 3181 volatile sdio_slc1_to_eof_des_addr_reg_t slc1_to_eof_des_addr; 3182 volatile sdio_slc1_tx_eof_des_addr_reg_t slc1_tx_eof_des_addr; 3183 volatile sdio_slc1_to_eof_bfr_des_addr_reg_t slc1_to_eof_bfr_des_addr; 3184 volatile sdio_slc_ahb_test_reg_t slc_ahb_test; 3185 volatile sdio_slc_sdio_st_reg_t slc_sdio_st; 3186 volatile sdio_slc_rx_dscr_conf_reg_t slc_rx_dscr_conf; 3187 volatile sdio_slc0_txlink_dscr_reg_t slc0_txlink_dscr; 3188 volatile sdio_slc0_txlink_dscr_bf0_reg_t slc0_txlink_dscr_bf0; 3189 volatile sdio_slc0_txlink_dscr_bf1_reg_t slc0_txlink_dscr_bf1; 3190 volatile sdio_slc0_rxlink_dscr_reg_t slc0_rxlink_dscr; 3191 volatile sdio_slc0_rxlink_dscr_bf0_reg_t slc0_rxlink_dscr_bf0; 3192 volatile sdio_slc0_rxlink_dscr_bf1_reg_t slc0_rxlink_dscr_bf1; 3193 volatile sdio_slc1_txlink_dscr_reg_t slc1_txlink_dscr; 3194 volatile sdio_slc1_txlink_dscr_bf0_reg_t slc1_txlink_dscr_bf0; 3195 volatile sdio_slc1_txlink_dscr_bf1_reg_t slc1_txlink_dscr_bf1; 3196 volatile sdio_slc1_rxlink_dscr_reg_t slc1_rxlink_dscr; 3197 volatile sdio_slc1_rxlink_dscr_bf0_reg_t slc1_rxlink_dscr_bf0; 3198 volatile sdio_slc1_rxlink_dscr_bf1_reg_t slc1_rxlink_dscr_bf1; 3199 volatile sdio_slc0_tx_erreof_des_addr_reg_t slc0_tx_erreof_des_addr; 3200 volatile sdio_slc1_tx_erreof_des_addr_reg_t slc1_tx_erreof_des_addr; 3201 volatile sdio_slc_token_lat_reg_t slc_token_lat; 3202 volatile sdio_slc_tx_dscr_conf_reg_t slc_tx_dscr_conf; 3203 volatile sdio_slc_cmd_infor0_reg_t slc_cmd_infor0; 3204 volatile sdio_slc_cmd_infor1_reg_t slc_cmd_infor1; 3205 volatile sdio_slc0_len_conf_reg_t slc0_len_conf; 3206 volatile sdio_slc0_length_reg_t slc0_length; 3207 volatile sdio_slc0_txpkt_h_dscr_reg_t slc0_txpkt_h_dscr; 3208 volatile sdio_slc0_txpkt_e_dscr_reg_t slc0_txpkt_e_dscr; 3209 volatile sdio_slc0_rxpkt_h_dscr_reg_t slc0_rxpkt_h_dscr; 3210 volatile sdio_slc0_rxpkt_e_dscr_reg_t slc0_rxpkt_e_dscr; 3211 volatile sdio_slc0_txpktu_h_dscr_reg_t slc0_txpktu_h_dscr; 3212 volatile sdio_slc0_txpktu_e_dscr_reg_t slc0_txpktu_e_dscr; 3213 volatile sdio_slc0_rxpktu_h_dscr_reg_t slc0_rxpktu_h_dscr; 3214 volatile sdio_slc0_rxpktu_e_dscr_reg_t slc0_rxpktu_e_dscr; 3215 volatile sdio_slc_seq_position_reg_t slc_seq_position; 3216 volatile sdio_slc0_dscr_rec_conf_reg_t slc0_dscr_rec_conf; 3217 volatile sdio_slc_sdio_crc_st0_reg_t slc_sdio_crc_st0; 3218 volatile sdio_slc_sdio_crc_st1_reg_t slc_sdio_crc_st1; 3219 volatile sdio_slc0_eof_start_des_reg_t slc0_eof_start_des; 3220 volatile sdio_slc0_push_dscr_addr_reg_t slc0_push_dscr_addr; 3221 volatile sdio_slc0_done_dscr_addr_reg_t slc0_done_dscr_addr; 3222 volatile sdio_slc0_sub_start_des_reg_t slc0_sub_start_des; 3223 volatile sdio_slc0_dscr_cnt_reg_t slc0_dscr_cnt; 3224 volatile sdio_slc0_len_lim_conf_reg_t slc0_len_lim_conf; 3225 volatile sdio_slc0int_st1_reg_t slc0int_st1; 3226 volatile sdio_slc0int_ena1_reg_t slc0int_ena1; 3227 volatile sdio_slc1int_st1_reg_t slc1int_st1; 3228 volatile sdio_slc1int_ena1_reg_t slc1int_ena1; 3229 volatile sdio_slc0_tx_sharemem_start_reg_t slc0_tx_sharemem_start; 3230 volatile sdio_slc0_tx_sharemem_end_reg_t slc0_tx_sharemem_end; 3231 volatile sdio_slc0_rx_sharemem_start_reg_t slc0_rx_sharemem_start; 3232 volatile sdio_slc0_rx_sharemem_end_reg_t slc0_rx_sharemem_end; 3233 volatile sdio_slc1_tx_sharemem_start_reg_t slc1_tx_sharemem_start; 3234 volatile sdio_slc1_tx_sharemem_end_reg_t slc1_tx_sharemem_end; 3235 volatile sdio_slc1_rx_sharemem_start_reg_t slc1_rx_sharemem_start; 3236 volatile sdio_slc1_rx_sharemem_end_reg_t slc1_rx_sharemem_end; 3237 volatile sdio_hda_tx_sharemem_start_reg_t hda_tx_sharemem_start; 3238 volatile sdio_hda_rx_sharemem_start_reg_t hda_rx_sharemem_start; 3239 volatile sdio_slc_burst_len_reg_t slc_burst_len; 3240 uint32_t reserved_180[30]; 3241 volatile sdio_slcdate_reg_t slcdate; 3242 volatile sdio_slcid_reg_t slcid; 3243 } slc_dev_t; 3244 3245 extern slc_dev_t SLC; 3246 3247 #ifndef __cplusplus 3248 _Static_assert(sizeof(slc_dev_t) == 0x200, "Invalid size of slc_dev_t structure"); 3249 #endif 3250 3251 #ifdef __cplusplus 3252 } 3253 #endif 3254
