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Searched refs:sclk_sel (Results 1 – 24 of 24) sorted by relevance

/hal_espressif-latest/components/hal/esp32s3/include/hal/
Duart_ll.h108 hw->clk_conf.sclk_sel = 1; in uart_ll_set_sclk()
111 hw->clk_conf.sclk_sel = 2; in uart_ll_set_sclk()
114 hw->clk_conf.sclk_sel = 3; in uart_ll_set_sclk()
129 switch (hw->clk_conf.sclk_sel) { in uart_ll_get_sclk()
Drmt_ll.h121 dev->sys_conf.sclk_sel = 1; in rmt_ll_set_group_clock_src()
124 dev->sys_conf.sclk_sel = 2; in rmt_ll_set_group_clock_src()
127 dev->sys_conf.sclk_sel = 3; in rmt_ll_set_group_clock_src()
815 switch (dev->sys_conf.sclk_sel) { in rmt_ll_get_group_clock_src()
Di2c_ll.h661 hw->clk_conf.sclk_sel = (src_clk == I2C_CLK_SRC_RC_FAST) ? 1 : 0; in i2c_ll_set_source_clk()
/hal_espressif-latest/components/hal/esp32c2/include/hal/
Duart_ll.h133 hw->clk_conf.sclk_sel = 1; in uart_ll_set_sclk()
136 hw->clk_conf.sclk_sel = 2; in uart_ll_set_sclk()
139 hw->clk_conf.sclk_sel = 3; in uart_ll_set_sclk()
154 switch (hw->clk_conf.sclk_sel) { in uart_ll_get_sclk()
Di2c_ll.h651 hw->clk_conf.sclk_sel = (src_clk == I2C_CLK_SRC_RC_FAST) ? 1 : 0; in i2c_ll_set_source_clk()
/hal_espressif-latest/components/hal/esp32c3/include/hal/
Drmt_ll.h121 dev->sys_conf.sclk_sel = 1; in rmt_ll_set_group_clock_src()
124 dev->sys_conf.sclk_sel = 2; in rmt_ll_set_group_clock_src()
127 dev->sys_conf.sclk_sel = 3; in rmt_ll_set_group_clock_src()
777 switch (dev->sys_conf.sclk_sel) { in rmt_ll_get_group_clock_src()
Duart_ll.h134 hw->clk_conf.sclk_sel = 1; in uart_ll_set_sclk()
137 hw->clk_conf.sclk_sel = 2; in uart_ll_set_sclk()
140 hw->clk_conf.sclk_sel = 3; in uart_ll_set_sclk()
155 switch (hw->clk_conf.sclk_sel) { in uart_ll_get_sclk()
Di2c_ll.h669 hw->clk_conf.sclk_sel = (src_clk == I2C_CLK_SRC_RC_FAST) ? 1 : 0; in i2c_ll_set_source_clk()
/hal_espressif-latest/components/hal/esp32c6/include/hal/
Duart_ll.h146 UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 1); in uart_ll_set_sclk()
149 UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 2); in uart_ll_set_sclk()
152 UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 3); in uart_ll_set_sclk()
167 switch (UART_LL_PCR_REG_GET(hw, sclk_conf, sclk_sel)) { in uart_ll_get_sclk()
/hal_espressif-latest/components/hal/esp32h2/include/hal/
Duart_ll.h167 UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 1); in uart_ll_set_sclk()
170 UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 2); in uart_ll_set_sclk()
173 UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 3); in uart_ll_set_sclk()
188 switch (UART_LL_PCR_REG_GET(hw, sclk_conf, sclk_sel)) { in uart_ll_get_sclk()
/hal_espressif-latest/components/soc/esp32c6/include/soc/
Drmt_struct.h249 uint32_t sclk_sel:2; member
Dlp_i2c_struct.h347 uint32_t sclk_sel:1; member
Di2c_struct.h385 uint32_t sclk_sel:1; member
Duart_struct.h898 uint32_t sclk_sel:2; member
/hal_espressif-latest/components/soc/esp32h2/include/soc/
Drmt_struct.h249 uint32_t sclk_sel:2; member
Di2c_struct.h385 uint32_t sclk_sel:1; member
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Drmt_struct.h213 uint32_t sclk_sel: 2; member
Di2c_struct.h287 uint32_t sclk_sel : 1; member
Duart_struct.h372 …uint32_t sclk_sel: 2; /*UART clock source select. 1: 80Mhz 2: 8Mhz 3: XTAL… member
/hal_espressif-latest/components/soc/esp32c2/include/soc/
Di2c_struct.h356 uint32_t sclk_sel:1; member
Duart_struct.h373 …uint32_t sclk_sel : 2; /*UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: … member
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Di2c_struct.h394 uint32_t sclk_sel:1; member
Drmt_struct.h274 uint32_t sclk_sel: 2; member
Duart_struct.h846 uint32_t sclk_sel:2; member