1 /** 2 * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #ifdef __cplusplus 10 extern "C" { 11 #endif 12 13 /** Group: PGM Data Register */ 14 /** Type of pgm_data0 register 15 * Register 0 that stores data to be programmed. 16 */ 17 typedef union { 18 struct { 19 /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; 20 * The content of the 0th 32-bit data to be programmed. 21 */ 22 uint32_t pgm_data_0:32; 23 }; 24 uint32_t val; 25 } efuse_pgm_data0_reg_t; 26 27 /** Type of pgm_data1 register 28 * Register 1 that stores data to be programmed. 29 */ 30 typedef union { 31 struct { 32 /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0; 33 * The content of the 1st 32-bit data to be programmed. 34 */ 35 uint32_t pgm_data_1:32; 36 }; 37 uint32_t val; 38 } efuse_pgm_data1_reg_t; 39 40 /** Type of pgm_data2 register 41 * Register 2 that stores data to be programmed. 42 */ 43 typedef union { 44 struct { 45 /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0; 46 * The content of the 2nd 32-bit data to be programmed. 47 */ 48 uint32_t pgm_data_2:32; 49 }; 50 uint32_t val; 51 } efuse_pgm_data2_reg_t; 52 53 /** Type of pgm_data3 register 54 * Register 3 that stores data to be programmed. 55 */ 56 typedef union { 57 struct { 58 /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0; 59 * The content of the 3rd 32-bit data to be programmed. 60 */ 61 uint32_t pgm_data_3:32; 62 }; 63 uint32_t val; 64 } efuse_pgm_data3_reg_t; 65 66 /** Type of pgm_data4 register 67 * Register 4 that stores data to be programmed. 68 */ 69 typedef union { 70 struct { 71 /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0; 72 * The content of the 4th 32-bit data to be programmed. 73 */ 74 uint32_t pgm_data_4:32; 75 }; 76 uint32_t val; 77 } efuse_pgm_data4_reg_t; 78 79 /** Type of pgm_data5 register 80 * Register 5 that stores data to be programmed. 81 */ 82 typedef union { 83 struct { 84 /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0; 85 * The content of the 5th 32-bit data to be programmed. 86 */ 87 uint32_t pgm_data_5:32; 88 }; 89 uint32_t val; 90 } efuse_pgm_data5_reg_t; 91 92 /** Type of pgm_data6 register 93 * Register 6 that stores data to be programmed. 94 */ 95 typedef union { 96 struct { 97 /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0; 98 * The content of the 6th 32-bit data to be programmed. 99 */ 100 uint32_t pgm_data_6:32; 101 }; 102 uint32_t val; 103 } efuse_pgm_data6_reg_t; 104 105 /** Type of pgm_data7 register 106 * Register 7 that stores data to be programmed. 107 */ 108 typedef union { 109 struct { 110 /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0; 111 * The content of the 7th 32-bit data to be programmed. 112 */ 113 uint32_t pgm_data_7:32; 114 }; 115 uint32_t val; 116 } efuse_pgm_data7_reg_t; 117 118 /** Type of pgm_check_value0 register 119 * Register 0 that stores the RS code to be programmed. 120 */ 121 typedef union { 122 struct { 123 /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0; 124 * The content of the 0th 32-bit RS code to be programmed. 125 */ 126 uint32_t pgm_rs_data_0:32; 127 }; 128 uint32_t val; 129 } efuse_pgm_check_value0_reg_t; 130 131 /** Type of pgm_check_value1 register 132 * Register 1 that stores the RS code to be programmed. 133 */ 134 typedef union { 135 struct { 136 /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0; 137 * The content of the 1st 32-bit RS code to be programmed. 138 */ 139 uint32_t pgm_rs_data_1:32; 140 }; 141 uint32_t val; 142 } efuse_pgm_check_value1_reg_t; 143 144 /** Type of pgm_check_value2 register 145 * Register 2 that stores the RS code to be programmed. 146 */ 147 typedef union { 148 struct { 149 /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0; 150 * The content of the 2nd 32-bit RS code to be programmed. 151 */ 152 uint32_t pgm_rs_data_2:32; 153 }; 154 uint32_t val; 155 } efuse_pgm_check_value2_reg_t; 156 157 158 /** Group: Read Data Register */ 159 /** Type of rd_wr_dis register 160 * BLOCK0 data register 0. 161 */ 162 typedef union { 163 struct { 164 /** wr_dis : RO; bitpos: [31:0]; default: 0; 165 * Disable programming of individual eFuses. 166 */ 167 uint32_t wr_dis:32; 168 }; 169 uint32_t val; 170 } efuse_rd_wr_dis_reg_t; 171 172 /** Type of rd_repeat_data0 register 173 * BLOCK0 data register 1. 174 */ 175 typedef union { 176 struct { 177 /** rd_dis : RO; bitpos: [6:0]; default: 0; 178 * Set this bit to disable reading from BlOCK4-10. 179 */ 180 uint32_t rd_dis:7; 181 /** dis_rtc_ram_boot : RO; bitpos: [7]; default: 0; 182 * Set this bit to disable boot from RTC RAM. 183 */ 184 uint32_t dis_rtc_ram_boot:1; 185 /** dis_icache : RO; bitpos: [8]; default: 0; 186 * Set this bit to disable Icache. 187 */ 188 uint32_t dis_icache:1; 189 /** dis_usb_jtag : RO; bitpos: [9]; default: 0; 190 * Set this bit to disable function of usb switch to jtag in module of usb device. 191 */ 192 uint32_t dis_usb_jtag:1; 193 /** dis_download_icache : RO; bitpos: [10]; default: 0; 194 * Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, 195 * 7). 196 */ 197 uint32_t dis_download_icache:1; 198 /** dis_usb_serial_jtag : RO; bitpos: [11]; default: 0; 199 * Represents whether USB-Serial-JTAG is disabled. 1: Disabled. 0: Enabled 200 */ 201 uint32_t dis_usb_serial_jtag:1; 202 /** dis_force_download : RO; bitpos: [12]; default: 0; 203 * Set this bit to disable the function that forces chip into download mode. 204 */ 205 uint32_t dis_force_download:1; 206 /** rpt4_reserved6 : RO; bitpos: [13]; default: 0; 207 * Reserved (used for four backups method). 208 */ 209 uint32_t rpt4_reserved6:1; 210 /** dis_twai : RO; bitpos: [14]; default: 0; 211 * Set this bit to disable CAN function. 212 */ 213 uint32_t dis_twai:1; 214 /** jtag_sel_enable : RO; bitpos: [15]; default: 0; 215 * Set this bit to enable selection between usb_to_jtag and pad_to_jtag through 216 * strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0. 217 */ 218 uint32_t jtag_sel_enable:1; 219 /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0; 220 * Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG 221 * can be enabled in HMAC module. 222 */ 223 uint32_t soft_dis_jtag:3; 224 /** dis_pad_jtag : RO; bitpos: [19]; default: 0; 225 * Set this bit to disable JTAG in the hard way. JTAG is disabled permanently. 226 */ 227 uint32_t dis_pad_jtag:1; 228 /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0; 229 * Set this bit to disable flash encryption when in download boot modes. 230 */ 231 uint32_t dis_download_manual_encrypt:1; 232 /** usb_drefh : RO; bitpos: [22:21]; default: 0; 233 * Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored 234 * in eFuse. 235 */ 236 uint32_t usb_drefh:2; 237 /** usb_drefl : RO; bitpos: [24:23]; default: 0; 238 * Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, 239 * stored in eFuse. 240 */ 241 uint32_t usb_drefl:2; 242 /** usb_exchg_pins : RO; bitpos: [25]; default: 0; 243 * Set this bit to exchange USB D+ and D- pins. 244 */ 245 uint32_t usb_exchg_pins:1; 246 /** vdd_spi_as_gpio : RO; bitpos: [26]; default: 0; 247 * Set this bit to vdd spi pin function as gpio. 248 */ 249 uint32_t vdd_spi_as_gpio:1; 250 /** btlc_gpio_enable : RO; bitpos: [28:27]; default: 0; 251 * Enable btlc gpio. 252 */ 253 uint32_t btlc_gpio_enable:2; 254 /** powerglitch_en : RO; bitpos: [29]; default: 0; 255 * Set this bit to enable power glitch function. 256 */ 257 uint32_t powerglitch_en:1; 258 /** power_glitch_dsense : RO; bitpos: [31:30]; default: 0; 259 * Sample delay configuration of power glitch. 260 */ 261 uint32_t power_glitch_dsense:2; 262 }; 263 uint32_t val; 264 } efuse_rd_repeat_data0_reg_t; 265 266 /** Type of rd_repeat_data1 register 267 * BLOCK0 data register 2. 268 */ 269 typedef union { 270 struct { 271 /** rpt4_reserved2 : RO; bitpos: [15:0]; default: 0; 272 * Reserved (used for four backups method). 273 */ 274 uint32_t rpt4_reserved2:16; 275 /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0; 276 * Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 277 * 80000. 2: 160000. 3:320000. 278 */ 279 uint32_t wdt_delay_sel:2; 280 /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0; 281 * Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even 282 * number of 1: disable. 283 */ 284 uint32_t spi_boot_crypt_cnt:3; 285 /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0; 286 * Set this bit to enable revoking first secure boot key. 287 */ 288 uint32_t secure_boot_key_revoke0:1; 289 /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0; 290 * Set this bit to enable revoking second secure boot key. 291 */ 292 uint32_t secure_boot_key_revoke1:1; 293 /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0; 294 * Set this bit to enable revoking third secure boot key. 295 */ 296 uint32_t secure_boot_key_revoke2:1; 297 /** key_purpose_0 : RO; bitpos: [27:24]; default: 0; 298 * Purpose of Key0. 299 */ 300 uint32_t key_purpose_0:4; 301 /** key_purpose_1 : RO; bitpos: [31:28]; default: 0; 302 * Purpose of Key1. 303 */ 304 uint32_t key_purpose_1:4; 305 }; 306 uint32_t val; 307 } efuse_rd_repeat_data1_reg_t; 308 309 /** Type of rd_repeat_data2 register 310 * BLOCK0 data register 3. 311 */ 312 typedef union { 313 struct { 314 /** key_purpose_2 : RO; bitpos: [3:0]; default: 0; 315 * Purpose of Key2. 316 */ 317 uint32_t key_purpose_2:4; 318 /** key_purpose_3 : RO; bitpos: [7:4]; default: 0; 319 * Purpose of Key3. 320 */ 321 uint32_t key_purpose_3:4; 322 /** key_purpose_4 : RO; bitpos: [11:8]; default: 0; 323 * Purpose of Key4. 324 */ 325 uint32_t key_purpose_4:4; 326 /** key_purpose_5 : RO; bitpos: [15:12]; default: 0; 327 * Purpose of Key5. 328 */ 329 uint32_t key_purpose_5:4; 330 /** rpt4_reserved3 : RO; bitpos: [19:16]; default: 0; 331 * Reserved (used for four backups method). 332 */ 333 uint32_t rpt4_reserved3:4; 334 /** secure_boot_en : RO; bitpos: [20]; default: 0; 335 * Set this bit to enable secure boot. 336 */ 337 uint32_t secure_boot_en:1; 338 /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0; 339 * Set this bit to enable revoking aggressive secure boot. 340 */ 341 uint32_t secure_boot_aggressive_revoke:1; 342 /** rpt4_reserved0 : RO; bitpos: [27:22]; default: 0; 343 * Reserved (used for four backups method). 344 */ 345 uint32_t rpt4_reserved0:6; 346 /** flash_tpuw : RO; bitpos: [31:28]; default: 0; 347 * Configures flash waiting time after power-up, in unit of ms. If the value is less 348 * than 15, the waiting time is the configurable value; Otherwise, the waiting time is 349 * twice the configurable value. 350 */ 351 uint32_t flash_tpuw:4; 352 }; 353 uint32_t val; 354 } efuse_rd_repeat_data2_reg_t; 355 356 /** Type of rd_repeat_data3 register 357 * BLOCK0 data register 4. 358 */ 359 typedef union { 360 struct { 361 /** dis_download_mode : RO; bitpos: [0]; default: 0; 362 * Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7). 363 */ 364 uint32_t dis_download_mode:1; 365 /** dis_direct_boot : RO; bitpos: [1]; default: 0; 366 * Disable direct boot mode 367 */ 368 uint32_t dis_direct_boot:1; 369 /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0; 370 * Represents whether USB printing is disabled or enabled. 1: Disabled. 0: Enabled 371 */ 372 uint32_t dis_usb_serial_jtag_rom_print:1; 373 /** flash_ecc_mode : RO; bitpos: [3]; default: 0; 374 * Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would 375 * use 16to17 byte mode. 376 */ 377 uint32_t flash_ecc_mode:1; 378 /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0; 379 * Disable UART download mode through USB-Serial-JTAG 380 */ 381 uint32_t dis_usb_serial_jtag_download_mode:1; 382 /** enable_security_download : RO; bitpos: [5]; default: 0; 383 * Set this bit to enable secure UART download mode. 384 */ 385 uint32_t enable_security_download:1; 386 /** uart_print_control : RO; bitpos: [7:6]; default: 0; 387 * Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 388 * is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled. 389 */ 390 uint32_t uart_print_control:2; 391 /** pin_power_selection : RO; bitpos: [8]; default: 0; 392 * GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI. 393 */ 394 uint32_t pin_power_selection:1; 395 /** flash_type : RO; bitpos: [9]; default: 0; 396 * Set the maximum lines of SPI flash. 0: four lines. 1: eight lines. 397 */ 398 uint32_t flash_type:1; 399 /** flash_page_size : RO; bitpos: [11:10]; default: 0; 400 * Set Flash page size. 401 */ 402 uint32_t flash_page_size:2; 403 /** flash_ecc_en : RO; bitpos: [12]; default: 0; 404 * Set 1 to enable ECC for flash boot. 405 */ 406 uint32_t flash_ecc_en:1; 407 /** force_send_resume : RO; bitpos: [13]; default: 0; 408 * Set this bit to force ROM code to send a resume command during SPI boot. 409 */ 410 uint32_t force_send_resume:1; 411 /** secure_version : RO; bitpos: [29:14]; default: 0; 412 * Secure version (used by ESP-IDF anti-rollback feature). 413 */ 414 uint32_t secure_version:16; 415 /** reserved_0_158 : R; bitpos: [30]; default: 0; 416 * reserved 417 */ 418 uint32_t reserved_0_158:1; 419 /** err_rst_enable : R; bitpos: [31]; default: 0; 420 * Use BLOCK0 to check error record registers 421 */ 422 uint32_t err_rst_enable:1; 423 }; 424 uint32_t val; 425 } efuse_rd_repeat_data3_reg_t; 426 427 /** Type of rd_repeat_data4 register 428 * BLOCK0 data register 5. 429 */ 430 typedef union { 431 struct { 432 /** disable_wafer_version_major : R; bitpos: [0]; default: 0; 433 * Disables check of wafer version major 434 */ 435 uint32_t disable_wafer_version_major:1; 436 /** disable_blk_version_major : R; bitpos: [1]; default: 0; 437 * Disables check of blk version major 438 */ 439 uint32_t disable_blk_version_major:1; 440 /** reserved_0_162 : R; bitpos: [23:2]; default: 0; 441 * reserved 442 */ 443 uint32_t reserved_0_162:22; 444 uint32_t reserved_24:8; 445 }; 446 uint32_t val; 447 } efuse_rd_repeat_data4_reg_t; 448 449 /** Type of rd_mac_spi_sys_0 register 450 * BLOCK1 data register 0. 451 */ 452 typedef union { 453 struct { 454 /** mac_0 : RO; bitpos: [31:0]; default: 0; 455 * Stores the low 32 bits of MAC address. 456 */ 457 uint32_t mac_0:32; 458 }; 459 uint32_t val; 460 } efuse_rd_mac_spi_sys_0_reg_t; 461 462 /** Type of rd_mac_spi_sys_1 register 463 * BLOCK1 data register 1. 464 */ 465 typedef union { 466 struct { 467 /** mac_1 : RO; bitpos: [15:0]; default: 0; 468 * Stores the high 16 bits of MAC address. 469 */ 470 uint32_t mac_1:16; 471 /** spi_pad_config_clk : R; bitpos: [21:16]; default: 0; 472 * SPI PAD CLK 473 */ 474 uint32_t spi_pad_config_clk:6; 475 /** spi_pad_config_q : R; bitpos: [27:22]; default: 0; 476 * SPI PAD Q(D1) 477 */ 478 uint32_t spi_pad_config_q:6; 479 /** spi_pad_config_d : R; bitpos: [31:28]; default: 0; 480 * SPI PAD D(D0) 481 */ 482 uint32_t spi_pad_config_d:4; 483 }; 484 uint32_t val; 485 } efuse_rd_mac_spi_sys_1_reg_t; 486 487 /** Type of rd_mac_spi_sys_2 register 488 * BLOCK1 data register 2. 489 */ 490 typedef union { 491 struct { 492 /** spi_pad_config_d_1 : R; bitpos: [1:0]; default: 0; 493 * SPI PAD D(D0) 494 */ 495 uint32_t spi_pad_config_d_1:2; 496 /** spi_pad_config_cs : R; bitpos: [7:2]; default: 0; 497 * SPI PAD CS 498 */ 499 uint32_t spi_pad_config_cs:6; 500 /** spi_pad_config_hd : R; bitpos: [13:8]; default: 0; 501 * SPI PAD HD(D3) 502 */ 503 uint32_t spi_pad_config_hd:6; 504 /** spi_pad_config_wp : R; bitpos: [19:14]; default: 0; 505 * SPI PAD WP(D2) 506 */ 507 uint32_t spi_pad_config_wp:6; 508 /** spi_pad_config_dqs : R; bitpos: [25:20]; default: 0; 509 * SPI PAD DQS 510 */ 511 uint32_t spi_pad_config_dqs:6; 512 /** spi_pad_config_d4 : R; bitpos: [31:26]; default: 0; 513 * SPI PAD D4 514 */ 515 uint32_t spi_pad_config_d4:6; 516 }; 517 uint32_t val; 518 } efuse_rd_mac_spi_sys_2_reg_t; 519 520 /** Type of rd_mac_spi_sys_3 register 521 * BLOCK1 data register 3. 522 */ 523 typedef union { 524 struct { 525 /** spi_pad_config_d5 : R; bitpos: [5:0]; default: 0; 526 * SPI PAD D5 527 */ 528 uint32_t spi_pad_config_d5:6; 529 /** spi_pad_config_d6 : R; bitpos: [11:6]; default: 0; 530 * SPI PAD D6 531 */ 532 uint32_t spi_pad_config_d6:6; 533 /** spi_pad_config_d7 : R; bitpos: [17:12]; default: 0; 534 * SPI PAD D7 535 */ 536 uint32_t spi_pad_config_d7:6; 537 /** wafer_version_minor_lo : R; bitpos: [20:18]; default: 0; 538 * WAFER_VERSION_MINOR least significant bits 539 */ 540 uint32_t wafer_version_minor_lo:3; 541 /** pkg_version : R; bitpos: [23:21]; default: 0; 542 * Package version 543 */ 544 uint32_t pkg_version:3; 545 /** blk_version_minor : R; bitpos: [26:24]; default: 0; 546 * BLK_VERSION_MINOR 547 */ 548 uint32_t blk_version_minor:3; 549 /** reserved_1_123 : R; bitpos: [31:27]; default: 0; 550 * reserved 551 */ 552 uint32_t reserved_1_123:5; 553 }; 554 uint32_t val; 555 } efuse_rd_mac_spi_sys_3_reg_t; 556 557 /** Type of rd_mac_spi_sys_4 register 558 * BLOCK1 data register 4. 559 */ 560 typedef union { 561 struct { 562 /** reserved_1_128 : R; bitpos: [6:0]; default: 0; 563 * reserved 564 */ 565 uint32_t reserved_1_128:7; 566 /** k_rtc_ldo : R; bitpos: [13:7]; default: 0; 567 * BLOCK1 K_RTC_LDO 568 */ 569 uint32_t k_rtc_ldo:7; 570 /** k_dig_ldo : R; bitpos: [20:14]; default: 0; 571 * BLOCK1 K_DIG_LDO 572 */ 573 uint32_t k_dig_ldo:7; 574 /** v_rtc_dbias20 : R; bitpos: [28:21]; default: 0; 575 * BLOCK1 voltage of rtc dbias20 576 */ 577 uint32_t v_rtc_dbias20:8; 578 /** v_dig_dbias20 : R; bitpos: [31:29]; default: 0; 579 * BLOCK1 voltage of digital dbias20 580 */ 581 uint32_t v_dig_dbias20:3; 582 }; 583 uint32_t val; 584 } efuse_rd_mac_spi_sys_4_reg_t; 585 586 /** Type of rd_mac_spi_sys_5 register 587 * BLOCK1 data register 5. 588 */ 589 typedef union { 590 struct { 591 /** v_dig_dbias20_1 : R; bitpos: [4:0]; default: 0; 592 * BLOCK1 voltage of digital dbias20 593 */ 594 uint32_t v_dig_dbias20_1:5; 595 /** dig_dbias_hvt : R; bitpos: [9:5]; default: 0; 596 * BLOCK1 digital dbias when hvt 597 */ 598 uint32_t dig_dbias_hvt:5; 599 /** thres_hvt : R; bitpos: [19:10]; default: 0; 600 * BLOCK1 pvt threshold when hvt 601 */ 602 uint32_t thres_hvt:10; 603 /** reserved_1_180 : R; bitpos: [22:20]; default: 0; 604 * reserved 605 */ 606 uint32_t reserved_1_180:3; 607 /** wafer_version_minor_hi : R; bitpos: [23]; default: 0; 608 * WAFER_VERSION_MINOR most significant bit 609 */ 610 uint32_t wafer_version_minor_hi:1; 611 /** wafer_version_major : R; bitpos: [25:24]; default: 0; 612 * WAFER_VERSION_MAJOR 613 */ 614 uint32_t wafer_version_major:2; 615 /** reserved_1_186 : R; bitpos: [31:26]; default: 0; 616 * reserved 617 */ 618 uint32_t reserved_1_186:6; 619 }; 620 uint32_t val; 621 } efuse_rd_mac_spi_sys_5_reg_t; 622 623 /** Type of rd_sys_part1_data0 register 624 * Register 0 of BLOCK2 (system). 625 */ 626 typedef union { 627 struct { 628 /** optional_unique_id : R; bitpos: [31:0]; default: 0; 629 * Optional unique 128-bit ID 630 */ 631 uint32_t optional_unique_id:32; 632 }; 633 uint32_t val; 634 } efuse_rd_sys_part1_data0_reg_t; 635 636 /** Type of rd_sys_part1_data1 register 637 * Register 1 of BLOCK2 (system). 638 */ 639 typedef union { 640 struct { 641 /** optional_unique_id_1 : R; bitpos: [31:0]; default: 0; 642 * Optional unique 128-bit ID 643 */ 644 uint32_t optional_unique_id_1:32; 645 }; 646 uint32_t val; 647 } efuse_rd_sys_part1_data1_reg_t; 648 649 /** Type of rd_sys_part1_data2 register 650 * Register 2 of BLOCK2 (system). 651 */ 652 typedef union { 653 struct { 654 /** optional_unique_id_2 : R; bitpos: [31:0]; default: 0; 655 * Optional unique 128-bit ID 656 */ 657 uint32_t optional_unique_id_2:32; 658 }; 659 uint32_t val; 660 } efuse_rd_sys_part1_data2_reg_t; 661 662 /** Type of rd_sys_part1_data3 register 663 * Register 3 of BLOCK2 (system). 664 */ 665 typedef union { 666 struct { 667 /** optional_unique_id_3 : R; bitpos: [31:0]; default: 0; 668 * Optional unique 128-bit ID 669 */ 670 uint32_t optional_unique_id_3:32; 671 }; 672 uint32_t val; 673 } efuse_rd_sys_part1_data3_reg_t; 674 675 /** Type of rd_sys_part1_data4 register 676 * Register 4 of BLOCK2 (system). 677 */ 678 typedef union { 679 struct { 680 /** blk_version_major : R; bitpos: [1:0]; default: 0; 681 * BLK_VERSION_MAJOR of BLOCK2 682 */ 683 uint32_t blk_version_major:2; 684 /** reserved_2_130 : R; bitpos: [2]; default: 0; 685 * reserved 686 */ 687 uint32_t reserved_2_130:1; 688 /** temp_calib : R; bitpos: [11:3]; default: 0; 689 * Temperature calibration data 690 */ 691 uint32_t temp_calib:9; 692 /** ocode : R; bitpos: [19:12]; default: 0; 693 * ADC OCode 694 */ 695 uint32_t ocode:8; 696 /** adc1_init_code_atten0 : R; bitpos: [29:20]; default: 0; 697 * ADC1 init code at atten0 698 */ 699 uint32_t adc1_init_code_atten0:10; 700 /** adc1_init_code_atten1 : R; bitpos: [31:30]; default: 0; 701 * ADC1 init code at atten1 702 */ 703 uint32_t adc1_init_code_atten1:2; 704 }; 705 uint32_t val; 706 } efuse_rd_sys_part1_data4_reg_t; 707 708 /** Type of rd_sys_part1_data5 register 709 * Register 5 of BLOCK2 (system). 710 */ 711 typedef union { 712 struct { 713 /** adc1_init_code_atten1_1 : R; bitpos: [7:0]; default: 0; 714 * ADC1 init code at atten1 715 */ 716 uint32_t adc1_init_code_atten1_1:8; 717 /** adc1_init_code_atten2 : R; bitpos: [17:8]; default: 0; 718 * ADC1 init code at atten2 719 */ 720 uint32_t adc1_init_code_atten2:10; 721 /** adc1_init_code_atten3 : R; bitpos: [27:18]; default: 0; 722 * ADC1 init code at atten3 723 */ 724 uint32_t adc1_init_code_atten3:10; 725 /** adc1_cal_vol_atten0 : R; bitpos: [31:28]; default: 0; 726 * ADC1 calibration voltage at atten0 727 */ 728 uint32_t adc1_cal_vol_atten0:4; 729 }; 730 uint32_t val; 731 } efuse_rd_sys_part1_data5_reg_t; 732 733 /** Type of rd_sys_part1_data6 register 734 * Register 6 of BLOCK2 (system). 735 */ 736 typedef union { 737 struct { 738 /** adc1_cal_vol_atten0_1 : R; bitpos: [5:0]; default: 0; 739 * ADC1 calibration voltage at atten0 740 */ 741 uint32_t adc1_cal_vol_atten0_1:6; 742 /** adc1_cal_vol_atten1 : R; bitpos: [15:6]; default: 0; 743 * ADC1 calibration voltage at atten1 744 */ 745 uint32_t adc1_cal_vol_atten1:10; 746 /** adc1_cal_vol_atten2 : R; bitpos: [25:16]; default: 0; 747 * ADC1 calibration voltage at atten2 748 */ 749 uint32_t adc1_cal_vol_atten2:10; 750 /** adc1_cal_vol_atten3 : R; bitpos: [31:26]; default: 0; 751 * ADC1 calibration voltage at atten3 752 */ 753 uint32_t adc1_cal_vol_atten3:6; 754 }; 755 uint32_t val; 756 } efuse_rd_sys_part1_data6_reg_t; 757 758 /** Type of rd_sys_part1_data7 register 759 * Register 7 of BLOCK2 (system). 760 */ 761 typedef union { 762 struct { 763 /** adc1_cal_vol_atten3_1 : R; bitpos: [3:0]; default: 0; 764 * ADC1 calibration voltage at atten3 765 */ 766 uint32_t adc1_cal_vol_atten3_1:4; 767 /** reserved_2_228 : R; bitpos: [31:4]; default: 0; 768 * reserved 769 */ 770 uint32_t reserved_2_228:28; 771 }; 772 uint32_t val; 773 } efuse_rd_sys_part1_data7_reg_t; 774 775 /** Type of rd_usr_data0 register 776 * Register 0 of BLOCK3 (user). 777 */ 778 typedef union { 779 struct { 780 /** usr_data0 : RO; bitpos: [31:0]; default: 0; 781 * Stores the zeroth 32 bits of BLOCK3 (user). 782 */ 783 uint32_t usr_data0:32; 784 }; 785 uint32_t val; 786 } efuse_rd_usr_data0_reg_t; 787 788 /** Type of rd_usr_data1 register 789 * Register 1 of BLOCK3 (user). 790 */ 791 typedef union { 792 struct { 793 /** usr_data1 : RO; bitpos: [31:0]; default: 0; 794 * Stores the first 32 bits of BLOCK3 (user). 795 */ 796 uint32_t usr_data1:32; 797 }; 798 uint32_t val; 799 } efuse_rd_usr_data1_reg_t; 800 801 /** Type of rd_usr_data2 register 802 * Register 2 of BLOCK3 (user). 803 */ 804 typedef union { 805 struct { 806 /** usr_data2 : RO; bitpos: [31:0]; default: 0; 807 * Stores the second 32 bits of BLOCK3 (user). 808 */ 809 uint32_t usr_data2:32; 810 }; 811 uint32_t val; 812 } efuse_rd_usr_data2_reg_t; 813 814 /** Type of rd_usr_data3 register 815 * Register 3 of BLOCK3 (user). 816 */ 817 typedef union { 818 struct { 819 /** usr_data3 : RO; bitpos: [31:0]; default: 0; 820 * Stores the third 32 bits of BLOCK3 (user). 821 */ 822 uint32_t usr_data3:32; 823 }; 824 uint32_t val; 825 } efuse_rd_usr_data3_reg_t; 826 827 /** Type of rd_usr_data4 register 828 * Register 4 of BLOCK3 (user). 829 */ 830 typedef union { 831 struct { 832 /** usr_data4 : RO; bitpos: [31:0]; default: 0; 833 * Stores the fourth 32 bits of BLOCK3 (user). 834 */ 835 uint32_t usr_data4:32; 836 }; 837 uint32_t val; 838 } efuse_rd_usr_data4_reg_t; 839 840 /** Type of rd_usr_data5 register 841 * Register 5 of BLOCK3 (user). 842 */ 843 typedef union { 844 struct { 845 /** usr_data5 : RO; bitpos: [31:0]; default: 0; 846 * Stores the fifth 32 bits of BLOCK3 (user). 847 */ 848 uint32_t usr_data5:32; 849 }; 850 uint32_t val; 851 } efuse_rd_usr_data5_reg_t; 852 853 /** Type of rd_usr_data6 register 854 * Register 6 of BLOCK3 (user). 855 */ 856 typedef union { 857 struct { 858 /** reserved_3_192 : R; bitpos: [7:0]; default: 0; 859 * reserved 860 */ 861 uint32_t reserved_3_192:8; 862 /** custom_mac : R; bitpos: [31:8]; default: 0; 863 * Custom MAC address 864 */ 865 uint32_t custom_mac:24; 866 }; 867 uint32_t val; 868 } efuse_rd_usr_data6_reg_t; 869 870 /** Type of rd_usr_data7 register 871 * Register 7 of BLOCK3 (user). 872 */ 873 typedef union { 874 struct { 875 /** custom_mac_1 : R; bitpos: [23:0]; default: 0; 876 * Custom MAC address 877 */ 878 uint32_t custom_mac_1:24; 879 /** reserved_3_248 : R; bitpos: [31:24]; default: 0; 880 * reserved 881 */ 882 uint32_t reserved_3_248:8; 883 }; 884 uint32_t val; 885 } efuse_rd_usr_data7_reg_t; 886 887 /** Type of rd_key0_data0 register 888 * Register 0 of BLOCK4 (KEY0). 889 */ 890 typedef union { 891 struct { 892 /** key0_data0 : RO; bitpos: [31:0]; default: 0; 893 * Stores the zeroth 32 bits of KEY0. 894 */ 895 uint32_t key0_data0:32; 896 }; 897 uint32_t val; 898 } efuse_rd_key0_data0_reg_t; 899 900 /** Type of rd_key0_data1 register 901 * Register 1 of BLOCK4 (KEY0). 902 */ 903 typedef union { 904 struct { 905 /** key0_data1 : RO; bitpos: [31:0]; default: 0; 906 * Stores the first 32 bits of KEY0. 907 */ 908 uint32_t key0_data1:32; 909 }; 910 uint32_t val; 911 } efuse_rd_key0_data1_reg_t; 912 913 /** Type of rd_key0_data2 register 914 * Register 2 of BLOCK4 (KEY0). 915 */ 916 typedef union { 917 struct { 918 /** key0_data2 : RO; bitpos: [31:0]; default: 0; 919 * Stores the second 32 bits of KEY0. 920 */ 921 uint32_t key0_data2:32; 922 }; 923 uint32_t val; 924 } efuse_rd_key0_data2_reg_t; 925 926 /** Type of rd_key0_data3 register 927 * Register 3 of BLOCK4 (KEY0). 928 */ 929 typedef union { 930 struct { 931 /** key0_data3 : RO; bitpos: [31:0]; default: 0; 932 * Stores the third 32 bits of KEY0. 933 */ 934 uint32_t key0_data3:32; 935 }; 936 uint32_t val; 937 } efuse_rd_key0_data3_reg_t; 938 939 /** Type of rd_key0_data4 register 940 * Register 4 of BLOCK4 (KEY0). 941 */ 942 typedef union { 943 struct { 944 /** key0_data4 : RO; bitpos: [31:0]; default: 0; 945 * Stores the fourth 32 bits of KEY0. 946 */ 947 uint32_t key0_data4:32; 948 }; 949 uint32_t val; 950 } efuse_rd_key0_data4_reg_t; 951 952 /** Type of rd_key0_data5 register 953 * Register 5 of BLOCK4 (KEY0). 954 */ 955 typedef union { 956 struct { 957 /** key0_data5 : RO; bitpos: [31:0]; default: 0; 958 * Stores the fifth 32 bits of KEY0. 959 */ 960 uint32_t key0_data5:32; 961 }; 962 uint32_t val; 963 } efuse_rd_key0_data5_reg_t; 964 965 /** Type of rd_key0_data6 register 966 * Register 6 of BLOCK4 (KEY0). 967 */ 968 typedef union { 969 struct { 970 /** key0_data6 : RO; bitpos: [31:0]; default: 0; 971 * Stores the sixth 32 bits of KEY0. 972 */ 973 uint32_t key0_data6:32; 974 }; 975 uint32_t val; 976 } efuse_rd_key0_data6_reg_t; 977 978 /** Type of rd_key0_data7 register 979 * Register 7 of BLOCK4 (KEY0). 980 */ 981 typedef union { 982 struct { 983 /** key0_data7 : RO; bitpos: [31:0]; default: 0; 984 * Stores the seventh 32 bits of KEY0. 985 */ 986 uint32_t key0_data7:32; 987 }; 988 uint32_t val; 989 } efuse_rd_key0_data7_reg_t; 990 991 /** Type of rd_key1_data0 register 992 * Register 0 of BLOCK5 (KEY1). 993 */ 994 typedef union { 995 struct { 996 /** key1_data0 : RO; bitpos: [31:0]; default: 0; 997 * Stores the zeroth 32 bits of KEY1. 998 */ 999 uint32_t key1_data0:32; 1000 }; 1001 uint32_t val; 1002 } efuse_rd_key1_data0_reg_t; 1003 1004 /** Type of rd_key1_data1 register 1005 * Register 1 of BLOCK5 (KEY1). 1006 */ 1007 typedef union { 1008 struct { 1009 /** key1_data1 : RO; bitpos: [31:0]; default: 0; 1010 * Stores the first 32 bits of KEY1. 1011 */ 1012 uint32_t key1_data1:32; 1013 }; 1014 uint32_t val; 1015 } efuse_rd_key1_data1_reg_t; 1016 1017 /** Type of rd_key1_data2 register 1018 * Register 2 of BLOCK5 (KEY1). 1019 */ 1020 typedef union { 1021 struct { 1022 /** key1_data2 : RO; bitpos: [31:0]; default: 0; 1023 * Stores the second 32 bits of KEY1. 1024 */ 1025 uint32_t key1_data2:32; 1026 }; 1027 uint32_t val; 1028 } efuse_rd_key1_data2_reg_t; 1029 1030 /** Type of rd_key1_data3 register 1031 * Register 3 of BLOCK5 (KEY1). 1032 */ 1033 typedef union { 1034 struct { 1035 /** key1_data3 : RO; bitpos: [31:0]; default: 0; 1036 * Stores the third 32 bits of KEY1. 1037 */ 1038 uint32_t key1_data3:32; 1039 }; 1040 uint32_t val; 1041 } efuse_rd_key1_data3_reg_t; 1042 1043 /** Type of rd_key1_data4 register 1044 * Register 4 of BLOCK5 (KEY1). 1045 */ 1046 typedef union { 1047 struct { 1048 /** key1_data4 : RO; bitpos: [31:0]; default: 0; 1049 * Stores the fourth 32 bits of KEY1. 1050 */ 1051 uint32_t key1_data4:32; 1052 }; 1053 uint32_t val; 1054 } efuse_rd_key1_data4_reg_t; 1055 1056 /** Type of rd_key1_data5 register 1057 * Register 5 of BLOCK5 (KEY1). 1058 */ 1059 typedef union { 1060 struct { 1061 /** key1_data5 : RO; bitpos: [31:0]; default: 0; 1062 * Stores the fifth 32 bits of KEY1. 1063 */ 1064 uint32_t key1_data5:32; 1065 }; 1066 uint32_t val; 1067 } efuse_rd_key1_data5_reg_t; 1068 1069 /** Type of rd_key1_data6 register 1070 * Register 6 of BLOCK5 (KEY1). 1071 */ 1072 typedef union { 1073 struct { 1074 /** key1_data6 : RO; bitpos: [31:0]; default: 0; 1075 * Stores the sixth 32 bits of KEY1. 1076 */ 1077 uint32_t key1_data6:32; 1078 }; 1079 uint32_t val; 1080 } efuse_rd_key1_data6_reg_t; 1081 1082 /** Type of rd_key1_data7 register 1083 * Register 7 of BLOCK5 (KEY1). 1084 */ 1085 typedef union { 1086 struct { 1087 /** key1_data7 : RO; bitpos: [31:0]; default: 0; 1088 * Stores the seventh 32 bits of KEY1. 1089 */ 1090 uint32_t key1_data7:32; 1091 }; 1092 uint32_t val; 1093 } efuse_rd_key1_data7_reg_t; 1094 1095 /** Type of rd_key2_data0 register 1096 * Register 0 of BLOCK6 (KEY2). 1097 */ 1098 typedef union { 1099 struct { 1100 /** key2_data0 : RO; bitpos: [31:0]; default: 0; 1101 * Stores the zeroth 32 bits of KEY2. 1102 */ 1103 uint32_t key2_data0:32; 1104 }; 1105 uint32_t val; 1106 } efuse_rd_key2_data0_reg_t; 1107 1108 /** Type of rd_key2_data1 register 1109 * Register 1 of BLOCK6 (KEY2). 1110 */ 1111 typedef union { 1112 struct { 1113 /** key2_data1 : RO; bitpos: [31:0]; default: 0; 1114 * Stores the first 32 bits of KEY2. 1115 */ 1116 uint32_t key2_data1:32; 1117 }; 1118 uint32_t val; 1119 } efuse_rd_key2_data1_reg_t; 1120 1121 /** Type of rd_key2_data2 register 1122 * Register 2 of BLOCK6 (KEY2). 1123 */ 1124 typedef union { 1125 struct { 1126 /** key2_data2 : RO; bitpos: [31:0]; default: 0; 1127 * Stores the second 32 bits of KEY2. 1128 */ 1129 uint32_t key2_data2:32; 1130 }; 1131 uint32_t val; 1132 } efuse_rd_key2_data2_reg_t; 1133 1134 /** Type of rd_key2_data3 register 1135 * Register 3 of BLOCK6 (KEY2). 1136 */ 1137 typedef union { 1138 struct { 1139 /** key2_data3 : RO; bitpos: [31:0]; default: 0; 1140 * Stores the third 32 bits of KEY2. 1141 */ 1142 uint32_t key2_data3:32; 1143 }; 1144 uint32_t val; 1145 } efuse_rd_key2_data3_reg_t; 1146 1147 /** Type of rd_key2_data4 register 1148 * Register 4 of BLOCK6 (KEY2). 1149 */ 1150 typedef union { 1151 struct { 1152 /** key2_data4 : RO; bitpos: [31:0]; default: 0; 1153 * Stores the fourth 32 bits of KEY2. 1154 */ 1155 uint32_t key2_data4:32; 1156 }; 1157 uint32_t val; 1158 } efuse_rd_key2_data4_reg_t; 1159 1160 /** Type of rd_key2_data5 register 1161 * Register 5 of BLOCK6 (KEY2). 1162 */ 1163 typedef union { 1164 struct { 1165 /** key2_data5 : RO; bitpos: [31:0]; default: 0; 1166 * Stores the fifth 32 bits of KEY2. 1167 */ 1168 uint32_t key2_data5:32; 1169 }; 1170 uint32_t val; 1171 } efuse_rd_key2_data5_reg_t; 1172 1173 /** Type of rd_key2_data6 register 1174 * Register 6 of BLOCK6 (KEY2). 1175 */ 1176 typedef union { 1177 struct { 1178 /** key2_data6 : RO; bitpos: [31:0]; default: 0; 1179 * Stores the sixth 32 bits of KEY2. 1180 */ 1181 uint32_t key2_data6:32; 1182 }; 1183 uint32_t val; 1184 } efuse_rd_key2_data6_reg_t; 1185 1186 /** Type of rd_key2_data7 register 1187 * Register 7 of BLOCK6 (KEY2). 1188 */ 1189 typedef union { 1190 struct { 1191 /** key2_data7 : RO; bitpos: [31:0]; default: 0; 1192 * Stores the seventh 32 bits of KEY2. 1193 */ 1194 uint32_t key2_data7:32; 1195 }; 1196 uint32_t val; 1197 } efuse_rd_key2_data7_reg_t; 1198 1199 /** Type of rd_key3_data0 register 1200 * Register 0 of BLOCK7 (KEY3). 1201 */ 1202 typedef union { 1203 struct { 1204 /** key3_data0 : RO; bitpos: [31:0]; default: 0; 1205 * Stores the zeroth 32 bits of KEY3. 1206 */ 1207 uint32_t key3_data0:32; 1208 }; 1209 uint32_t val; 1210 } efuse_rd_key3_data0_reg_t; 1211 1212 /** Type of rd_key3_data1 register 1213 * Register 1 of BLOCK7 (KEY3). 1214 */ 1215 typedef union { 1216 struct { 1217 /** key3_data1 : RO; bitpos: [31:0]; default: 0; 1218 * Stores the first 32 bits of KEY3. 1219 */ 1220 uint32_t key3_data1:32; 1221 }; 1222 uint32_t val; 1223 } efuse_rd_key3_data1_reg_t; 1224 1225 /** Type of rd_key3_data2 register 1226 * Register 2 of BLOCK7 (KEY3). 1227 */ 1228 typedef union { 1229 struct { 1230 /** key3_data2 : RO; bitpos: [31:0]; default: 0; 1231 * Stores the second 32 bits of KEY3. 1232 */ 1233 uint32_t key3_data2:32; 1234 }; 1235 uint32_t val; 1236 } efuse_rd_key3_data2_reg_t; 1237 1238 /** Type of rd_key3_data3 register 1239 * Register 3 of BLOCK7 (KEY3). 1240 */ 1241 typedef union { 1242 struct { 1243 /** key3_data3 : RO; bitpos: [31:0]; default: 0; 1244 * Stores the third 32 bits of KEY3. 1245 */ 1246 uint32_t key3_data3:32; 1247 }; 1248 uint32_t val; 1249 } efuse_rd_key3_data3_reg_t; 1250 1251 /** Type of rd_key3_data4 register 1252 * Register 4 of BLOCK7 (KEY3). 1253 */ 1254 typedef union { 1255 struct { 1256 /** key3_data4 : RO; bitpos: [31:0]; default: 0; 1257 * Stores the fourth 32 bits of KEY3. 1258 */ 1259 uint32_t key3_data4:32; 1260 }; 1261 uint32_t val; 1262 } efuse_rd_key3_data4_reg_t; 1263 1264 /** Type of rd_key3_data5 register 1265 * Register 5 of BLOCK7 (KEY3). 1266 */ 1267 typedef union { 1268 struct { 1269 /** key3_data5 : RO; bitpos: [31:0]; default: 0; 1270 * Stores the fifth 32 bits of KEY3. 1271 */ 1272 uint32_t key3_data5:32; 1273 }; 1274 uint32_t val; 1275 } efuse_rd_key3_data5_reg_t; 1276 1277 /** Type of rd_key3_data6 register 1278 * Register 6 of BLOCK7 (KEY3). 1279 */ 1280 typedef union { 1281 struct { 1282 /** key3_data6 : RO; bitpos: [31:0]; default: 0; 1283 * Stores the sixth 32 bits of KEY3. 1284 */ 1285 uint32_t key3_data6:32; 1286 }; 1287 uint32_t val; 1288 } efuse_rd_key3_data6_reg_t; 1289 1290 /** Type of rd_key3_data7 register 1291 * Register 7 of BLOCK7 (KEY3). 1292 */ 1293 typedef union { 1294 struct { 1295 /** key3_data7 : RO; bitpos: [31:0]; default: 0; 1296 * Stores the seventh 32 bits of KEY3. 1297 */ 1298 uint32_t key3_data7:32; 1299 }; 1300 uint32_t val; 1301 } efuse_rd_key3_data7_reg_t; 1302 1303 /** Type of rd_key4_data0 register 1304 * Register 0 of BLOCK8 (KEY4). 1305 */ 1306 typedef union { 1307 struct { 1308 /** key4_data0 : RO; bitpos: [31:0]; default: 0; 1309 * Stores the zeroth 32 bits of KEY4. 1310 */ 1311 uint32_t key4_data0:32; 1312 }; 1313 uint32_t val; 1314 } efuse_rd_key4_data0_reg_t; 1315 1316 /** Type of rd_key4_data1 register 1317 * Register 1 of BLOCK8 (KEY4). 1318 */ 1319 typedef union { 1320 struct { 1321 /** key4_data1 : RO; bitpos: [31:0]; default: 0; 1322 * Stores the first 32 bits of KEY4. 1323 */ 1324 uint32_t key4_data1:32; 1325 }; 1326 uint32_t val; 1327 } efuse_rd_key4_data1_reg_t; 1328 1329 /** Type of rd_key4_data2 register 1330 * Register 2 of BLOCK8 (KEY4). 1331 */ 1332 typedef union { 1333 struct { 1334 /** key4_data2 : RO; bitpos: [31:0]; default: 0; 1335 * Stores the second 32 bits of KEY4. 1336 */ 1337 uint32_t key4_data2:32; 1338 }; 1339 uint32_t val; 1340 } efuse_rd_key4_data2_reg_t; 1341 1342 /** Type of rd_key4_data3 register 1343 * Register 3 of BLOCK8 (KEY4). 1344 */ 1345 typedef union { 1346 struct { 1347 /** key4_data3 : RO; bitpos: [31:0]; default: 0; 1348 * Stores the third 32 bits of KEY4. 1349 */ 1350 uint32_t key4_data3:32; 1351 }; 1352 uint32_t val; 1353 } efuse_rd_key4_data3_reg_t; 1354 1355 /** Type of rd_key4_data4 register 1356 * Register 4 of BLOCK8 (KEY4). 1357 */ 1358 typedef union { 1359 struct { 1360 /** key4_data4 : RO; bitpos: [31:0]; default: 0; 1361 * Stores the fourth 32 bits of KEY4. 1362 */ 1363 uint32_t key4_data4:32; 1364 }; 1365 uint32_t val; 1366 } efuse_rd_key4_data4_reg_t; 1367 1368 /** Type of rd_key4_data5 register 1369 * Register 5 of BLOCK8 (KEY4). 1370 */ 1371 typedef union { 1372 struct { 1373 /** key4_data5 : RO; bitpos: [31:0]; default: 0; 1374 * Stores the fifth 32 bits of KEY4. 1375 */ 1376 uint32_t key4_data5:32; 1377 }; 1378 uint32_t val; 1379 } efuse_rd_key4_data5_reg_t; 1380 1381 /** Type of rd_key4_data6 register 1382 * Register 6 of BLOCK8 (KEY4). 1383 */ 1384 typedef union { 1385 struct { 1386 /** key4_data6 : RO; bitpos: [31:0]; default: 0; 1387 * Stores the sixth 32 bits of KEY4. 1388 */ 1389 uint32_t key4_data6:32; 1390 }; 1391 uint32_t val; 1392 } efuse_rd_key4_data6_reg_t; 1393 1394 /** Type of rd_key4_data7 register 1395 * Register 7 of BLOCK8 (KEY4). 1396 */ 1397 typedef union { 1398 struct { 1399 /** key4_data7 : RO; bitpos: [31:0]; default: 0; 1400 * Stores the seventh 32 bits of KEY4. 1401 */ 1402 uint32_t key4_data7:32; 1403 }; 1404 uint32_t val; 1405 } efuse_rd_key4_data7_reg_t; 1406 1407 /** Type of rd_key5_data0 register 1408 * Register 0 of BLOCK9 (KEY5). 1409 */ 1410 typedef union { 1411 struct { 1412 /** key5_data0 : RO; bitpos: [31:0]; default: 0; 1413 * Stores the zeroth 32 bits of KEY5. 1414 */ 1415 uint32_t key5_data0:32; 1416 }; 1417 uint32_t val; 1418 } efuse_rd_key5_data0_reg_t; 1419 1420 /** Type of rd_key5_data1 register 1421 * Register 1 of BLOCK9 (KEY5). 1422 */ 1423 typedef union { 1424 struct { 1425 /** key5_data1 : RO; bitpos: [31:0]; default: 0; 1426 * Stores the first 32 bits of KEY5. 1427 */ 1428 uint32_t key5_data1:32; 1429 }; 1430 uint32_t val; 1431 } efuse_rd_key5_data1_reg_t; 1432 1433 /** Type of rd_key5_data2 register 1434 * Register 2 of BLOCK9 (KEY5). 1435 */ 1436 typedef union { 1437 struct { 1438 /** key5_data2 : RO; bitpos: [31:0]; default: 0; 1439 * Stores the second 32 bits of KEY5. 1440 */ 1441 uint32_t key5_data2:32; 1442 }; 1443 uint32_t val; 1444 } efuse_rd_key5_data2_reg_t; 1445 1446 /** Type of rd_key5_data3 register 1447 * Register 3 of BLOCK9 (KEY5). 1448 */ 1449 typedef union { 1450 struct { 1451 /** key5_data3 : RO; bitpos: [31:0]; default: 0; 1452 * Stores the third 32 bits of KEY5. 1453 */ 1454 uint32_t key5_data3:32; 1455 }; 1456 uint32_t val; 1457 } efuse_rd_key5_data3_reg_t; 1458 1459 /** Type of rd_key5_data4 register 1460 * Register 4 of BLOCK9 (KEY5). 1461 */ 1462 typedef union { 1463 struct { 1464 /** key5_data4 : RO; bitpos: [31:0]; default: 0; 1465 * Stores the fourth 32 bits of KEY5. 1466 */ 1467 uint32_t key5_data4:32; 1468 }; 1469 uint32_t val; 1470 } efuse_rd_key5_data4_reg_t; 1471 1472 /** Type of rd_key5_data5 register 1473 * Register 5 of BLOCK9 (KEY5). 1474 */ 1475 typedef union { 1476 struct { 1477 /** key5_data5 : RO; bitpos: [31:0]; default: 0; 1478 * Stores the fifth 32 bits of KEY5. 1479 */ 1480 uint32_t key5_data5:32; 1481 }; 1482 uint32_t val; 1483 } efuse_rd_key5_data5_reg_t; 1484 1485 /** Type of rd_key5_data6 register 1486 * Register 6 of BLOCK9 (KEY5). 1487 */ 1488 typedef union { 1489 struct { 1490 /** key5_data6 : RO; bitpos: [31:0]; default: 0; 1491 * Stores the sixth 32 bits of KEY5. 1492 */ 1493 uint32_t key5_data6:32; 1494 }; 1495 uint32_t val; 1496 } efuse_rd_key5_data6_reg_t; 1497 1498 /** Type of rd_key5_data7 register 1499 * Register 7 of BLOCK9 (KEY5). 1500 */ 1501 typedef union { 1502 struct { 1503 /** key5_data7 : RO; bitpos: [31:0]; default: 0; 1504 * Stores the seventh 32 bits of KEY5. 1505 */ 1506 uint32_t key5_data7:32; 1507 }; 1508 uint32_t val; 1509 } efuse_rd_key5_data7_reg_t; 1510 1511 /** Type of rd_sys_part2_data0 register 1512 * Register 0 of BLOCK10 (system). 1513 */ 1514 typedef union { 1515 struct { 1516 /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0; 1517 * Stores the 0th 32 bits of the 2nd part of system data. 1518 */ 1519 uint32_t sys_data_part2_0:32; 1520 }; 1521 uint32_t val; 1522 } efuse_rd_sys_part2_data0_reg_t; 1523 1524 /** Type of rd_sys_part2_data1 register 1525 * Register 1 of BLOCK9 (KEY5). 1526 */ 1527 typedef union { 1528 struct { 1529 /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0; 1530 * Stores the 1st 32 bits of the 2nd part of system data. 1531 */ 1532 uint32_t sys_data_part2_1:32; 1533 }; 1534 uint32_t val; 1535 } efuse_rd_sys_part2_data1_reg_t; 1536 1537 /** Type of rd_sys_part2_data2 register 1538 * Register 2 of BLOCK10 (system). 1539 */ 1540 typedef union { 1541 struct { 1542 /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0; 1543 * Stores the 2nd 32 bits of the 2nd part of system data. 1544 */ 1545 uint32_t sys_data_part2_2:32; 1546 }; 1547 uint32_t val; 1548 } efuse_rd_sys_part2_data2_reg_t; 1549 1550 /** Type of rd_sys_part2_data3 register 1551 * Register 3 of BLOCK10 (system). 1552 */ 1553 typedef union { 1554 struct { 1555 /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0; 1556 * Stores the 3rd 32 bits of the 2nd part of system data. 1557 */ 1558 uint32_t sys_data_part2_3:32; 1559 }; 1560 uint32_t val; 1561 } efuse_rd_sys_part2_data3_reg_t; 1562 1563 /** Type of rd_sys_part2_data4 register 1564 * Register 4 of BLOCK10 (system). 1565 */ 1566 typedef union { 1567 struct { 1568 /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0; 1569 * Stores the 4th 32 bits of the 2nd part of system data. 1570 */ 1571 uint32_t sys_data_part2_4:32; 1572 }; 1573 uint32_t val; 1574 } efuse_rd_sys_part2_data4_reg_t; 1575 1576 /** Type of rd_sys_part2_data5 register 1577 * Register 5 of BLOCK10 (system). 1578 */ 1579 typedef union { 1580 struct { 1581 /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0; 1582 * Stores the 5th 32 bits of the 2nd part of system data. 1583 */ 1584 uint32_t sys_data_part2_5:32; 1585 }; 1586 uint32_t val; 1587 } efuse_rd_sys_part2_data5_reg_t; 1588 1589 /** Type of rd_sys_part2_data6 register 1590 * Register 6 of BLOCK10 (system). 1591 */ 1592 typedef union { 1593 struct { 1594 /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0; 1595 * Stores the 6th 32 bits of the 2nd part of system data. 1596 */ 1597 uint32_t sys_data_part2_6:32; 1598 }; 1599 uint32_t val; 1600 } efuse_rd_sys_part2_data6_reg_t; 1601 1602 /** Type of rd_sys_part2_data7 register 1603 * Register 7 of BLOCK10 (system). 1604 */ 1605 typedef union { 1606 struct { 1607 /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0; 1608 * Stores the 7th 32 bits of the 2nd part of system data. 1609 */ 1610 uint32_t sys_data_part2_7:32; 1611 }; 1612 uint32_t val; 1613 } efuse_rd_sys_part2_data7_reg_t; 1614 1615 1616 /** Group: Report Register */ 1617 /** Type of rd_repeat_err0 register 1618 * Programming error record register 0 of BLOCK0. 1619 */ 1620 typedef union { 1621 struct { 1622 /** rd_dis_err : RO; bitpos: [6:0]; default: 0; 1623 * If any bit in RD_DIS is 1, then it indicates a programming error. 1624 */ 1625 uint32_t rd_dis_err:7; 1626 /** dis_rtc_ram_boot_err : RO; bitpos: [7]; default: 0; 1627 * If DIS_RTC_RAM_BOOT is 1, then it indicates a programming error. 1628 */ 1629 uint32_t dis_rtc_ram_boot_err:1; 1630 /** dis_icache_err : RO; bitpos: [8]; default: 0; 1631 * If DIS_ICACHE is 1, then it indicates a programming error. 1632 */ 1633 uint32_t dis_icache_err:1; 1634 /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0; 1635 * If DIS_USB_JTAG is 1, then it indicates a programming error. 1636 */ 1637 uint32_t dis_usb_jtag_err:1; 1638 /** dis_download_icache_err : RO; bitpos: [10]; default: 0; 1639 * If DIS_DOWNLOAD_ICACHE is 1, then it indicates a programming error. 1640 */ 1641 uint32_t dis_download_icache_err:1; 1642 /** dis_usb_device_err : RO; bitpos: [11]; default: 0; 1643 * If DIS_USB_DEVICE is 1, then it indicates a programming error. 1644 */ 1645 uint32_t dis_usb_device_err:1; 1646 /** dis_force_download_err : RO; bitpos: [12]; default: 0; 1647 * If DIS_FORCE_DOWNLOAD is 1, then it indicates a programming error. 1648 */ 1649 uint32_t dis_force_download_err:1; 1650 /** rpt4_reserved6_err : RO; bitpos: [13]; default: 0; 1651 * Reserved. 1652 */ 1653 uint32_t rpt4_reserved6_err:1; 1654 /** dis_can_err : RO; bitpos: [14]; default: 0; 1655 * If DIS_CAN is 1, then it indicates a programming error. 1656 */ 1657 uint32_t dis_can_err:1; 1658 /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0; 1659 * If JTAG_SEL_ENABLE is 1, then it indicates a programming error. 1660 */ 1661 uint32_t jtag_sel_enable_err:1; 1662 /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0; 1663 * If SOFT_DIS_JTAG is 1, then it indicates a programming error. 1664 */ 1665 uint32_t soft_dis_jtag_err:3; 1666 /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0; 1667 * If DIS_PAD_JTAG is 1, then it indicates a programming error. 1668 */ 1669 uint32_t dis_pad_jtag_err:1; 1670 /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0; 1671 * If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error. 1672 */ 1673 uint32_t dis_download_manual_encrypt_err:1; 1674 /** usb_drefh_err : RO; bitpos: [22:21]; default: 0; 1675 * If any bit in USB_DREFH is 1, then it indicates a programming error. 1676 */ 1677 uint32_t usb_drefh_err:2; 1678 /** usb_drefl_err : RO; bitpos: [24:23]; default: 0; 1679 * If any bit in USB_DREFL is 1, then it indicates a programming error. 1680 */ 1681 uint32_t usb_drefl_err:2; 1682 /** usb_exchg_pins_err : RO; bitpos: [25]; default: 0; 1683 * If USB_EXCHG_PINS is 1, then it indicates a programming error. 1684 */ 1685 uint32_t usb_exchg_pins_err:1; 1686 /** vdd_spi_as_gpio_err : RO; bitpos: [26]; default: 0; 1687 * If VDD_SPI_AS_GPIO is 1, then it indicates a programming error. 1688 */ 1689 uint32_t vdd_spi_as_gpio_err:1; 1690 /** btlc_gpio_enable_err : RO; bitpos: [28:27]; default: 0; 1691 * If any bit in BTLC_GPIO_ENABLE is 1, then it indicates a programming error. 1692 */ 1693 uint32_t btlc_gpio_enable_err:2; 1694 /** powerglitch_en_err : RO; bitpos: [29]; default: 0; 1695 * If POWERGLITCH_EN is 1, then it indicates a programming error. 1696 */ 1697 uint32_t powerglitch_en_err:1; 1698 /** power_glitch_dsense_err : RO; bitpos: [31:30]; default: 0; 1699 * If any bit in POWER_GLITCH_DSENSE is 1, then it indicates a programming error. 1700 */ 1701 uint32_t power_glitch_dsense_err:2; 1702 }; 1703 uint32_t val; 1704 } efuse_rd_repeat_err0_reg_t; 1705 1706 /** Type of rd_repeat_err1 register 1707 * Programming error record register 1 of BLOCK0. 1708 */ 1709 typedef union { 1710 struct { 1711 /** rpt4_reserved2_err : RO; bitpos: [15:0]; default: 0; 1712 * Reserved. 1713 */ 1714 uint32_t rpt4_reserved2_err:16; 1715 /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0; 1716 * If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error. 1717 */ 1718 uint32_t wdt_delay_sel_err:2; 1719 /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0; 1720 * If any bit in SPI_BOOT_CRYPT_CNT is 1, then it indicates a programming error. 1721 */ 1722 uint32_t spi_boot_crypt_cnt_err:3; 1723 /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0; 1724 * If SECURE_BOOT_KEY_REVOKE0 is 1, then it indicates a programming error. 1725 */ 1726 uint32_t secure_boot_key_revoke0_err:1; 1727 /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0; 1728 * If SECURE_BOOT_KEY_REVOKE1 is 1, then it indicates a programming error. 1729 */ 1730 uint32_t secure_boot_key_revoke1_err:1; 1731 /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0; 1732 * If SECURE_BOOT_KEY_REVOKE2 is 1, then it indicates a programming error. 1733 */ 1734 uint32_t secure_boot_key_revoke2_err:1; 1735 /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0; 1736 * If any bit in KEY_PURPOSE_0 is 1, then it indicates a programming error. 1737 */ 1738 uint32_t key_purpose_0_err:4; 1739 /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0; 1740 * If any bit in KEY_PURPOSE_1 is 1, then it indicates a programming error. 1741 */ 1742 uint32_t key_purpose_1_err:4; 1743 }; 1744 uint32_t val; 1745 } efuse_rd_repeat_err1_reg_t; 1746 1747 /** Type of rd_repeat_err2 register 1748 * Programming error record register 2 of BLOCK0. 1749 */ 1750 typedef union { 1751 struct { 1752 /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0; 1753 * If any bit in KEY_PURPOSE_2 is 1, then it indicates a programming error. 1754 */ 1755 uint32_t key_purpose_2_err:4; 1756 /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0; 1757 * If any bit in KEY_PURPOSE_3 is 1, then it indicates a programming error. 1758 */ 1759 uint32_t key_purpose_3_err:4; 1760 /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0; 1761 * If any bit in KEY_PURPOSE_4 is 1, then it indicates a programming error. 1762 */ 1763 uint32_t key_purpose_4_err:4; 1764 /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0; 1765 * If any bit in KEY_PURPOSE_5 is 1, then it indicates a programming error. 1766 */ 1767 uint32_t key_purpose_5_err:4; 1768 /** rpt4_reserved3_err : RO; bitpos: [19:16]; default: 0; 1769 * Reserved. 1770 */ 1771 uint32_t rpt4_reserved3_err:4; 1772 /** secure_boot_en_err : RO; bitpos: [20]; default: 0; 1773 * If SECURE_BOOT_EN is 1, then it indicates a programming error. 1774 */ 1775 uint32_t secure_boot_en_err:1; 1776 /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0; 1777 * If SECURE_BOOT_AGGRESSIVE_REVOKE is 1, then it indicates a programming error. 1778 */ 1779 uint32_t secure_boot_aggressive_revoke_err:1; 1780 /** rpt4_reserved0_err : RO; bitpos: [27:22]; default: 0; 1781 * Reserved. 1782 */ 1783 uint32_t rpt4_reserved0_err:6; 1784 /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0; 1785 * If any bit in FLASH_TPUM is 1, then it indicates a programming error. 1786 */ 1787 uint32_t flash_tpuw_err:4; 1788 }; 1789 uint32_t val; 1790 } efuse_rd_repeat_err2_reg_t; 1791 1792 /** Type of rd_repeat_err3 register 1793 * Programming error record register 3 of BLOCK0. 1794 */ 1795 typedef union { 1796 struct { 1797 /** dis_download_mode_err : RO; bitpos: [0]; default: 0; 1798 * If DIS_DOWNLOAD_MODE is 1, then it indicates a programming error. 1799 */ 1800 uint32_t dis_download_mode_err:1; 1801 /** dis_legacy_spi_boot_err : RO; bitpos: [1]; default: 0; 1802 * If DIS_LEGACY_SPI_BOOT is 1, then it indicates a programming error. 1803 */ 1804 uint32_t dis_legacy_spi_boot_err:1; 1805 /** uart_print_channel_err : RO; bitpos: [2]; default: 0; 1806 * If UART_PRINT_CHANNEL is 1, then it indicates a programming error. 1807 */ 1808 uint32_t uart_print_channel_err:1; 1809 /** flash_ecc_mode_err : RO; bitpos: [3]; default: 0; 1810 * If FLASH_ECC_MODE is 1, then it indicates a programming error. 1811 */ 1812 uint32_t flash_ecc_mode_err:1; 1813 /** dis_usb_download_mode_err : RO; bitpos: [4]; default: 0; 1814 * If DIS_USB_DOWNLOAD_MODE is 1, then it indicates a programming error. 1815 */ 1816 uint32_t dis_usb_download_mode_err:1; 1817 /** enable_security_download_err : RO; bitpos: [5]; default: 0; 1818 * If ENABLE_SECURITY_DOWNLOAD is 1, then it indicates a programming error. 1819 */ 1820 uint32_t enable_security_download_err:1; 1821 /** uart_print_control_err : RO; bitpos: [7:6]; default: 0; 1822 * If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error. 1823 */ 1824 uint32_t uart_print_control_err:2; 1825 /** pin_power_selection_err : RO; bitpos: [8]; default: 0; 1826 * If PIN_POWER_SELECTION is 1, then it indicates a programming error. 1827 */ 1828 uint32_t pin_power_selection_err:1; 1829 /** flash_type_err : RO; bitpos: [9]; default: 0; 1830 * If FLASH_TYPE is 1, then it indicates a programming error. 1831 */ 1832 uint32_t flash_type_err:1; 1833 /** flash_page_size_err : RO; bitpos: [11:10]; default: 0; 1834 * If any bits in FLASH_PAGE_SIZE is 1, then it indicates a programming error. 1835 */ 1836 uint32_t flash_page_size_err:2; 1837 /** flash_ecc_en_err : RO; bitpos: [12]; default: 0; 1838 * If FLASH_ECC_EN_ERR is 1, then it indicates a programming error. 1839 */ 1840 uint32_t flash_ecc_en_err:1; 1841 /** force_send_resume_err : RO; bitpos: [13]; default: 0; 1842 * If FORCE_SEND_RESUME is 1, then it indicates a programming error. 1843 */ 1844 uint32_t force_send_resume_err:1; 1845 /** secure_version_err : RO; bitpos: [29:14]; default: 0; 1846 * If any bit in SECURE_VERSION is 1, then it indicates a programming error. 1847 */ 1848 uint32_t secure_version_err:16; 1849 /** rpt4_reserved1_err : RO; bitpos: [31:30]; default: 0; 1850 * Reserved. 1851 */ 1852 uint32_t rpt4_reserved1_err:2; 1853 }; 1854 uint32_t val; 1855 } efuse_rd_repeat_err3_reg_t; 1856 1857 /** Type of rd_repeat_err4 register 1858 * Programming error record register 4 of BLOCK0. 1859 */ 1860 typedef union { 1861 struct { 1862 /** rpt4_reserved4_err : RO; bitpos: [23:0]; default: 0; 1863 * Reserved. 1864 */ 1865 uint32_t rpt4_reserved4_err:24; 1866 uint32_t reserved_24:8; 1867 }; 1868 uint32_t val; 1869 } efuse_rd_repeat_err4_reg_t; 1870 1871 /** Type of rd_rs_err0 register 1872 * Programming error record register 0 of BLOCK1-10. 1873 */ 1874 typedef union { 1875 struct { 1876 /** mac_spi_8m_err_num : RO; bitpos: [2:0]; default: 0; 1877 * The value of this signal means the number of error bytes. 1878 */ 1879 uint32_t mac_spi_8m_err_num:3; 1880 /** reserved_fail : RO; bitpos: [3]; default: 0; 1881 * 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that 1882 * programming user data failed and the number of error bytes is over 6. 1883 */ 1884 uint32_t reserved_fail:1; 1885 /** sys_part1_num : RO; bitpos: [6:4]; default: 0; 1886 * The value of this signal means the number of error bytes. 1887 */ 1888 uint32_t sys_part1_num:3; 1889 /** mac_spi_8m_fail : RO; bitpos: [7]; default: 0; 1890 * 0: Means no failure and that the data of system part1 is reliable 1: Means that 1891 * programming user data failed and the number of error bytes is over 6. 1892 */ 1893 uint32_t mac_spi_8m_fail:1; 1894 /** usr_data_err_num : RO; bitpos: [10:8]; default: 0; 1895 * The value of this signal means the number of error bytes. 1896 */ 1897 uint32_t usr_data_err_num:3; 1898 /** sys_part1_fail : RO; bitpos: [11]; default: 0; 1899 * 0: Means no failure and that the user data is reliable 1: Means that programming 1900 * user data failed and the number of error bytes is over 6. 1901 */ 1902 uint32_t sys_part1_fail:1; 1903 /** key0_err_num : RO; bitpos: [14:12]; default: 0; 1904 * The value of this signal means the number of error bytes. 1905 */ 1906 uint32_t key0_err_num:3; 1907 /** usr_data_fail : RO; bitpos: [15]; default: 0; 1908 * 0: Means no failure and that the data of key0 is reliable 1: Means that programming 1909 * key0 failed and the number of error bytes is over 6. 1910 */ 1911 uint32_t usr_data_fail:1; 1912 /** key1_err_num : RO; bitpos: [18:16]; default: 0; 1913 * The value of this signal means the number of error bytes. 1914 */ 1915 uint32_t key1_err_num:3; 1916 /** key0_fail : RO; bitpos: [19]; default: 0; 1917 * 0: Means no failure and that the data of key1 is reliable 1: Means that programming 1918 * key1 failed and the number of error bytes is over 6. 1919 */ 1920 uint32_t key0_fail:1; 1921 /** key2_err_num : RO; bitpos: [22:20]; default: 0; 1922 * The value of this signal means the number of error bytes. 1923 */ 1924 uint32_t key2_err_num:3; 1925 /** key1_fail : RO; bitpos: [23]; default: 0; 1926 * 0: Means no failure and that the data of key2 is reliable 1: Means that programming 1927 * key2 failed and the number of error bytes is over 6. 1928 */ 1929 uint32_t key1_fail:1; 1930 /** key3_err_num : RO; bitpos: [26:24]; default: 0; 1931 * The value of this signal means the number of error bytes. 1932 */ 1933 uint32_t key3_err_num:3; 1934 /** key2_fail : RO; bitpos: [27]; default: 0; 1935 * 0: Means no failure and that the data of key3 is reliable 1: Means that programming 1936 * key3 failed and the number of error bytes is over 6. 1937 */ 1938 uint32_t key2_fail:1; 1939 /** key4_err_num : RO; bitpos: [30:28]; default: 0; 1940 * The value of this signal means the number of error bytes. 1941 */ 1942 uint32_t key4_err_num:3; 1943 /** key3_fail : RO; bitpos: [31]; default: 0; 1944 * 0: Means no failure and that the data of key4 is reliable 1: Means that programming 1945 * key4 failed and the number of error bytes is over 6. 1946 */ 1947 uint32_t key3_fail:1; 1948 }; 1949 uint32_t val; 1950 } efuse_rd_rs_err0_reg_t; 1951 1952 /** Type of rd_rs_err1 register 1953 * Programming error record register 1 of BLOCK1-10. 1954 */ 1955 typedef union { 1956 struct { 1957 /** key5_err_num : RO; bitpos: [2:0]; default: 0; 1958 * The value of this signal means the number of error bytes. 1959 */ 1960 uint32_t key5_err_num:3; 1961 /** key4_fail : RO; bitpos: [3]; default: 0; 1962 * 0: Means no failure and that the data of KEY5 is reliable 1: Means that programming 1963 * user data failed and the number of error bytes is over 6. 1964 */ 1965 uint32_t key4_fail:1; 1966 /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0; 1967 * The value of this signal means the number of error bytes. 1968 */ 1969 uint32_t sys_part2_err_num:3; 1970 /** key5_fail : RO; bitpos: [7]; default: 0; 1971 * 0: Means no failure and that the data of system part2 is reliable 1: Means that 1972 * programming user data failed and the number of error bytes is over 6. 1973 */ 1974 uint32_t key5_fail:1; 1975 uint32_t reserved_8:24; 1976 }; 1977 uint32_t val; 1978 } efuse_rd_rs_err1_reg_t; 1979 1980 1981 /** Group: Configuration Register */ 1982 /** Type of clk register 1983 * eFuse clcok configuration register. 1984 */ 1985 typedef union { 1986 struct { 1987 /** efuse_mem_force_pd : R/W; bitpos: [0]; default: 0; 1988 * Set this bit to force eFuse SRAM into power-saving mode. 1989 */ 1990 uint32_t efuse_mem_force_pd:1; 1991 /** mem_clk_force_on : R/W; bitpos: [1]; default: 1; 1992 * Set this bit and force to activate clock signal of eFuse SRAM. 1993 */ 1994 uint32_t mem_clk_force_on:1; 1995 /** efuse_mem_force_pu : R/W; bitpos: [2]; default: 0; 1996 * Set this bit to force eFuse SRAM into working mode. 1997 */ 1998 uint32_t efuse_mem_force_pu:1; 1999 uint32_t reserved_3:13; 2000 /** clk_en : R/W; bitpos: [16]; default: 0; 2001 * Set this bit and force to enable clock signal of eFuse memory. 2002 */ 2003 uint32_t clk_en:1; 2004 uint32_t reserved_17:15; 2005 }; 2006 uint32_t val; 2007 } efuse_clk_reg_t; 2008 2009 /** Type of conf register 2010 * eFuse operation mode configuraiton register; 2011 */ 2012 typedef union { 2013 struct { 2014 /** op_code : R/W; bitpos: [15:0]; default: 0; 2015 * 0x5A5A: Operate programming command 0x5AA5: Operate read command. 2016 */ 2017 uint32_t op_code:16; 2018 uint32_t reserved_16:16; 2019 }; 2020 uint32_t val; 2021 } efuse_conf_reg_t; 2022 2023 /** Type of cmd register 2024 * eFuse command register. 2025 */ 2026 typedef union { 2027 struct { 2028 /** read_cmd : R/WS/SC; bitpos: [0]; default: 0; 2029 * Set this bit to send read command. 2030 */ 2031 uint32_t read_cmd:1; 2032 /** pgm_cmd : R/WS/SC; bitpos: [1]; default: 0; 2033 * Set this bit to send programming command. 2034 */ 2035 uint32_t pgm_cmd:1; 2036 /** blk_num : R/W; bitpos: [5:2]; default: 0; 2037 * The serial number of the block to be programmed. Value 0-10 corresponds to block 2038 * number 0-10, respectively. 2039 */ 2040 uint32_t blk_num:4; 2041 uint32_t reserved_6:26; 2042 }; 2043 uint32_t val; 2044 } efuse_cmd_reg_t; 2045 2046 /** Type of dac_conf register 2047 * Controls the eFuse programming voltage. 2048 */ 2049 typedef union { 2050 struct { 2051 /** dac_clk_div : R/W; bitpos: [7:0]; default: 28; 2052 * Controls the division factor of the rising clock of the programming voltage. 2053 */ 2054 uint32_t dac_clk_div:8; 2055 /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0; 2056 * Don't care. 2057 */ 2058 uint32_t dac_clk_pad_sel:1; 2059 /** dac_num : R/W; bitpos: [16:9]; default: 255; 2060 * Controls the rising period of the programming voltage. 2061 */ 2062 uint32_t dac_num:8; 2063 /** oe_clr : R/W; bitpos: [17]; default: 0; 2064 * Reduces the power supply of the programming voltage. 2065 */ 2066 uint32_t oe_clr:1; 2067 uint32_t reserved_18:14; 2068 }; 2069 uint32_t val; 2070 } efuse_dac_conf_reg_t; 2071 2072 /** Type of rd_tim_conf register 2073 * Configures read timing parameters. 2074 */ 2075 typedef union { 2076 struct { 2077 uint32_t reserved_0:24; 2078 /** read_init_num : R/W; bitpos: [31:24]; default: 18; 2079 * Configures the initial read time of eFuse. 2080 */ 2081 uint32_t read_init_num:8; 2082 }; 2083 uint32_t val; 2084 } efuse_rd_tim_conf_reg_t; 2085 2086 /** Type of wr_tim_conf1 register 2087 * Configurarion register 1 of eFuse programming timing parameters. 2088 */ 2089 typedef union { 2090 struct { 2091 uint32_t reserved_0:8; 2092 /** pwr_on_num : R/W; bitpos: [23:8]; default: 10368; 2093 * Configures the power up time for VDDQ. 2094 */ 2095 uint32_t pwr_on_num:16; 2096 uint32_t reserved_24:8; 2097 }; 2098 uint32_t val; 2099 } efuse_wr_tim_conf1_reg_t; 2100 2101 /** Type of wr_tim_conf2 register 2102 * Configurarion register 2 of eFuse programming timing parameters. 2103 */ 2104 typedef union { 2105 struct { 2106 /** pwr_off_num : R/W; bitpos: [15:0]; default: 400; 2107 * Configures the power outage time for VDDQ. 2108 */ 2109 uint32_t pwr_off_num:16; 2110 uint32_t reserved_16:16; 2111 }; 2112 uint32_t val; 2113 } efuse_wr_tim_conf2_reg_t; 2114 2115 2116 /** Group: Status Register */ 2117 /** Type of status register 2118 * eFuse status register. 2119 */ 2120 typedef union { 2121 struct { 2122 /** state : RO; bitpos: [3:0]; default: 0; 2123 * Indicates the state of the eFuse state machine. 2124 */ 2125 uint32_t state:4; 2126 /** otp_load_sw : RO; bitpos: [4]; default: 0; 2127 * The value of OTP_LOAD_SW. 2128 */ 2129 uint32_t otp_load_sw:1; 2130 /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0; 2131 * The value of OTP_VDDQ_C_SYNC2. 2132 */ 2133 uint32_t otp_vddq_c_sync2:1; 2134 /** otp_strobe_sw : RO; bitpos: [6]; default: 0; 2135 * The value of OTP_STROBE_SW. 2136 */ 2137 uint32_t otp_strobe_sw:1; 2138 /** otp_csb_sw : RO; bitpos: [7]; default: 0; 2139 * The value of OTP_CSB_SW. 2140 */ 2141 uint32_t otp_csb_sw:1; 2142 /** otp_pgenb_sw : RO; bitpos: [8]; default: 0; 2143 * The value of OTP_PGENB_SW. 2144 */ 2145 uint32_t otp_pgenb_sw:1; 2146 /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0; 2147 * The value of OTP_VDDQ_IS_SW. 2148 */ 2149 uint32_t otp_vddq_is_sw:1; 2150 /** repeat_err_cnt : RO; bitpos: [17:10]; default: 0; 2151 * Indicates the number of error bits during programming BLOCK0. 2152 */ 2153 uint32_t repeat_err_cnt:8; 2154 uint32_t reserved_18:14; 2155 }; 2156 uint32_t val; 2157 } efuse_status_reg_t; 2158 2159 2160 /** Group: Interrupt Register */ 2161 /** Type of int_raw register 2162 * eFuse raw interrupt register. 2163 */ 2164 typedef union { 2165 struct { 2166 /** read_done_int_raw : R/WC/SS; bitpos: [0]; default: 0; 2167 * The raw bit signal for read_done interrupt. 2168 */ 2169 uint32_t read_done_int_raw:1; 2170 /** pgm_done_int_raw : R/WC/SS; bitpos: [1]; default: 0; 2171 * The raw bit signal for pgm_done interrupt. 2172 */ 2173 uint32_t pgm_done_int_raw:1; 2174 uint32_t reserved_2:30; 2175 }; 2176 uint32_t val; 2177 } efuse_int_raw_reg_t; 2178 2179 /** Type of int_st register 2180 * eFuse interrupt status register. 2181 */ 2182 typedef union { 2183 struct { 2184 /** read_done_int_st : RO; bitpos: [0]; default: 0; 2185 * The status signal for read_done interrupt. 2186 */ 2187 uint32_t read_done_int_st:1; 2188 /** pgm_done_int_st : RO; bitpos: [1]; default: 0; 2189 * The status signal for pgm_done interrupt. 2190 */ 2191 uint32_t pgm_done_int_st:1; 2192 uint32_t reserved_2:30; 2193 }; 2194 uint32_t val; 2195 } efuse_int_st_reg_t; 2196 2197 /** Type of int_ena register 2198 * eFuse interrupt enable register. 2199 */ 2200 typedef union { 2201 struct { 2202 /** read_done_int_ena : R/W; bitpos: [0]; default: 0; 2203 * The enable signal for read_done interrupt. 2204 */ 2205 uint32_t read_done_int_ena:1; 2206 /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0; 2207 * The enable signal for pgm_done interrupt. 2208 */ 2209 uint32_t pgm_done_int_ena:1; 2210 uint32_t reserved_2:30; 2211 }; 2212 uint32_t val; 2213 } efuse_int_ena_reg_t; 2214 2215 /** Type of int_clr register 2216 * eFuse interrupt clear register. 2217 */ 2218 typedef union { 2219 struct { 2220 /** read_done_int_clr : WO; bitpos: [0]; default: 0; 2221 * The clear signal for read_done interrupt. 2222 */ 2223 uint32_t read_done_int_clr:1; 2224 /** pgm_done_int_clr : WO; bitpos: [1]; default: 0; 2225 * The clear signal for pgm_done interrupt. 2226 */ 2227 uint32_t pgm_done_int_clr:1; 2228 uint32_t reserved_2:30; 2229 }; 2230 uint32_t val; 2231 } efuse_int_clr_reg_t; 2232 2233 2234 /** Group: Version Register */ 2235 /** Type of date register 2236 * eFuse version register. 2237 */ 2238 typedef union { 2239 struct { 2240 /** date : R/W; bitpos: [27:0]; default: 33583616; 2241 * Stores eFuse version. 2242 */ 2243 uint32_t date:28; 2244 uint32_t reserved_28:4; 2245 }; 2246 uint32_t val; 2247 } efuse_date_reg_t; 2248 2249 2250 typedef struct { 2251 volatile efuse_pgm_data0_reg_t pgm_data0; 2252 volatile efuse_pgm_data1_reg_t pgm_data1; 2253 volatile efuse_pgm_data2_reg_t pgm_data2; 2254 volatile efuse_pgm_data3_reg_t pgm_data3; 2255 volatile efuse_pgm_data4_reg_t pgm_data4; 2256 volatile efuse_pgm_data5_reg_t pgm_data5; 2257 volatile efuse_pgm_data6_reg_t pgm_data6; 2258 volatile efuse_pgm_data7_reg_t pgm_data7; 2259 volatile efuse_pgm_check_value0_reg_t pgm_check_value0; 2260 volatile efuse_pgm_check_value1_reg_t pgm_check_value1; 2261 volatile efuse_pgm_check_value2_reg_t pgm_check_value2; 2262 volatile efuse_rd_wr_dis_reg_t rd_wr_dis; 2263 volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0; 2264 volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1; 2265 volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2; 2266 volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3; 2267 volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4; 2268 volatile efuse_rd_mac_spi_sys_0_reg_t rd_mac_spi_sys_0; 2269 volatile efuse_rd_mac_spi_sys_1_reg_t rd_mac_spi_sys_1; 2270 volatile efuse_rd_mac_spi_sys_2_reg_t rd_mac_spi_sys_2; 2271 volatile efuse_rd_mac_spi_sys_3_reg_t rd_mac_spi_sys_3; 2272 volatile efuse_rd_mac_spi_sys_4_reg_t rd_mac_spi_sys_4; 2273 volatile efuse_rd_mac_spi_sys_5_reg_t rd_mac_spi_sys_5; 2274 volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0; 2275 volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1; 2276 volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2; 2277 volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3; 2278 volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4; 2279 volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5; 2280 volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6; 2281 volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7; 2282 volatile efuse_rd_usr_data0_reg_t rd_usr_data0; 2283 volatile efuse_rd_usr_data1_reg_t rd_usr_data1; 2284 volatile efuse_rd_usr_data2_reg_t rd_usr_data2; 2285 volatile efuse_rd_usr_data3_reg_t rd_usr_data3; 2286 volatile efuse_rd_usr_data4_reg_t rd_usr_data4; 2287 volatile efuse_rd_usr_data5_reg_t rd_usr_data5; 2288 volatile efuse_rd_usr_data6_reg_t rd_usr_data6; 2289 volatile efuse_rd_usr_data7_reg_t rd_usr_data7; 2290 volatile efuse_rd_key0_data0_reg_t rd_key0_data0; 2291 volatile efuse_rd_key0_data1_reg_t rd_key0_data1; 2292 volatile efuse_rd_key0_data2_reg_t rd_key0_data2; 2293 volatile efuse_rd_key0_data3_reg_t rd_key0_data3; 2294 volatile efuse_rd_key0_data4_reg_t rd_key0_data4; 2295 volatile efuse_rd_key0_data5_reg_t rd_key0_data5; 2296 volatile efuse_rd_key0_data6_reg_t rd_key0_data6; 2297 volatile efuse_rd_key0_data7_reg_t rd_key0_data7; 2298 volatile efuse_rd_key1_data0_reg_t rd_key1_data0; 2299 volatile efuse_rd_key1_data1_reg_t rd_key1_data1; 2300 volatile efuse_rd_key1_data2_reg_t rd_key1_data2; 2301 volatile efuse_rd_key1_data3_reg_t rd_key1_data3; 2302 volatile efuse_rd_key1_data4_reg_t rd_key1_data4; 2303 volatile efuse_rd_key1_data5_reg_t rd_key1_data5; 2304 volatile efuse_rd_key1_data6_reg_t rd_key1_data6; 2305 volatile efuse_rd_key1_data7_reg_t rd_key1_data7; 2306 volatile efuse_rd_key2_data0_reg_t rd_key2_data0; 2307 volatile efuse_rd_key2_data1_reg_t rd_key2_data1; 2308 volatile efuse_rd_key2_data2_reg_t rd_key2_data2; 2309 volatile efuse_rd_key2_data3_reg_t rd_key2_data3; 2310 volatile efuse_rd_key2_data4_reg_t rd_key2_data4; 2311 volatile efuse_rd_key2_data5_reg_t rd_key2_data5; 2312 volatile efuse_rd_key2_data6_reg_t rd_key2_data6; 2313 volatile efuse_rd_key2_data7_reg_t rd_key2_data7; 2314 volatile efuse_rd_key3_data0_reg_t rd_key3_data0; 2315 volatile efuse_rd_key3_data1_reg_t rd_key3_data1; 2316 volatile efuse_rd_key3_data2_reg_t rd_key3_data2; 2317 volatile efuse_rd_key3_data3_reg_t rd_key3_data3; 2318 volatile efuse_rd_key3_data4_reg_t rd_key3_data4; 2319 volatile efuse_rd_key3_data5_reg_t rd_key3_data5; 2320 volatile efuse_rd_key3_data6_reg_t rd_key3_data6; 2321 volatile efuse_rd_key3_data7_reg_t rd_key3_data7; 2322 volatile efuse_rd_key4_data0_reg_t rd_key4_data0; 2323 volatile efuse_rd_key4_data1_reg_t rd_key4_data1; 2324 volatile efuse_rd_key4_data2_reg_t rd_key4_data2; 2325 volatile efuse_rd_key4_data3_reg_t rd_key4_data3; 2326 volatile efuse_rd_key4_data4_reg_t rd_key4_data4; 2327 volatile efuse_rd_key4_data5_reg_t rd_key4_data5; 2328 volatile efuse_rd_key4_data6_reg_t rd_key4_data6; 2329 volatile efuse_rd_key4_data7_reg_t rd_key4_data7; 2330 volatile efuse_rd_key5_data0_reg_t rd_key5_data0; 2331 volatile efuse_rd_key5_data1_reg_t rd_key5_data1; 2332 volatile efuse_rd_key5_data2_reg_t rd_key5_data2; 2333 volatile efuse_rd_key5_data3_reg_t rd_key5_data3; 2334 volatile efuse_rd_key5_data4_reg_t rd_key5_data4; 2335 volatile efuse_rd_key5_data5_reg_t rd_key5_data5; 2336 volatile efuse_rd_key5_data6_reg_t rd_key5_data6; 2337 volatile efuse_rd_key5_data7_reg_t rd_key5_data7; 2338 volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0; 2339 volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1; 2340 volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2; 2341 volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3; 2342 volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4; 2343 volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5; 2344 volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6; 2345 volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7; 2346 volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0; 2347 volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1; 2348 volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2; 2349 volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3; 2350 uint32_t reserved_18c; 2351 volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4; 2352 uint32_t reserved_194[11]; 2353 volatile efuse_rd_rs_err0_reg_t rd_rs_err0; 2354 volatile efuse_rd_rs_err1_reg_t rd_rs_err1; 2355 volatile efuse_clk_reg_t clk; 2356 volatile efuse_conf_reg_t conf; 2357 volatile efuse_status_reg_t status; 2358 volatile efuse_cmd_reg_t cmd; 2359 volatile efuse_int_raw_reg_t int_raw; 2360 volatile efuse_int_st_reg_t int_st; 2361 volatile efuse_int_ena_reg_t int_ena; 2362 volatile efuse_int_clr_reg_t int_clr; 2363 volatile efuse_dac_conf_reg_t dac_conf; 2364 volatile efuse_rd_tim_conf_reg_t rd_tim_conf; 2365 volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1; 2366 volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2; 2367 uint32_t reserved_1f8; 2368 volatile efuse_date_reg_t date; 2369 } efuse_dev_t; 2370 extern efuse_dev_t EFUSE; 2371 2372 #ifndef __cplusplus 2373 _Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure"); 2374 #endif 2375 2376 #ifdef __cplusplus 2377 } 2378 #endif 2379
