1 /** 2 * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #ifdef __cplusplus 10 extern "C" { 11 #endif 12 13 /** Group: PGM Data Register */ 14 /** Type of pgm_data0 register 15 * Register 0 that stores data to be programmed. 16 */ 17 typedef union { 18 struct { 19 /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; 20 * Configures the 0th 32-bit data to be programmed. 21 */ 22 uint32_t pgm_data_0:32; 23 }; 24 uint32_t val; 25 } efuse_pgm_data0_reg_t; 26 27 /** Type of pgm_data1 register 28 * Register 1 that stores data to be programmed. 29 */ 30 typedef union { 31 struct { 32 /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0; 33 * Configures the 1st 32-bit data to be programmed. 34 */ 35 uint32_t pgm_data_1:32; 36 }; 37 uint32_t val; 38 } efuse_pgm_data1_reg_t; 39 40 /** Type of pgm_data2 register 41 * Register 2 that stores data to be programmed. 42 */ 43 typedef union { 44 struct { 45 /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0; 46 * Configures the 2nd 32-bit data to be programmed. 47 */ 48 uint32_t pgm_data_2:32; 49 }; 50 uint32_t val; 51 } efuse_pgm_data2_reg_t; 52 53 /** Type of pgm_data3 register 54 * Register 3 that stores data to be programmed. 55 */ 56 typedef union { 57 struct { 58 /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0; 59 * Configures the 3rd 32-bit data to be programmed. 60 */ 61 uint32_t pgm_data_3:32; 62 }; 63 uint32_t val; 64 } efuse_pgm_data3_reg_t; 65 66 /** Type of pgm_data4 register 67 * Register 4 that stores data to be programmed. 68 */ 69 typedef union { 70 struct { 71 /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0; 72 * Configures the 4th 32-bit data to be programmed. 73 */ 74 uint32_t pgm_data_4:32; 75 }; 76 uint32_t val; 77 } efuse_pgm_data4_reg_t; 78 79 /** Type of pgm_data5 register 80 * Register 5 that stores data to be programmed. 81 */ 82 typedef union { 83 struct { 84 /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0; 85 * Configures the 5th 32-bit data to be programmed. 86 */ 87 uint32_t pgm_data_5:32; 88 }; 89 uint32_t val; 90 } efuse_pgm_data5_reg_t; 91 92 /** Type of pgm_data6 register 93 * Register 6 that stores data to be programmed. 94 */ 95 typedef union { 96 struct { 97 /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0; 98 * Configures the 6th 32-bit data to be programmed. 99 */ 100 uint32_t pgm_data_6:32; 101 }; 102 uint32_t val; 103 } efuse_pgm_data6_reg_t; 104 105 /** Type of pgm_data7 register 106 * Register 7 that stores data to be programmed. 107 */ 108 typedef union { 109 struct { 110 /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0; 111 * Configures the 7th 32-bit data to be programmed. 112 */ 113 uint32_t pgm_data_7:32; 114 }; 115 uint32_t val; 116 } efuse_pgm_data7_reg_t; 117 118 /** Type of pgm_check_value0 register 119 * Register 0 that stores the RS code to be programmed. 120 */ 121 typedef union { 122 struct { 123 /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0; 124 * Configures the 0th 32-bit RS code to be programmed. 125 */ 126 uint32_t pgm_rs_data_0:32; 127 }; 128 uint32_t val; 129 } efuse_pgm_check_value0_reg_t; 130 131 /** Type of pgm_check_value1 register 132 * Register 1 that stores the RS code to be programmed. 133 */ 134 typedef union { 135 struct { 136 /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0; 137 * Configures the 1st 32-bit RS code to be programmed. 138 */ 139 uint32_t pgm_rs_data_1:32; 140 }; 141 uint32_t val; 142 } efuse_pgm_check_value1_reg_t; 143 144 /** Type of pgm_check_value2 register 145 * Register 2 that stores the RS code to be programmed. 146 */ 147 typedef union { 148 struct { 149 /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0; 150 * Configures the 2nd 32-bit RS code to be programmed. 151 */ 152 uint32_t pgm_rs_data_2:32; 153 }; 154 uint32_t val; 155 } efuse_pgm_check_value2_reg_t; 156 157 158 /** Group: Read Data Register */ 159 /** Type of rd_wr_dis register 160 * BLOCK0 data register 0. 161 */ 162 typedef union { 163 struct { 164 /** wr_dis : RO; bitpos: [31:0]; default: 0; 165 * Represents whether programming of individual eFuse memory bit is disabled or 166 * enabled. 1: Disabled. 0 Enabled. 167 */ 168 uint32_t wr_dis:32; 169 }; 170 uint32_t val; 171 } efuse_rd_wr_dis_reg_t; 172 173 /** Type of rd_repeat_data0 register 174 * BLOCK0 data register 1. 175 */ 176 typedef union { 177 struct { 178 /** rd_dis : RO; bitpos: [6:0]; default: 0; 179 * Represents whether reading of individual eFuse block(block4~block10) is disabled or 180 * enabled. 1: disabled. 0: enabled. 181 */ 182 uint32_t rd_dis:7; 183 /** swap_uart_sdio_en : RO; bitpos: [7]; default: 0; 184 * Represents whether pad of uart and sdio is swapped or not. 1: swapped. 0: not 185 * swapped. 186 */ 187 uint32_t swap_uart_sdio_en:1; 188 /** dis_icache : RO; bitpos: [8]; default: 0; 189 * Represents whether icache is disabled or enabled. 1: disabled. 0: enabled. 190 */ 191 uint32_t dis_icache:1; 192 /** dis_usb_jtag : RO; bitpos: [9]; default: 0; 193 * Represents whether the function of usb switch to jtag is disabled or enabled. 1: 194 * disabled. 0: enabled. 195 */ 196 uint32_t dis_usb_jtag:1; 197 /** dis_download_icache : RO; bitpos: [10]; default: 0; 198 * Represents whether icache is disabled or enabled in Download mode. 1: disabled. 0: 199 * enabled. 200 */ 201 uint32_t dis_download_icache:1; 202 /** dis_usb_serial_jtag : RO; bitpos: [11]; default: 0; 203 * Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled. 204 */ 205 uint32_t dis_usb_serial_jtag:1; 206 /** dis_force_download : RO; bitpos: [12]; default: 0; 207 * Represents whether the function that forces chip into download mode is disabled or 208 * enabled. 1: disabled. 0: enabled. 209 */ 210 uint32_t dis_force_download:1; 211 /** spi_download_mspi_dis : RO; bitpos: [13]; default: 0; 212 * Represents whether SPI0 controller during boot_mode_download is disabled or 213 * enabled. 1: disabled. 0: enabled. 214 */ 215 uint32_t spi_download_mspi_dis:1; 216 /** dis_twai : RO; bitpos: [14]; default: 0; 217 * Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled. 218 */ 219 uint32_t dis_twai:1; 220 /** jtag_sel_enable : RO; bitpos: [15]; default: 0; 221 * Represents whether the selection between usb_to_jtag and pad_to_jtag through 222 * strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 223 * is enabled or disabled. 1: enabled. 0: disabled. 224 */ 225 uint32_t jtag_sel_enable:1; 226 /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0; 227 * Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: 228 * enabled. 229 */ 230 uint32_t soft_dis_jtag:3; 231 /** dis_pad_jtag : RO; bitpos: [19]; default: 0; 232 * Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: 233 * enabled. 234 */ 235 uint32_t dis_pad_jtag:1; 236 /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0; 237 * Represents whether flash encrypt function is disabled or enabled(except in SPI boot 238 * mode). 1: disabled. 0: enabled. 239 */ 240 uint32_t dis_download_manual_encrypt:1; 241 /** usb_drefh : RO; bitpos: [22:21]; default: 0; 242 * Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV. 243 */ 244 uint32_t usb_drefh:2; 245 /** usb_drefl : RO; bitpos: [24:23]; default: 0; 246 * Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV. 247 */ 248 uint32_t usb_drefl:2; 249 /** usb_exchg_pins : RO; bitpos: [25]; default: 0; 250 * Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged. 251 */ 252 uint32_t usb_exchg_pins:1; 253 /** vdd_spi_as_gpio : RO; bitpos: [26]; default: 0; 254 * Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not 255 * functioned. 256 */ 257 uint32_t vdd_spi_as_gpio:1; 258 /** rpt4_reserved0_2 : RO; bitpos: [28:27]; default: 0; 259 * Reserved. 260 */ 261 uint32_t rpt4_reserved0_2:2; 262 /** rpt4_reserved0_1 : RO; bitpos: [29]; default: 0; 263 * Reserved. 264 */ 265 uint32_t rpt4_reserved0_1:1; 266 /** rpt4_reserved0_0 : RO; bitpos: [31:30]; default: 0; 267 * Reserved. 268 */ 269 uint32_t rpt4_reserved0_0:2; 270 }; 271 uint32_t val; 272 } efuse_rd_repeat_data0_reg_t; 273 274 /** Type of rd_repeat_data1 register 275 * BLOCK0 data register 2. 276 */ 277 typedef union { 278 struct { 279 /** rpt4_reserved1_0 : RO; bitpos: [15:0]; default: 0; 280 * Reserved. 281 */ 282 uint32_t rpt4_reserved1_0:16; 283 /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0; 284 * Represents whether RTC watchdog timeout threshold is selected at startup. 1: 285 * selected. 0: not selected. 286 */ 287 uint32_t wdt_delay_sel:2; 288 /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0; 289 * Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of 290 * 1: enabled. Even number of 1: disabled. 291 */ 292 uint32_t spi_boot_crypt_cnt:3; 293 /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0; 294 * Represents whether revoking first secure boot key is enabled or disabled. 1: 295 * enabled. 0: disabled. 296 */ 297 uint32_t secure_boot_key_revoke0:1; 298 /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0; 299 * Represents whether revoking second secure boot key is enabled or disabled. 1: 300 * enabled. 0: disabled. 301 */ 302 uint32_t secure_boot_key_revoke1:1; 303 /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0; 304 * Represents whether revoking third secure boot key is enabled or disabled. 1: 305 * enabled. 0: disabled. 306 */ 307 uint32_t secure_boot_key_revoke2:1; 308 /** key_purpose_0 : RO; bitpos: [27:24]; default: 0; 309 * Represents the purpose of Key0. 310 */ 311 uint32_t key_purpose_0:4; 312 /** key_purpose_1 : RO; bitpos: [31:28]; default: 0; 313 * Represents the purpose of Key1. 314 */ 315 uint32_t key_purpose_1:4; 316 }; 317 uint32_t val; 318 } efuse_rd_repeat_data1_reg_t; 319 320 /** Type of rd_repeat_data2 register 321 * BLOCK0 data register 3. 322 */ 323 typedef union { 324 struct { 325 /** key_purpose_2 : RO; bitpos: [3:0]; default: 0; 326 * Represents the purpose of Key2. 327 */ 328 uint32_t key_purpose_2:4; 329 /** key_purpose_3 : RO; bitpos: [7:4]; default: 0; 330 * Represents the purpose of Key3. 331 */ 332 uint32_t key_purpose_3:4; 333 /** key_purpose_4 : RO; bitpos: [11:8]; default: 0; 334 * Represents the purpose of Key4. 335 */ 336 uint32_t key_purpose_4:4; 337 /** key_purpose_5 : RO; bitpos: [15:12]; default: 0; 338 * Represents the purpose of Key5. 339 */ 340 uint32_t key_purpose_5:4; 341 /** sec_dpa_level : RO; bitpos: [17:16]; default: 0; 342 * Represents the spa secure level by configuring the clock random divide mode. 343 */ 344 uint32_t sec_dpa_level:2; 345 /** crypt_dpa_enable : RO; bitpos: [18]; default: 0; 346 * Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled. 347 */ 348 uint32_t crypt_dpa_enable:1; 349 /** rpt4_reserved2_1 : RO; bitpos: [19]; default: 1; 350 * Reserved. 351 */ 352 uint32_t rpt4_reserved2_1:1; 353 /** secure_boot_en : RO; bitpos: [20]; default: 0; 354 * Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled. 355 */ 356 uint32_t secure_boot_en:1; 357 /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0; 358 * Represents whether revoking aggressive secure boot is enabled or disabled. 1: 359 * enabled. 0: disabled. 360 */ 361 uint32_t secure_boot_aggressive_revoke:1; 362 /** rpt4_reserved2_0 : RO; bitpos: [27:22]; default: 0; 363 * Reserved. 364 */ 365 uint32_t rpt4_reserved2_0:6; 366 /** flash_tpuw : RO; bitpos: [31:28]; default: 0; 367 * Represents the flash waiting time after power-up, in unit of ms. When the value 368 * less than 15, the waiting time is the programmed value. Otherwise, the waiting time 369 * is 2 times the programmed value. 370 */ 371 uint32_t flash_tpuw:4; 372 }; 373 uint32_t val; 374 } efuse_rd_repeat_data2_reg_t; 375 376 /** Type of rd_repeat_data3 register 377 * BLOCK0 data register 4. 378 */ 379 typedef union { 380 struct { 381 /** dis_download_mode : RO; bitpos: [0]; default: 0; 382 * Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled. 383 */ 384 uint32_t dis_download_mode:1; 385 /** dis_direct_boot : RO; bitpos: [1]; default: 0; 386 * Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled. 387 */ 388 uint32_t dis_direct_boot:1; 389 /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0; 390 * Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 391 * 0: enabled. 392 */ 393 uint32_t dis_usb_serial_jtag_rom_print:1; 394 /** rpt4_reserved3_5 : RO; bitpos: [3]; default: 0; 395 * Reserved. 396 */ 397 uint32_t rpt4_reserved3_5:1; 398 /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0; 399 * Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: 400 * disabled. 0: enabled. 401 */ 402 uint32_t dis_usb_serial_jtag_download_mode:1; 403 /** enable_security_download : RO; bitpos: [5]; default: 0; 404 * Represents whether security download is enabled or disabled. 1: enabled. 0: 405 * disabled. 406 */ 407 uint32_t enable_security_download:1; 408 /** uart_print_control : RO; bitpos: [7:6]; default: 0; 409 * Represents the type of UART printing. 00: force enable printing. 01: enable 410 * printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset 411 * at high level. 11: force disable printing. 412 */ 413 uint32_t uart_print_control:2; 414 /** rpt4_reserved3_4 : RO; bitpos: [8]; default: 0; 415 * Reserved. 416 */ 417 uint32_t rpt4_reserved3_4:1; 418 /** rpt4_reserved3_3 : RO; bitpos: [9]; default: 0; 419 * Reserved. 420 */ 421 uint32_t rpt4_reserved3_3:1; 422 /** rpt4_reserved3_2 : RO; bitpos: [11:10]; default: 0; 423 * Reserved. 424 */ 425 uint32_t rpt4_reserved3_2:2; 426 /** rpt4_reserved3_1 : RO; bitpos: [12]; default: 0; 427 * Reserved. 428 */ 429 uint32_t rpt4_reserved3_1:1; 430 /** force_send_resume : RO; bitpos: [13]; default: 0; 431 * Represents whether ROM code is forced to send a resume command during SPI boot. 1: 432 * forced. 0:not forced. 433 */ 434 uint32_t force_send_resume:1; 435 /** secure_version : RO; bitpos: [29:14]; default: 0; 436 * Represents the version used by ESP-IDF anti-rollback feature. 437 */ 438 uint32_t secure_version:16; 439 /** secure_boot_disable_fast_wake : RO; bitpos: [30]; default: 0; 440 * Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is 441 * enabled. 1: disabled. 0: enabled. 442 */ 443 uint32_t secure_boot_disable_fast_wake:1; 444 /** rpt4_reserved3_0 : RO; bitpos: [31]; default: 0; 445 * Reserved. 446 */ 447 uint32_t rpt4_reserved3_0:1; 448 }; 449 uint32_t val; 450 } efuse_rd_repeat_data3_reg_t; 451 452 /** Type of rd_repeat_data4 register 453 * BLOCK0 data register 5. 454 */ 455 typedef union { 456 struct { 457 /** disable_wafer_version_major : R; bitpos: [0]; default: 0; 458 * Disables check of wafer version major 459 */ 460 uint32_t disable_wafer_version_major:1; 461 /** disable_blk_version_major : R; bitpos: [1]; default: 0; 462 * Disables check of blk version major 463 */ 464 uint32_t disable_blk_version_major:1; 465 /** reserved_0_162 : R; bitpos: [23:2]; default: 0; 466 * reserved 467 */ 468 uint32_t reserved_0_162:22; 469 /** rpt4_reserved4_0 : RO; bitpos: [31:24]; default: 0; 470 * Reserved. 471 */ 472 uint32_t rpt4_reserved4_0:8; 473 }; 474 uint32_t val; 475 } efuse_rd_repeat_data4_reg_t; 476 477 /** Type of rd_mac_spi_sys_0 register 478 * BLOCK1 data register $n. 479 */ 480 typedef union { 481 struct { 482 /** mac_0 : RO; bitpos: [31:0]; default: 0; 483 * Stores the low 32 bits of MAC address. 484 */ 485 uint32_t mac_0:32; 486 }; 487 uint32_t val; 488 } efuse_rd_mac_spi_sys_0_reg_t; 489 490 /** Type of rd_mac_spi_sys_1 register 491 * BLOCK1 data register $n. 492 */ 493 typedef union { 494 struct { 495 /** mac_1 : RO; bitpos: [15:0]; default: 0; 496 * Stores the high 16 bits of MAC address. 497 */ 498 uint32_t mac_1:16; 499 /** mac_ext : RO; bitpos: [31:16]; default: 0; 500 * Stores the extended bits of MAC address. 501 */ 502 uint32_t mac_ext:16; 503 }; 504 uint32_t val; 505 } efuse_rd_mac_spi_sys_1_reg_t; 506 507 /** Type of rd_mac_spi_sys_2 register 508 * BLOCK1 data register $n. 509 */ 510 typedef union { 511 struct { 512 /** active_hp_dbias : RO; bitpos: [4:0]; default: 0; 513 * Stores the active hp dbias. 514 */ 515 uint32_t active_hp_dbias:5; 516 /** active_lp_dbias : RO; bitpos: [9:5]; default: 0; 517 * Stores the active lp dbias. 518 */ 519 uint32_t active_lp_dbias:5; 520 /** lslp_hp_dbg : RO; bitpos: [11:10]; default: 0; 521 * Stores the lslp hp dbg. 522 */ 523 uint32_t lslp_hp_dbg:2; 524 /** lslp_hp_dbias : RO; bitpos: [15:12]; default: 0; 525 * Stores the lslp hp dbias. 526 */ 527 uint32_t lslp_hp_dbias:4; 528 /** dslp_lp_dbg : RO; bitpos: [18:16]; default: 0; 529 * Stores the dslp lp dbg. 530 */ 531 uint32_t dslp_lp_dbg:3; 532 /** dslp_lp_dbias : RO; bitpos: [22:19]; default: 0; 533 * Stores the dslp lp dbias. 534 */ 535 uint32_t dslp_lp_dbias:4; 536 /** dbias_vol_gap : RO; bitpos: [27:23]; default: 0; 537 * Stores the hp and lp dbias vol gap. 538 */ 539 uint32_t dbias_vol_gap:5; 540 /** spi_pad_conf_1 : RO; bitpos: [31:28]; default: 0; 541 * Stores the first part of SPI_PAD_CONF. 542 */ 543 uint32_t spi_pad_conf_1:4; 544 }; 545 uint32_t val; 546 } efuse_rd_mac_spi_sys_2_reg_t; 547 548 /** Type of rd_mac_spi_sys_3 register 549 * BLOCK1 data register $n. 550 */ 551 typedef union { 552 struct { 553 /** spi_pad_conf_2 : RO; bitpos: [17:0]; default: 0; 554 * Stores the second part of SPI_PAD_CONF. 555 */ 556 uint32_t spi_pad_conf_2:18; 557 /** wafer_version_minor : R; bitpos: [21:18]; default: 0; */ 558 uint32_t wafer_version_minor:4; 559 /** wafer_version_major : R; bitpos: [23:22]; default: 0; */ 560 uint32_t wafer_version_major:2; 561 /** pkg_version : R; bitpos: [26:24]; default: 0; 562 * Package version 563 */ 564 uint32_t pkg_version:3; 565 /** blk_version_minor : R; bitpos: [29:27]; default: 0; 566 * BLK_VERSION_MINOR of BLOCK2 567 */ 568 uint32_t blk_version_minor:3; 569 /** blk_version_major : R; bitpos: [31:30]; default: 0; 570 * BLK_VERSION_MAJOR of BLOCK2 571 */ 572 uint32_t blk_version_major:2; 573 }; 574 uint32_t val; 575 } efuse_rd_mac_spi_sys_3_reg_t; 576 577 /** Type of rd_mac_spi_sys_4 register 578 * BLOCK1 data register $n. 579 */ 580 typedef union { 581 struct { 582 /** flash_cap : R; bitpos: [2:0]; default: 0; */ 583 uint32_t flash_cap:3; 584 /** flash_temp : R; bitpos: [4:3]; default: 0; */ 585 uint32_t flash_temp:2; 586 /** flash_vendor : R; bitpos: [7:5]; default: 0; */ 587 uint32_t flash_vendor:3; 588 /** reserved_1_136 : R; bitpos: [31:8]; default: 0; 589 * reserved 590 */ 591 uint32_t reserved_1_136:24; 592 }; 593 uint32_t val; 594 } efuse_rd_mac_spi_sys_4_reg_t; 595 596 /** Type of rd_mac_spi_sys_5 register 597 * BLOCK1 data register $n. 598 */ 599 typedef union { 600 struct { 601 /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0; 602 * Stores the second 32 bits of the zeroth part of system data. 603 */ 604 uint32_t sys_data_part0_2:32; 605 }; 606 uint32_t val; 607 } efuse_rd_mac_spi_sys_5_reg_t; 608 609 /** Type of rd_sys_part1_data0 register 610 * Register $n of BLOCK2 (system). 611 */ 612 typedef union { 613 struct { 614 /** optional_unique_id : R; bitpos: [31:0]; default: 0; 615 * Optional unique 128-bit ID 616 */ 617 uint32_t optional_unique_id:32; 618 }; 619 uint32_t val; 620 } efuse_rd_sys_part1_data0_reg_t; 621 622 /** Type of rd_sys_part1_data1 register 623 * Register $n of BLOCK2 (system). 624 */ 625 typedef union { 626 struct { 627 /** optional_unique_id_1 : R; bitpos: [31:0]; default: 0; 628 * Optional unique 128-bit ID 629 */ 630 uint32_t optional_unique_id_1:32; 631 }; 632 uint32_t val; 633 } efuse_rd_sys_part1_data1_reg_t; 634 635 /** Type of rd_sys_part1_data2 register 636 * Register $n of BLOCK2 (system). 637 */ 638 typedef union { 639 struct { 640 /** optional_unique_id_2 : R; bitpos: [31:0]; default: 0; 641 * Optional unique 128-bit ID 642 */ 643 uint32_t optional_unique_id_2:32; 644 }; 645 uint32_t val; 646 } efuse_rd_sys_part1_data2_reg_t; 647 648 /** Type of rd_sys_part1_data3 register 649 * Register $n of BLOCK2 (system). 650 */ 651 typedef union { 652 struct { 653 /** optional_unique_id_3 : R; bitpos: [31:0]; default: 0; 654 * Optional unique 128-bit ID 655 */ 656 uint32_t optional_unique_id_3:32; 657 }; 658 uint32_t val; 659 } efuse_rd_sys_part1_data3_reg_t; 660 661 /** Type of rd_sys_part1_data4 register 662 * Register $n of BLOCK2 (system). 663 */ 664 typedef union { 665 struct { 666 /** temp_calib : R; bitpos: [8:0]; default: 0; 667 * Temperature calibration data 668 */ 669 uint32_t temp_calib:9; 670 /** ocode : R; bitpos: [16:9]; default: 0; 671 * ADC OCode 672 */ 673 uint32_t ocode:8; 674 /** adc1_init_code_atten0 : R; bitpos: [26:17]; default: 0; 675 * ADC1 init code at atten0 676 */ 677 uint32_t adc1_init_code_atten0:10; 678 /** adc1_init_code_atten1 : R; bitpos: [31:27]; default: 0; 679 * ADC1 init code at atten1 680 */ 681 uint32_t adc1_init_code_atten1:5; 682 }; 683 uint32_t val; 684 } efuse_rd_sys_part1_data4_reg_t; 685 686 /** Type of rd_sys_part1_data5 register 687 * Register $n of BLOCK2 (system). 688 */ 689 typedef union { 690 struct { 691 /** adc1_init_code_atten1_1 : R; bitpos: [4:0]; default: 0; 692 * ADC1 init code at atten1 693 */ 694 uint32_t adc1_init_code_atten1_1:5; 695 /** adc1_init_code_atten2 : R; bitpos: [14:5]; default: 0; 696 * ADC1 init code at atten2 697 */ 698 uint32_t adc1_init_code_atten2:10; 699 /** adc1_init_code_atten3 : R; bitpos: [24:15]; default: 0; 700 * ADC1 init code at atten3 701 */ 702 uint32_t adc1_init_code_atten3:10; 703 /** adc1_cal_vol_atten0 : R; bitpos: [31:25]; default: 0; 704 * ADC1 calibration voltage at atten0 705 */ 706 uint32_t adc1_cal_vol_atten0:7; 707 }; 708 uint32_t val; 709 } efuse_rd_sys_part1_data5_reg_t; 710 711 /** Type of rd_sys_part1_data6 register 712 * Register $n of BLOCK2 (system). 713 */ 714 typedef union { 715 struct { 716 /** adc1_cal_vol_atten0_1 : R; bitpos: [2:0]; default: 0; 717 * ADC1 calibration voltage at atten0 718 */ 719 uint32_t adc1_cal_vol_atten0_1:3; 720 /** adc1_cal_vol_atten1 : R; bitpos: [12:3]; default: 0; 721 * ADC1 calibration voltage at atten1 722 */ 723 uint32_t adc1_cal_vol_atten1:10; 724 /** adc1_cal_vol_atten2 : R; bitpos: [22:13]; default: 0; 725 * ADC1 calibration voltage at atten2 726 */ 727 uint32_t adc1_cal_vol_atten2:10; 728 /** adc1_cal_vol_atten3 : R; bitpos: [31:23]; default: 0; 729 * ADC1 calibration voltage at atten3 730 */ 731 uint32_t adc1_cal_vol_atten3:9; 732 }; 733 uint32_t val; 734 } efuse_rd_sys_part1_data6_reg_t; 735 736 /** Type of rd_sys_part1_data7 register 737 * Register $n of BLOCK2 (system). 738 */ 739 typedef union { 740 struct { 741 /** adc1_cal_vol_atten3_1 : R; bitpos: [0]; default: 0; 742 * ADC1 calibration voltage at atten3 743 */ 744 uint32_t adc1_cal_vol_atten3_1:1; 745 /** adc1_init_code_atten0_ch0 : R; bitpos: [4:1]; default: 0; 746 * ADC1 init code at atten0 ch0 747 */ 748 uint32_t adc1_init_code_atten0_ch0:4; 749 /** adc1_init_code_atten0_ch1 : R; bitpos: [8:5]; default: 0; 750 * ADC1 init code at atten0 ch1 751 */ 752 uint32_t adc1_init_code_atten0_ch1:4; 753 /** adc1_init_code_atten0_ch2 : R; bitpos: [12:9]; default: 0; 754 * ADC1 init code at atten0 ch2 755 */ 756 uint32_t adc1_init_code_atten0_ch2:4; 757 /** adc1_init_code_atten0_ch3 : R; bitpos: [16:13]; default: 0; 758 * ADC1 init code at atten0 ch3 759 */ 760 uint32_t adc1_init_code_atten0_ch3:4; 761 /** adc1_init_code_atten0_ch4 : R; bitpos: [20:17]; default: 0; 762 * ADC1 init code at atten0 ch4 763 */ 764 uint32_t adc1_init_code_atten0_ch4:4; 765 /** adc1_init_code_atten0_ch5 : R; bitpos: [24:21]; default: 0; 766 * ADC1 init code at atten0 ch5 767 */ 768 uint32_t adc1_init_code_atten0_ch5:4; 769 /** adc1_init_code_atten0_ch6 : R; bitpos: [28:25]; default: 0; 770 * ADC1 init code at atten0 ch6 771 */ 772 uint32_t adc1_init_code_atten0_ch6:4; 773 /** reserved_2_253 : R; bitpos: [31:29]; default: 0; 774 * reserved 775 */ 776 uint32_t reserved_2_253:3; 777 }; 778 uint32_t val; 779 } efuse_rd_sys_part1_data7_reg_t; 780 781 /** Type of rd_usr_data0 register 782 * Register $n of BLOCK3 (user). 783 */ 784 typedef union { 785 struct { 786 /** usr_data0 : RO; bitpos: [31:0]; default: 0; 787 * Stores the zeroth 32 bits of BLOCK3 (user). 788 */ 789 uint32_t usr_data0:32; 790 }; 791 uint32_t val; 792 } efuse_rd_usr_data0_reg_t; 793 794 /** Type of rd_usr_data1 register 795 * Register $n of BLOCK3 (user). 796 */ 797 typedef union { 798 struct { 799 /** usr_data1 : RO; bitpos: [31:0]; default: 0; 800 * Stores the first 32 bits of BLOCK3 (user). 801 */ 802 uint32_t usr_data1:32; 803 }; 804 uint32_t val; 805 } efuse_rd_usr_data1_reg_t; 806 807 /** Type of rd_usr_data2 register 808 * Register $n of BLOCK3 (user). 809 */ 810 typedef union { 811 struct { 812 /** usr_data2 : RO; bitpos: [31:0]; default: 0; 813 * Stores the second 32 bits of BLOCK3 (user). 814 */ 815 uint32_t usr_data2:32; 816 }; 817 uint32_t val; 818 } efuse_rd_usr_data2_reg_t; 819 820 /** Type of rd_usr_data3 register 821 * Register $n of BLOCK3 (user). 822 */ 823 typedef union { 824 struct { 825 /** usr_data3 : RO; bitpos: [31:0]; default: 0; 826 * Stores the third 32 bits of BLOCK3 (user). 827 */ 828 uint32_t usr_data3:32; 829 }; 830 uint32_t val; 831 } efuse_rd_usr_data3_reg_t; 832 833 /** Type of rd_usr_data4 register 834 * Register $n of BLOCK3 (user). 835 */ 836 typedef union { 837 struct { 838 /** usr_data4 : RO; bitpos: [31:0]; default: 0; 839 * Stores the fourth 32 bits of BLOCK3 (user). 840 */ 841 uint32_t usr_data4:32; 842 }; 843 uint32_t val; 844 } efuse_rd_usr_data4_reg_t; 845 846 /** Type of rd_usr_data5 register 847 * Register $n of BLOCK3 (user). 848 */ 849 typedef union { 850 struct { 851 /** usr_data5 : RO; bitpos: [31:0]; default: 0; 852 * Stores the fifth 32 bits of BLOCK3 (user). 853 */ 854 uint32_t usr_data5:32; 855 }; 856 uint32_t val; 857 } efuse_rd_usr_data5_reg_t; 858 859 /** Type of rd_usr_data6 register 860 * Register $n of BLOCK3 (user). 861 */ 862 typedef union { 863 struct { 864 /** reserved_3_192 : R; bitpos: [7:0]; default: 0; 865 * reserved 866 */ 867 uint32_t reserved_3_192:8; 868 /** custom_mac : R; bitpos: [31:8]; default: 0; 869 * Custom MAC 870 */ 871 uint32_t custom_mac:24; 872 }; 873 uint32_t val; 874 } efuse_rd_usr_data6_reg_t; 875 876 /** Type of rd_usr_data7 register 877 * Register $n of BLOCK3 (user). 878 */ 879 typedef union { 880 struct { 881 /** custom_mac_1 : R; bitpos: [23:0]; default: 0; 882 * Custom MAC 883 */ 884 uint32_t custom_mac_1:24; 885 /** reserved_3_248 : R; bitpos: [31:24]; default: 0; 886 * reserved 887 */ 888 uint32_t reserved_3_248:8; 889 }; 890 uint32_t val; 891 } efuse_rd_usr_data7_reg_t; 892 893 /** Type of rd_key0_data0 register 894 * Register $n of BLOCK4 (KEY0). 895 */ 896 typedef union { 897 struct { 898 /** key0_data0 : RO; bitpos: [31:0]; default: 0; 899 * Stores the zeroth 32 bits of KEY0. 900 */ 901 uint32_t key0_data0:32; 902 }; 903 uint32_t val; 904 } efuse_rd_key0_data0_reg_t; 905 906 /** Type of rd_key0_data1 register 907 * Register $n of BLOCK4 (KEY0). 908 */ 909 typedef union { 910 struct { 911 /** key0_data1 : RO; bitpos: [31:0]; default: 0; 912 * Stores the first 32 bits of KEY0. 913 */ 914 uint32_t key0_data1:32; 915 }; 916 uint32_t val; 917 } efuse_rd_key0_data1_reg_t; 918 919 /** Type of rd_key0_data2 register 920 * Register $n of BLOCK4 (KEY0). 921 */ 922 typedef union { 923 struct { 924 /** key0_data2 : RO; bitpos: [31:0]; default: 0; 925 * Stores the second 32 bits of KEY0. 926 */ 927 uint32_t key0_data2:32; 928 }; 929 uint32_t val; 930 } efuse_rd_key0_data2_reg_t; 931 932 /** Type of rd_key0_data3 register 933 * Register $n of BLOCK4 (KEY0). 934 */ 935 typedef union { 936 struct { 937 /** key0_data3 : RO; bitpos: [31:0]; default: 0; 938 * Stores the third 32 bits of KEY0. 939 */ 940 uint32_t key0_data3:32; 941 }; 942 uint32_t val; 943 } efuse_rd_key0_data3_reg_t; 944 945 /** Type of rd_key0_data4 register 946 * Register $n of BLOCK4 (KEY0). 947 */ 948 typedef union { 949 struct { 950 /** key0_data4 : RO; bitpos: [31:0]; default: 0; 951 * Stores the fourth 32 bits of KEY0. 952 */ 953 uint32_t key0_data4:32; 954 }; 955 uint32_t val; 956 } efuse_rd_key0_data4_reg_t; 957 958 /** Type of rd_key0_data5 register 959 * Register $n of BLOCK4 (KEY0). 960 */ 961 typedef union { 962 struct { 963 /** key0_data5 : RO; bitpos: [31:0]; default: 0; 964 * Stores the fifth 32 bits of KEY0. 965 */ 966 uint32_t key0_data5:32; 967 }; 968 uint32_t val; 969 } efuse_rd_key0_data5_reg_t; 970 971 /** Type of rd_key0_data6 register 972 * Register $n of BLOCK4 (KEY0). 973 */ 974 typedef union { 975 struct { 976 /** key0_data6 : RO; bitpos: [31:0]; default: 0; 977 * Stores the sixth 32 bits of KEY0. 978 */ 979 uint32_t key0_data6:32; 980 }; 981 uint32_t val; 982 } efuse_rd_key0_data6_reg_t; 983 984 /** Type of rd_key0_data7 register 985 * Register $n of BLOCK4 (KEY0). 986 */ 987 typedef union { 988 struct { 989 /** key0_data7 : RO; bitpos: [31:0]; default: 0; 990 * Stores the seventh 32 bits of KEY0. 991 */ 992 uint32_t key0_data7:32; 993 }; 994 uint32_t val; 995 } efuse_rd_key0_data7_reg_t; 996 997 /** Type of rd_key1_data0 register 998 * Register $n of BLOCK5 (KEY1). 999 */ 1000 typedef union { 1001 struct { 1002 /** key1_data0 : RO; bitpos: [31:0]; default: 0; 1003 * Stores the zeroth 32 bits of KEY1. 1004 */ 1005 uint32_t key1_data0:32; 1006 }; 1007 uint32_t val; 1008 } efuse_rd_key1_data0_reg_t; 1009 1010 /** Type of rd_key1_data1 register 1011 * Register $n of BLOCK5 (KEY1). 1012 */ 1013 typedef union { 1014 struct { 1015 /** key1_data1 : RO; bitpos: [31:0]; default: 0; 1016 * Stores the first 32 bits of KEY1. 1017 */ 1018 uint32_t key1_data1:32; 1019 }; 1020 uint32_t val; 1021 } efuse_rd_key1_data1_reg_t; 1022 1023 /** Type of rd_key1_data2 register 1024 * Register $n of BLOCK5 (KEY1). 1025 */ 1026 typedef union { 1027 struct { 1028 /** key1_data2 : RO; bitpos: [31:0]; default: 0; 1029 * Stores the second 32 bits of KEY1. 1030 */ 1031 uint32_t key1_data2:32; 1032 }; 1033 uint32_t val; 1034 } efuse_rd_key1_data2_reg_t; 1035 1036 /** Type of rd_key1_data3 register 1037 * Register $n of BLOCK5 (KEY1). 1038 */ 1039 typedef union { 1040 struct { 1041 /** key1_data3 : RO; bitpos: [31:0]; default: 0; 1042 * Stores the third 32 bits of KEY1. 1043 */ 1044 uint32_t key1_data3:32; 1045 }; 1046 uint32_t val; 1047 } efuse_rd_key1_data3_reg_t; 1048 1049 /** Type of rd_key1_data4 register 1050 * Register $n of BLOCK5 (KEY1). 1051 */ 1052 typedef union { 1053 struct { 1054 /** key1_data4 : RO; bitpos: [31:0]; default: 0; 1055 * Stores the fourth 32 bits of KEY1. 1056 */ 1057 uint32_t key1_data4:32; 1058 }; 1059 uint32_t val; 1060 } efuse_rd_key1_data4_reg_t; 1061 1062 /** Type of rd_key1_data5 register 1063 * Register $n of BLOCK5 (KEY1). 1064 */ 1065 typedef union { 1066 struct { 1067 /** key1_data5 : RO; bitpos: [31:0]; default: 0; 1068 * Stores the fifth 32 bits of KEY1. 1069 */ 1070 uint32_t key1_data5:32; 1071 }; 1072 uint32_t val; 1073 } efuse_rd_key1_data5_reg_t; 1074 1075 /** Type of rd_key1_data6 register 1076 * Register $n of BLOCK5 (KEY1). 1077 */ 1078 typedef union { 1079 struct { 1080 /** key1_data6 : RO; bitpos: [31:0]; default: 0; 1081 * Stores the sixth 32 bits of KEY1. 1082 */ 1083 uint32_t key1_data6:32; 1084 }; 1085 uint32_t val; 1086 } efuse_rd_key1_data6_reg_t; 1087 1088 /** Type of rd_key1_data7 register 1089 * Register $n of BLOCK5 (KEY1). 1090 */ 1091 typedef union { 1092 struct { 1093 /** key1_data7 : RO; bitpos: [31:0]; default: 0; 1094 * Stores the seventh 32 bits of KEY1. 1095 */ 1096 uint32_t key1_data7:32; 1097 }; 1098 uint32_t val; 1099 } efuse_rd_key1_data7_reg_t; 1100 1101 /** Type of rd_key2_data0 register 1102 * Register $n of BLOCK6 (KEY2). 1103 */ 1104 typedef union { 1105 struct { 1106 /** key2_data0 : RO; bitpos: [31:0]; default: 0; 1107 * Stores the zeroth 32 bits of KEY2. 1108 */ 1109 uint32_t key2_data0:32; 1110 }; 1111 uint32_t val; 1112 } efuse_rd_key2_data0_reg_t; 1113 1114 /** Type of rd_key2_data1 register 1115 * Register $n of BLOCK6 (KEY2). 1116 */ 1117 typedef union { 1118 struct { 1119 /** key2_data1 : RO; bitpos: [31:0]; default: 0; 1120 * Stores the first 32 bits of KEY2. 1121 */ 1122 uint32_t key2_data1:32; 1123 }; 1124 uint32_t val; 1125 } efuse_rd_key2_data1_reg_t; 1126 1127 /** Type of rd_key2_data2 register 1128 * Register $n of BLOCK6 (KEY2). 1129 */ 1130 typedef union { 1131 struct { 1132 /** key2_data2 : RO; bitpos: [31:0]; default: 0; 1133 * Stores the second 32 bits of KEY2. 1134 */ 1135 uint32_t key2_data2:32; 1136 }; 1137 uint32_t val; 1138 } efuse_rd_key2_data2_reg_t; 1139 1140 /** Type of rd_key2_data3 register 1141 * Register $n of BLOCK6 (KEY2). 1142 */ 1143 typedef union { 1144 struct { 1145 /** key2_data3 : RO; bitpos: [31:0]; default: 0; 1146 * Stores the third 32 bits of KEY2. 1147 */ 1148 uint32_t key2_data3:32; 1149 }; 1150 uint32_t val; 1151 } efuse_rd_key2_data3_reg_t; 1152 1153 /** Type of rd_key2_data4 register 1154 * Register $n of BLOCK6 (KEY2). 1155 */ 1156 typedef union { 1157 struct { 1158 /** key2_data4 : RO; bitpos: [31:0]; default: 0; 1159 * Stores the fourth 32 bits of KEY2. 1160 */ 1161 uint32_t key2_data4:32; 1162 }; 1163 uint32_t val; 1164 } efuse_rd_key2_data4_reg_t; 1165 1166 /** Type of rd_key2_data5 register 1167 * Register $n of BLOCK6 (KEY2). 1168 */ 1169 typedef union { 1170 struct { 1171 /** key2_data5 : RO; bitpos: [31:0]; default: 0; 1172 * Stores the fifth 32 bits of KEY2. 1173 */ 1174 uint32_t key2_data5:32; 1175 }; 1176 uint32_t val; 1177 } efuse_rd_key2_data5_reg_t; 1178 1179 /** Type of rd_key2_data6 register 1180 * Register $n of BLOCK6 (KEY2). 1181 */ 1182 typedef union { 1183 struct { 1184 /** key2_data6 : RO; bitpos: [31:0]; default: 0; 1185 * Stores the sixth 32 bits of KEY2. 1186 */ 1187 uint32_t key2_data6:32; 1188 }; 1189 uint32_t val; 1190 } efuse_rd_key2_data6_reg_t; 1191 1192 /** Type of rd_key2_data7 register 1193 * Register $n of BLOCK6 (KEY2). 1194 */ 1195 typedef union { 1196 struct { 1197 /** key2_data7 : RO; bitpos: [31:0]; default: 0; 1198 * Stores the seventh 32 bits of KEY2. 1199 */ 1200 uint32_t key2_data7:32; 1201 }; 1202 uint32_t val; 1203 } efuse_rd_key2_data7_reg_t; 1204 1205 /** Type of rd_key3_data0 register 1206 * Register $n of BLOCK7 (KEY3). 1207 */ 1208 typedef union { 1209 struct { 1210 /** key3_data0 : RO; bitpos: [31:0]; default: 0; 1211 * Stores the zeroth 32 bits of KEY3. 1212 */ 1213 uint32_t key3_data0:32; 1214 }; 1215 uint32_t val; 1216 } efuse_rd_key3_data0_reg_t; 1217 1218 /** Type of rd_key3_data1 register 1219 * Register $n of BLOCK7 (KEY3). 1220 */ 1221 typedef union { 1222 struct { 1223 /** key3_data1 : RO; bitpos: [31:0]; default: 0; 1224 * Stores the first 32 bits of KEY3. 1225 */ 1226 uint32_t key3_data1:32; 1227 }; 1228 uint32_t val; 1229 } efuse_rd_key3_data1_reg_t; 1230 1231 /** Type of rd_key3_data2 register 1232 * Register $n of BLOCK7 (KEY3). 1233 */ 1234 typedef union { 1235 struct { 1236 /** key3_data2 : RO; bitpos: [31:0]; default: 0; 1237 * Stores the second 32 bits of KEY3. 1238 */ 1239 uint32_t key3_data2:32; 1240 }; 1241 uint32_t val; 1242 } efuse_rd_key3_data2_reg_t; 1243 1244 /** Type of rd_key3_data3 register 1245 * Register $n of BLOCK7 (KEY3). 1246 */ 1247 typedef union { 1248 struct { 1249 /** key3_data3 : RO; bitpos: [31:0]; default: 0; 1250 * Stores the third 32 bits of KEY3. 1251 */ 1252 uint32_t key3_data3:32; 1253 }; 1254 uint32_t val; 1255 } efuse_rd_key3_data3_reg_t; 1256 1257 /** Type of rd_key3_data4 register 1258 * Register $n of BLOCK7 (KEY3). 1259 */ 1260 typedef union { 1261 struct { 1262 /** key3_data4 : RO; bitpos: [31:0]; default: 0; 1263 * Stores the fourth 32 bits of KEY3. 1264 */ 1265 uint32_t key3_data4:32; 1266 }; 1267 uint32_t val; 1268 } efuse_rd_key3_data4_reg_t; 1269 1270 /** Type of rd_key3_data5 register 1271 * Register $n of BLOCK7 (KEY3). 1272 */ 1273 typedef union { 1274 struct { 1275 /** key3_data5 : RO; bitpos: [31:0]; default: 0; 1276 * Stores the fifth 32 bits of KEY3. 1277 */ 1278 uint32_t key3_data5:32; 1279 }; 1280 uint32_t val; 1281 } efuse_rd_key3_data5_reg_t; 1282 1283 /** Type of rd_key3_data6 register 1284 * Register $n of BLOCK7 (KEY3). 1285 */ 1286 typedef union { 1287 struct { 1288 /** key3_data6 : RO; bitpos: [31:0]; default: 0; 1289 * Stores the sixth 32 bits of KEY3. 1290 */ 1291 uint32_t key3_data6:32; 1292 }; 1293 uint32_t val; 1294 } efuse_rd_key3_data6_reg_t; 1295 1296 /** Type of rd_key3_data7 register 1297 * Register $n of BLOCK7 (KEY3). 1298 */ 1299 typedef union { 1300 struct { 1301 /** key3_data7 : RO; bitpos: [31:0]; default: 0; 1302 * Stores the seventh 32 bits of KEY3. 1303 */ 1304 uint32_t key3_data7:32; 1305 }; 1306 uint32_t val; 1307 } efuse_rd_key3_data7_reg_t; 1308 1309 /** Type of rd_key4_data0 register 1310 * Register $n of BLOCK8 (KEY4). 1311 */ 1312 typedef union { 1313 struct { 1314 /** key4_data0 : RO; bitpos: [31:0]; default: 0; 1315 * Stores the zeroth 32 bits of KEY4. 1316 */ 1317 uint32_t key4_data0:32; 1318 }; 1319 uint32_t val; 1320 } efuse_rd_key4_data0_reg_t; 1321 1322 /** Type of rd_key4_data1 register 1323 * Register $n of BLOCK8 (KEY4). 1324 */ 1325 typedef union { 1326 struct { 1327 /** key4_data1 : RO; bitpos: [31:0]; default: 0; 1328 * Stores the first 32 bits of KEY4. 1329 */ 1330 uint32_t key4_data1:32; 1331 }; 1332 uint32_t val; 1333 } efuse_rd_key4_data1_reg_t; 1334 1335 /** Type of rd_key4_data2 register 1336 * Register $n of BLOCK8 (KEY4). 1337 */ 1338 typedef union { 1339 struct { 1340 /** key4_data2 : RO; bitpos: [31:0]; default: 0; 1341 * Stores the second 32 bits of KEY4. 1342 */ 1343 uint32_t key4_data2:32; 1344 }; 1345 uint32_t val; 1346 } efuse_rd_key4_data2_reg_t; 1347 1348 /** Type of rd_key4_data3 register 1349 * Register $n of BLOCK8 (KEY4). 1350 */ 1351 typedef union { 1352 struct { 1353 /** key4_data3 : RO; bitpos: [31:0]; default: 0; 1354 * Stores the third 32 bits of KEY4. 1355 */ 1356 uint32_t key4_data3:32; 1357 }; 1358 uint32_t val; 1359 } efuse_rd_key4_data3_reg_t; 1360 1361 /** Type of rd_key4_data4 register 1362 * Register $n of BLOCK8 (KEY4). 1363 */ 1364 typedef union { 1365 struct { 1366 /** key4_data4 : RO; bitpos: [31:0]; default: 0; 1367 * Stores the fourth 32 bits of KEY4. 1368 */ 1369 uint32_t key4_data4:32; 1370 }; 1371 uint32_t val; 1372 } efuse_rd_key4_data4_reg_t; 1373 1374 /** Type of rd_key4_data5 register 1375 * Register $n of BLOCK8 (KEY4). 1376 */ 1377 typedef union { 1378 struct { 1379 /** key4_data5 : RO; bitpos: [31:0]; default: 0; 1380 * Stores the fifth 32 bits of KEY4. 1381 */ 1382 uint32_t key4_data5:32; 1383 }; 1384 uint32_t val; 1385 } efuse_rd_key4_data5_reg_t; 1386 1387 /** Type of rd_key4_data6 register 1388 * Register $n of BLOCK8 (KEY4). 1389 */ 1390 typedef union { 1391 struct { 1392 /** key4_data6 : RO; bitpos: [31:0]; default: 0; 1393 * Stores the sixth 32 bits of KEY4. 1394 */ 1395 uint32_t key4_data6:32; 1396 }; 1397 uint32_t val; 1398 } efuse_rd_key4_data6_reg_t; 1399 1400 /** Type of rd_key4_data7 register 1401 * Register $n of BLOCK8 (KEY4). 1402 */ 1403 typedef union { 1404 struct { 1405 /** key4_data7 : RO; bitpos: [31:0]; default: 0; 1406 * Stores the seventh 32 bits of KEY4. 1407 */ 1408 uint32_t key4_data7:32; 1409 }; 1410 uint32_t val; 1411 } efuse_rd_key4_data7_reg_t; 1412 1413 /** Type of rd_key5_data0 register 1414 * Register $n of BLOCK9 (KEY5). 1415 */ 1416 typedef union { 1417 struct { 1418 /** key5_data0 : RO; bitpos: [31:0]; default: 0; 1419 * Stores the zeroth 32 bits of KEY5. 1420 */ 1421 uint32_t key5_data0:32; 1422 }; 1423 uint32_t val; 1424 } efuse_rd_key5_data0_reg_t; 1425 1426 /** Type of rd_key5_data1 register 1427 * Register $n of BLOCK9 (KEY5). 1428 */ 1429 typedef union { 1430 struct { 1431 /** key5_data1 : RO; bitpos: [31:0]; default: 0; 1432 * Stores the first 32 bits of KEY5. 1433 */ 1434 uint32_t key5_data1:32; 1435 }; 1436 uint32_t val; 1437 } efuse_rd_key5_data1_reg_t; 1438 1439 /** Type of rd_key5_data2 register 1440 * Register $n of BLOCK9 (KEY5). 1441 */ 1442 typedef union { 1443 struct { 1444 /** key5_data2 : RO; bitpos: [31:0]; default: 0; 1445 * Stores the second 32 bits of KEY5. 1446 */ 1447 uint32_t key5_data2:32; 1448 }; 1449 uint32_t val; 1450 } efuse_rd_key5_data2_reg_t; 1451 1452 /** Type of rd_key5_data3 register 1453 * Register $n of BLOCK9 (KEY5). 1454 */ 1455 typedef union { 1456 struct { 1457 /** key5_data3 : RO; bitpos: [31:0]; default: 0; 1458 * Stores the third 32 bits of KEY5. 1459 */ 1460 uint32_t key5_data3:32; 1461 }; 1462 uint32_t val; 1463 } efuse_rd_key5_data3_reg_t; 1464 1465 /** Type of rd_key5_data4 register 1466 * Register $n of BLOCK9 (KEY5). 1467 */ 1468 typedef union { 1469 struct { 1470 /** key5_data4 : RO; bitpos: [31:0]; default: 0; 1471 * Stores the fourth 32 bits of KEY5. 1472 */ 1473 uint32_t key5_data4:32; 1474 }; 1475 uint32_t val; 1476 } efuse_rd_key5_data4_reg_t; 1477 1478 /** Type of rd_key5_data5 register 1479 * Register $n of BLOCK9 (KEY5). 1480 */ 1481 typedef union { 1482 struct { 1483 /** key5_data5 : RO; bitpos: [31:0]; default: 0; 1484 * Stores the fifth 32 bits of KEY5. 1485 */ 1486 uint32_t key5_data5:32; 1487 }; 1488 uint32_t val; 1489 } efuse_rd_key5_data5_reg_t; 1490 1491 /** Type of rd_key5_data6 register 1492 * Register $n of BLOCK9 (KEY5). 1493 */ 1494 typedef union { 1495 struct { 1496 /** key5_data6 : RO; bitpos: [31:0]; default: 0; 1497 * Stores the sixth 32 bits of KEY5. 1498 */ 1499 uint32_t key5_data6:32; 1500 }; 1501 uint32_t val; 1502 } efuse_rd_key5_data6_reg_t; 1503 1504 /** Type of rd_key5_data7 register 1505 * Register $n of BLOCK9 (KEY5). 1506 */ 1507 typedef union { 1508 struct { 1509 /** key5_data7 : RO; bitpos: [31:0]; default: 0; 1510 * Stores the seventh 32 bits of KEY5. 1511 */ 1512 uint32_t key5_data7:32; 1513 }; 1514 uint32_t val; 1515 } efuse_rd_key5_data7_reg_t; 1516 1517 /** Type of rd_sys_part2_data0 register 1518 * Register $n of BLOCK10 (system). 1519 */ 1520 typedef union { 1521 struct { 1522 /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0; 1523 * Stores the $nth 32 bits of the 2nd part of system data. 1524 */ 1525 uint32_t sys_data_part2_0:32; 1526 }; 1527 uint32_t val; 1528 } efuse_rd_sys_part2_data0_reg_t; 1529 1530 /** Type of rd_sys_part2_data1 register 1531 * Register $n of BLOCK9 (KEY5). 1532 */ 1533 typedef union { 1534 struct { 1535 /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0; 1536 * Stores the $nth 32 bits of the 2nd part of system data. 1537 */ 1538 uint32_t sys_data_part2_1:32; 1539 }; 1540 uint32_t val; 1541 } efuse_rd_sys_part2_data1_reg_t; 1542 1543 /** Type of rd_sys_part2_data2 register 1544 * Register $n of BLOCK10 (system). 1545 */ 1546 typedef union { 1547 struct { 1548 /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0; 1549 * Stores the $nth 32 bits of the 2nd part of system data. 1550 */ 1551 uint32_t sys_data_part2_2:32; 1552 }; 1553 uint32_t val; 1554 } efuse_rd_sys_part2_data2_reg_t; 1555 1556 /** Type of rd_sys_part2_data3 register 1557 * Register $n of BLOCK10 (system). 1558 */ 1559 typedef union { 1560 struct { 1561 /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0; 1562 * Stores the $nth 32 bits of the 2nd part of system data. 1563 */ 1564 uint32_t sys_data_part2_3:32; 1565 }; 1566 uint32_t val; 1567 } efuse_rd_sys_part2_data3_reg_t; 1568 1569 /** Type of rd_sys_part2_data4 register 1570 * Register $n of BLOCK10 (system). 1571 */ 1572 typedef union { 1573 struct { 1574 /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0; 1575 * Stores the $nth 32 bits of the 2nd part of system data. 1576 */ 1577 uint32_t sys_data_part2_4:32; 1578 }; 1579 uint32_t val; 1580 } efuse_rd_sys_part2_data4_reg_t; 1581 1582 /** Type of rd_sys_part2_data5 register 1583 * Register $n of BLOCK10 (system). 1584 */ 1585 typedef union { 1586 struct { 1587 /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0; 1588 * Stores the $nth 32 bits of the 2nd part of system data. 1589 */ 1590 uint32_t sys_data_part2_5:32; 1591 }; 1592 uint32_t val; 1593 } efuse_rd_sys_part2_data5_reg_t; 1594 1595 /** Type of rd_sys_part2_data6 register 1596 * Register $n of BLOCK10 (system). 1597 */ 1598 typedef union { 1599 struct { 1600 /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0; 1601 * Stores the $nth 32 bits of the 2nd part of system data. 1602 */ 1603 uint32_t sys_data_part2_6:32; 1604 }; 1605 uint32_t val; 1606 } efuse_rd_sys_part2_data6_reg_t; 1607 1608 /** Type of rd_sys_part2_data7 register 1609 * Register $n of BLOCK10 (system). 1610 */ 1611 typedef union { 1612 struct { 1613 /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0; 1614 * Stores the $nth 32 bits of the 2nd part of system data. 1615 */ 1616 uint32_t sys_data_part2_7:32; 1617 }; 1618 uint32_t val; 1619 } efuse_rd_sys_part2_data7_reg_t; 1620 1621 1622 /** Group: Report Register */ 1623 /** Type of rd_repeat_err0 register 1624 * Programming error record register 0 of BLOCK0. 1625 */ 1626 typedef union { 1627 struct { 1628 /** rd_dis_err : RO; bitpos: [6:0]; default: 0; 1629 * Indicates a programming error of RD_DIS. 1630 */ 1631 uint32_t rd_dis_err:7; 1632 /** swap_uart_sdio_en_err : RO; bitpos: [7]; default: 0; 1633 * Indicates a programming error of SWAP_UART_SDIO_EN. 1634 */ 1635 uint32_t swap_uart_sdio_en_err:1; 1636 /** dis_icache_err : RO; bitpos: [8]; default: 0; 1637 * Indicates a programming error of DIS_ICACHE. 1638 */ 1639 uint32_t dis_icache_err:1; 1640 /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0; 1641 * Indicates a programming error of DIS_USB_JTAG. 1642 */ 1643 uint32_t dis_usb_jtag_err:1; 1644 /** dis_download_icache_err : RO; bitpos: [10]; default: 0; 1645 * Indicates a programming error of DIS_DOWNLOAD_ICACHE. 1646 */ 1647 uint32_t dis_download_icache_err:1; 1648 /** dis_usb_serial_jtag_err : RO; bitpos: [11]; default: 0; 1649 * Indicates a programming error of DIS_USB_DEVICE. 1650 */ 1651 uint32_t dis_usb_serial_jtag_err:1; 1652 /** dis_force_download_err : RO; bitpos: [12]; default: 0; 1653 * Indicates a programming error of DIS_FORCE_DOWNLOAD. 1654 */ 1655 uint32_t dis_force_download_err:1; 1656 /** spi_download_mspi_dis_err : RO; bitpos: [13]; default: 0; 1657 * Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. 1658 */ 1659 uint32_t spi_download_mspi_dis_err:1; 1660 /** dis_twai_err : RO; bitpos: [14]; default: 0; 1661 * Indicates a programming error of DIS_CAN. 1662 */ 1663 uint32_t dis_twai_err:1; 1664 /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0; 1665 * Indicates a programming error of JTAG_SEL_ENABLE. 1666 */ 1667 uint32_t jtag_sel_enable_err:1; 1668 /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0; 1669 * Indicates a programming error of SOFT_DIS_JTAG. 1670 */ 1671 uint32_t soft_dis_jtag_err:3; 1672 /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0; 1673 * Indicates a programming error of DIS_PAD_JTAG. 1674 */ 1675 uint32_t dis_pad_jtag_err:1; 1676 /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0; 1677 * Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. 1678 */ 1679 uint32_t dis_download_manual_encrypt_err:1; 1680 /** usb_drefh_err : RO; bitpos: [22:21]; default: 0; 1681 * Indicates a programming error of USB_DREFH. 1682 */ 1683 uint32_t usb_drefh_err:2; 1684 /** usb_drefl_err : RO; bitpos: [24:23]; default: 0; 1685 * Indicates a programming error of USB_DREFL. 1686 */ 1687 uint32_t usb_drefl_err:2; 1688 /** usb_exchg_pins_err : RO; bitpos: [25]; default: 0; 1689 * Indicates a programming error of USB_EXCHG_PINS. 1690 */ 1691 uint32_t usb_exchg_pins_err:1; 1692 /** vdd_spi_as_gpio_err : RO; bitpos: [26]; default: 0; 1693 * Indicates a programming error of VDD_SPI_AS_GPIO. 1694 */ 1695 uint32_t vdd_spi_as_gpio_err:1; 1696 /** rpt4_reserved0_err_2 : RO; bitpos: [28:27]; default: 0; 1697 * Reserved. 1698 */ 1699 uint32_t rpt4_reserved0_err_2:2; 1700 /** rpt4_reserved0_err_1 : RO; bitpos: [29]; default: 0; 1701 * Reserved. 1702 */ 1703 uint32_t rpt4_reserved0_err_1:1; 1704 /** rpt4_reserved0_err_0 : RO; bitpos: [31:30]; default: 0; 1705 * Reserved. 1706 */ 1707 uint32_t rpt4_reserved0_err_0:2; 1708 }; 1709 uint32_t val; 1710 } efuse_rd_repeat_err0_reg_t; 1711 1712 /** Type of rd_repeat_err1 register 1713 * Programming error record register 1 of BLOCK0. 1714 */ 1715 typedef union { 1716 struct { 1717 /** rpt4_reserved1_err_0 : RO; bitpos: [15:0]; default: 0; 1718 * Reserved. 1719 */ 1720 uint32_t rpt4_reserved1_err_0:16; 1721 /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0; 1722 * Indicates a programming error of WDT_DELAY_SEL. 1723 */ 1724 uint32_t wdt_delay_sel_err:2; 1725 /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0; 1726 * Indicates a programming error of SPI_BOOT_CRYPT_CNT. 1727 */ 1728 uint32_t spi_boot_crypt_cnt_err:3; 1729 /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0; 1730 * Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. 1731 */ 1732 uint32_t secure_boot_key_revoke0_err:1; 1733 /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0; 1734 * Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. 1735 */ 1736 uint32_t secure_boot_key_revoke1_err:1; 1737 /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0; 1738 * Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. 1739 */ 1740 uint32_t secure_boot_key_revoke2_err:1; 1741 /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0; 1742 * Indicates a programming error of KEY_PURPOSE_0. 1743 */ 1744 uint32_t key_purpose_0_err:4; 1745 /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0; 1746 * Indicates a programming error of KEY_PURPOSE_1. 1747 */ 1748 uint32_t key_purpose_1_err:4; 1749 }; 1750 uint32_t val; 1751 } efuse_rd_repeat_err1_reg_t; 1752 1753 /** Type of rd_repeat_err2 register 1754 * Programming error record register 2 of BLOCK0. 1755 */ 1756 typedef union { 1757 struct { 1758 /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0; 1759 * Indicates a programming error of KEY_PURPOSE_2. 1760 */ 1761 uint32_t key_purpose_2_err:4; 1762 /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0; 1763 * Indicates a programming error of KEY_PURPOSE_3. 1764 */ 1765 uint32_t key_purpose_3_err:4; 1766 /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0; 1767 * Indicates a programming error of KEY_PURPOSE_4. 1768 */ 1769 uint32_t key_purpose_4_err:4; 1770 /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0; 1771 * Indicates a programming error of KEY_PURPOSE_5. 1772 */ 1773 uint32_t key_purpose_5_err:4; 1774 /** sec_dpa_level_err : RO; bitpos: [17:16]; default: 0; 1775 * Indicates a programming error of SEC_DPA_LEVEL. 1776 */ 1777 uint32_t sec_dpa_level_err:2; 1778 /** rpt4_reserved2_err_1 : RO; bitpos: [18]; default: 0; 1779 * Reserved. 1780 */ 1781 uint32_t rpt4_reserved2_err_1:1; 1782 /** crypt_dpa_enable_err : RO; bitpos: [19]; default: 0; 1783 * Indicates a programming error of CRYPT_DPA_ENABLE. 1784 */ 1785 uint32_t crypt_dpa_enable_err:1; 1786 /** secure_boot_en_err : RO; bitpos: [20]; default: 0; 1787 * Indicates a programming error of SECURE_BOOT_EN. 1788 */ 1789 uint32_t secure_boot_en_err:1; 1790 /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0; 1791 * Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. 1792 */ 1793 uint32_t secure_boot_aggressive_revoke_err:1; 1794 /** rpt4_reserved2_err_0 : RO; bitpos: [27:22]; default: 0; 1795 * Reserved. 1796 */ 1797 uint32_t rpt4_reserved2_err_0:6; 1798 /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0; 1799 * Indicates a programming error of FLASH_TPUW. 1800 */ 1801 uint32_t flash_tpuw_err:4; 1802 }; 1803 uint32_t val; 1804 } efuse_rd_repeat_err2_reg_t; 1805 1806 /** Type of rd_repeat_err3 register 1807 * Programming error record register 3 of BLOCK0. 1808 */ 1809 typedef union { 1810 struct { 1811 /** dis_download_mode_err : RO; bitpos: [0]; default: 0; 1812 * Indicates a programming error of DIS_DOWNLOAD_MODE. 1813 */ 1814 uint32_t dis_download_mode_err:1; 1815 /** dis_direct_boot_err : RO; bitpos: [1]; default: 0; 1816 * Indicates a programming error of DIS_DIRECT_BOOT. 1817 */ 1818 uint32_t dis_direct_boot_err:1; 1819 /** usb_print_err : RO; bitpos: [2]; default: 0; 1820 * Indicates a programming error of UART_PRINT_CHANNEL. 1821 */ 1822 uint32_t usb_print_err:1; 1823 /** rpt4_reserved3_err_5 : RO; bitpos: [3]; default: 0; 1824 * Reserved. 1825 */ 1826 uint32_t rpt4_reserved3_err_5:1; 1827 /** dis_usb_serial_jtag_download_mode_err : RO; bitpos: [4]; default: 0; 1828 * Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. 1829 */ 1830 uint32_t dis_usb_serial_jtag_download_mode_err:1; 1831 /** enable_security_download_err : RO; bitpos: [5]; default: 0; 1832 * Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. 1833 */ 1834 uint32_t enable_security_download_err:1; 1835 /** uart_print_control_err : RO; bitpos: [7:6]; default: 0; 1836 * Indicates a programming error of UART_PRINT_CONTROL. 1837 */ 1838 uint32_t uart_print_control_err:2; 1839 /** rpt4_reserved3_err_4 : RO; bitpos: [8]; default: 0; 1840 * Reserved. 1841 */ 1842 uint32_t rpt4_reserved3_err_4:1; 1843 /** rpt4_reserved3_err_3 : RO; bitpos: [9]; default: 0; 1844 * Reserved. 1845 */ 1846 uint32_t rpt4_reserved3_err_3:1; 1847 /** rpt4_reserved3_err_2 : RO; bitpos: [11:10]; default: 0; 1848 * Reserved. 1849 */ 1850 uint32_t rpt4_reserved3_err_2:2; 1851 /** rpt4_reserved3_err_1 : RO; bitpos: [12]; default: 0; 1852 * Reserved. 1853 */ 1854 uint32_t rpt4_reserved3_err_1:1; 1855 /** force_send_resume_err : RO; bitpos: [13]; default: 0; 1856 * Indicates a programming error of FORCE_SEND_RESUME. 1857 */ 1858 uint32_t force_send_resume_err:1; 1859 /** secure_version_err : RO; bitpos: [29:14]; default: 0; 1860 * Indicates a programming error of SECURE_VERSION. 1861 */ 1862 uint32_t secure_version_err:16; 1863 /** rpt4_reserved3_err_0 : RO; bitpos: [31:30]; default: 0; 1864 * Reserved. 1865 */ 1866 uint32_t rpt4_reserved3_err_0:2; 1867 }; 1868 uint32_t val; 1869 } efuse_rd_repeat_err3_reg_t; 1870 1871 /** Type of rd_repeat_err4 register 1872 * Programming error record register 4 of BLOCK0. 1873 */ 1874 typedef union { 1875 struct { 1876 /** rpt4_reserved4_err_1 : RO; bitpos: [23:0]; default: 0; 1877 * Reserved. 1878 */ 1879 uint32_t rpt4_reserved4_err_1:24; 1880 /** rpt4_reserved4_err_0 : RO; bitpos: [31:24]; default: 0; 1881 * Reserved. 1882 */ 1883 uint32_t rpt4_reserved4_err_0:8; 1884 }; 1885 uint32_t val; 1886 } efuse_rd_repeat_err4_reg_t; 1887 1888 /** Type of rd_rs_err0 register 1889 * Programming error record register 0 of BLOCK1-10. 1890 */ 1891 typedef union { 1892 struct { 1893 /** mac_spi_8m_err_num : RO; bitpos: [2:0]; default: 0; 1894 * The value of this signal means the number of error bytes. 1895 */ 1896 uint32_t mac_spi_8m_err_num:3; 1897 /** mac_spi_8m_fail : RO; bitpos: [3]; default: 0; 1898 * 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that 1899 * programming user data failed and the number of error bytes is over 6. 1900 */ 1901 uint32_t mac_spi_8m_fail:1; 1902 /** sys_part1_num : RO; bitpos: [6:4]; default: 0; 1903 * The value of this signal means the number of error bytes. 1904 */ 1905 uint32_t sys_part1_num:3; 1906 /** sys_part1_fail : RO; bitpos: [7]; default: 0; 1907 * 0: Means no failure and that the data of system part1 is reliable 1: Means that 1908 * programming user data failed and the number of error bytes is over 6. 1909 */ 1910 uint32_t sys_part1_fail:1; 1911 /** usr_data_err_num : RO; bitpos: [10:8]; default: 0; 1912 * The value of this signal means the number of error bytes. 1913 */ 1914 uint32_t usr_data_err_num:3; 1915 /** usr_data_fail : RO; bitpos: [11]; default: 0; 1916 * 0: Means no failure and that the user data is reliable 1: Means that programming 1917 * user data failed and the number of error bytes is over 6. 1918 */ 1919 uint32_t usr_data_fail:1; 1920 /** key0_err_num : RO; bitpos: [14:12]; default: 0; 1921 * The value of this signal means the number of error bytes. 1922 */ 1923 uint32_t key0_err_num:3; 1924 /** key0_fail : RO; bitpos: [15]; default: 0; 1925 * 0: Means no failure and that the data of key0 is reliable 1: Means that programming 1926 * key0 failed and the number of error bytes is over 6. 1927 */ 1928 uint32_t key0_fail:1; 1929 /** key1_err_num : RO; bitpos: [18:16]; default: 0; 1930 * The value of this signal means the number of error bytes. 1931 */ 1932 uint32_t key1_err_num:3; 1933 /** key1_fail : RO; bitpos: [19]; default: 0; 1934 * 0: Means no failure and that the data of key1 is reliable 1: Means that programming 1935 * key1 failed and the number of error bytes is over 6. 1936 */ 1937 uint32_t key1_fail:1; 1938 /** key2_err_num : RO; bitpos: [22:20]; default: 0; 1939 * The value of this signal means the number of error bytes. 1940 */ 1941 uint32_t key2_err_num:3; 1942 /** key2_fail : RO; bitpos: [23]; default: 0; 1943 * 0: Means no failure and that the data of key2 is reliable 1: Means that programming 1944 * key2 failed and the number of error bytes is over 6. 1945 */ 1946 uint32_t key2_fail:1; 1947 /** key3_err_num : RO; bitpos: [26:24]; default: 0; 1948 * The value of this signal means the number of error bytes. 1949 */ 1950 uint32_t key3_err_num:3; 1951 /** key3_fail : RO; bitpos: [27]; default: 0; 1952 * 0: Means no failure and that the data of key3 is reliable 1: Means that programming 1953 * key3 failed and the number of error bytes is over 6. 1954 */ 1955 uint32_t key3_fail:1; 1956 /** key4_err_num : RO; bitpos: [30:28]; default: 0; 1957 * The value of this signal means the number of error bytes. 1958 */ 1959 uint32_t key4_err_num:3; 1960 /** key4_fail : RO; bitpos: [31]; default: 0; 1961 * 0: Means no failure and that the data of key4 is reliable 1: Means that programming 1962 * key4 failed and the number of error bytes is over 6. 1963 */ 1964 uint32_t key4_fail:1; 1965 }; 1966 uint32_t val; 1967 } efuse_rd_rs_err0_reg_t; 1968 1969 /** Type of rd_rs_err1 register 1970 * Programming error record register 1 of BLOCK1-10. 1971 */ 1972 typedef union { 1973 struct { 1974 /** key5_err_num : RO; bitpos: [2:0]; default: 0; 1975 * The value of this signal means the number of error bytes. 1976 */ 1977 uint32_t key5_err_num:3; 1978 /** key5_fail : RO; bitpos: [3]; default: 0; 1979 * 0: Means no failure and that the data of key5 is reliable 1: Means that programming 1980 * key5 failed and the number of error bytes is over 6. 1981 */ 1982 uint32_t key5_fail:1; 1983 /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0; 1984 * The value of this signal means the number of error bytes. 1985 */ 1986 uint32_t sys_part2_err_num:3; 1987 /** sys_part2_fail : RO; bitpos: [7]; default: 0; 1988 * 0: Means no failure and that the data of system part2 is reliable 1: Means that 1989 * programming user data failed and the number of error bytes is over 6. 1990 */ 1991 uint32_t sys_part2_fail:1; 1992 uint32_t reserved_8:24; 1993 }; 1994 uint32_t val; 1995 } efuse_rd_rs_err1_reg_t; 1996 1997 1998 /** Group: Configuration Register */ 1999 /** Type of clk register 2000 * eFuse clcok configuration register. 2001 */ 2002 typedef union { 2003 struct { 2004 /** mem_force_pd : R/W; bitpos: [0]; default: 0; 2005 * Set this bit to force eFuse SRAM into power-saving mode. 2006 */ 2007 uint32_t mem_force_pd:1; 2008 /** mem_clk_force_on : R/W; bitpos: [1]; default: 1; 2009 * Set this bit and force to activate clock signal of eFuse SRAM. 2010 */ 2011 uint32_t mem_clk_force_on:1; 2012 /** mem_force_pu : R/W; bitpos: [2]; default: 0; 2013 * Set this bit to force eFuse SRAM into working mode. 2014 */ 2015 uint32_t mem_force_pu:1; 2016 uint32_t reserved_3:13; 2017 /** clk_en : R/W; bitpos: [16]; default: 0; 2018 * Set this bit to force enable eFuse register configuration clock signal. 2019 */ 2020 uint32_t clk_en:1; 2021 uint32_t reserved_17:15; 2022 }; 2023 uint32_t val; 2024 } efuse_clk_reg_t; 2025 2026 /** Type of conf register 2027 * eFuse operation mode configuraiton register 2028 */ 2029 typedef union { 2030 struct { 2031 /** op_code : R/W; bitpos: [15:0]; default: 0; 2032 * 0x5A5A: programming operation command 0x5AA5: read operation command. 2033 */ 2034 uint32_t op_code:16; 2035 uint32_t reserved_16:16; 2036 }; 2037 uint32_t val; 2038 } efuse_conf_reg_t; 2039 2040 /** Type of cmd register 2041 * eFuse command register. 2042 */ 2043 typedef union { 2044 struct { 2045 /** read_cmd : R/W/SC; bitpos: [0]; default: 0; 2046 * Set this bit to send read command. 2047 */ 2048 uint32_t read_cmd:1; 2049 /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0; 2050 * Set this bit to send programming command. 2051 */ 2052 uint32_t pgm_cmd:1; 2053 /** blk_num : R/W; bitpos: [5:2]; default: 0; 2054 * The serial number of the block to be programmed. Value 0-10 corresponds to block 2055 * number 0-10, respectively. 2056 */ 2057 uint32_t blk_num:4; 2058 uint32_t reserved_6:26; 2059 }; 2060 uint32_t val; 2061 } efuse_cmd_reg_t; 2062 2063 /** Type of dac_conf register 2064 * Controls the eFuse programming voltage. 2065 */ 2066 typedef union { 2067 struct { 2068 /** dac_clk_div : R/W; bitpos: [7:0]; default: 28; 2069 * Controls the division factor of the rising clock of the programming voltage. 2070 */ 2071 uint32_t dac_clk_div:8; 2072 /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0; 2073 * Don't care. 2074 */ 2075 uint32_t dac_clk_pad_sel:1; 2076 /** dac_num : R/W; bitpos: [16:9]; default: 255; 2077 * Controls the rising period of the programming voltage. 2078 */ 2079 uint32_t dac_num:8; 2080 /** oe_clr : R/W; bitpos: [17]; default: 0; 2081 * Reduces the power supply of the programming voltage. 2082 */ 2083 uint32_t oe_clr:1; 2084 uint32_t reserved_18:14; 2085 }; 2086 uint32_t val; 2087 } efuse_dac_conf_reg_t; 2088 2089 /** Type of rd_tim_conf register 2090 * Configures read timing parameters. 2091 */ 2092 typedef union { 2093 struct { 2094 /** thr_a : R/W; bitpos: [7:0]; default: 1; 2095 * Configures the read hold time. 2096 */ 2097 uint32_t thr_a:8; 2098 /** trd : R/W; bitpos: [15:8]; default: 2; 2099 * Configures the read time. 2100 */ 2101 uint32_t trd:8; 2102 /** tsur_a : R/W; bitpos: [23:16]; default: 1; 2103 * Configures the read setup time. 2104 */ 2105 uint32_t tsur_a:8; 2106 /** read_init_num : R/W; bitpos: [31:24]; default: 18; 2107 * Configures the waiting time of reading eFuse memory. 2108 */ 2109 uint32_t read_init_num:8; 2110 }; 2111 uint32_t val; 2112 } efuse_rd_tim_conf_reg_t; 2113 2114 /** Type of wr_tim_conf1 register 2115 * Configurarion register 1 of eFuse programming timing parameters. 2116 */ 2117 typedef union { 2118 struct { 2119 /** tsup_a : R/W; bitpos: [7:0]; default: 1; 2120 * Configures the programming setup time. 2121 */ 2122 uint32_t tsup_a:8; 2123 /** pwr_on_num : R/W; bitpos: [23:8]; default: 12288; 2124 * Configures the power up time for VDDQ. 2125 */ 2126 uint32_t pwr_on_num:16; 2127 /** thp_a : R/W; bitpos: [31:24]; default: 1; 2128 * Configures the programming hold time. 2129 */ 2130 uint32_t thp_a:8; 2131 }; 2132 uint32_t val; 2133 } efuse_wr_tim_conf1_reg_t; 2134 2135 /** Type of wr_tim_conf2 register 2136 * Configurarion register 2 of eFuse programming timing parameters. 2137 */ 2138 typedef union { 2139 struct { 2140 /** pwr_off_num : R/W; bitpos: [15:0]; default: 400; 2141 * Configures the power outage time for VDDQ. 2142 */ 2143 uint32_t pwr_off_num:16; 2144 /** tpgm : R/W; bitpos: [31:16]; default: 200; 2145 * Configures the active programming time. 2146 */ 2147 uint32_t tpgm:16; 2148 }; 2149 uint32_t val; 2150 } efuse_wr_tim_conf2_reg_t; 2151 2152 /** Type of wr_tim_conf0_rs_bypass register 2153 * Configurarion register0 of eFuse programming time parameters and rs bypass 2154 * operation. 2155 */ 2156 typedef union { 2157 struct { 2158 /** bypass_rs_correction : R/W; bitpos: [0]; default: 0; 2159 * Set this bit to bypass reed solomon correction step. 2160 */ 2161 uint32_t bypass_rs_correction:1; 2162 /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0; 2163 * Configures block number of programming twice operation. 2164 */ 2165 uint32_t bypass_rs_blk_num:11; 2166 /** update : WT; bitpos: [12]; default: 0; 2167 * Set this bit to update multi-bit register signals. 2168 */ 2169 uint32_t update:1; 2170 /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1; 2171 * Configures the inactive programming time. 2172 */ 2173 uint32_t tpgm_inactive:8; 2174 uint32_t reserved_21:11; 2175 }; 2176 uint32_t val; 2177 } efuse_wr_tim_conf0_rs_bypass_reg_t; 2178 2179 2180 /** Group: Status Register */ 2181 /** Type of status register 2182 * eFuse status register. 2183 */ 2184 typedef union { 2185 struct { 2186 /** state : RO; bitpos: [3:0]; default: 0; 2187 * Indicates the state of the eFuse state machine. 2188 */ 2189 uint32_t state:4; 2190 /** otp_load_sw : RO; bitpos: [4]; default: 0; 2191 * The value of OTP_LOAD_SW. 2192 */ 2193 uint32_t otp_load_sw:1; 2194 /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0; 2195 * The value of OTP_VDDQ_C_SYNC2. 2196 */ 2197 uint32_t otp_vddq_c_sync2:1; 2198 /** otp_strobe_sw : RO; bitpos: [6]; default: 0; 2199 * The value of OTP_STROBE_SW. 2200 */ 2201 uint32_t otp_strobe_sw:1; 2202 /** otp_csb_sw : RO; bitpos: [7]; default: 0; 2203 * The value of OTP_CSB_SW. 2204 */ 2205 uint32_t otp_csb_sw:1; 2206 /** otp_pgenb_sw : RO; bitpos: [8]; default: 0; 2207 * The value of OTP_PGENB_SW. 2208 */ 2209 uint32_t otp_pgenb_sw:1; 2210 /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0; 2211 * The value of OTP_VDDQ_IS_SW. 2212 */ 2213 uint32_t otp_vddq_is_sw:1; 2214 /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0; 2215 * Indicates the number of block valid bit. 2216 */ 2217 uint32_t blk0_valid_bit_cnt:10; 2218 uint32_t reserved_20:12; 2219 }; 2220 uint32_t val; 2221 } efuse_status_reg_t; 2222 2223 2224 /** Group: Interrupt Register */ 2225 /** Type of int_raw register 2226 * eFuse raw interrupt register. 2227 */ 2228 typedef union { 2229 struct { 2230 /** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0; 2231 * The raw bit signal for read_done interrupt. 2232 */ 2233 uint32_t read_done_int_raw:1; 2234 /** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0; 2235 * The raw bit signal for pgm_done interrupt. 2236 */ 2237 uint32_t pgm_done_int_raw:1; 2238 uint32_t reserved_2:30; 2239 }; 2240 uint32_t val; 2241 } efuse_int_raw_reg_t; 2242 2243 /** Type of int_st register 2244 * eFuse interrupt status register. 2245 */ 2246 typedef union { 2247 struct { 2248 /** read_done_int_st : RO; bitpos: [0]; default: 0; 2249 * The status signal for read_done interrupt. 2250 */ 2251 uint32_t read_done_int_st:1; 2252 /** pgm_done_int_st : RO; bitpos: [1]; default: 0; 2253 * The status signal for pgm_done interrupt. 2254 */ 2255 uint32_t pgm_done_int_st:1; 2256 uint32_t reserved_2:30; 2257 }; 2258 uint32_t val; 2259 } efuse_int_st_reg_t; 2260 2261 /** Type of int_ena register 2262 * eFuse interrupt enable register. 2263 */ 2264 typedef union { 2265 struct { 2266 /** read_done_int_ena : R/W; bitpos: [0]; default: 0; 2267 * The enable signal for read_done interrupt. 2268 */ 2269 uint32_t read_done_int_ena:1; 2270 /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0; 2271 * The enable signal for pgm_done interrupt. 2272 */ 2273 uint32_t pgm_done_int_ena:1; 2274 uint32_t reserved_2:30; 2275 }; 2276 uint32_t val; 2277 } efuse_int_ena_reg_t; 2278 2279 /** Type of int_clr register 2280 * eFuse interrupt clear register. 2281 */ 2282 typedef union { 2283 struct { 2284 /** read_done_int_clr : WO; bitpos: [0]; default: 0; 2285 * The clear signal for read_done interrupt. 2286 */ 2287 uint32_t read_done_int_clr:1; 2288 /** pgm_done_int_clr : WO; bitpos: [1]; default: 0; 2289 * The clear signal for pgm_done interrupt. 2290 */ 2291 uint32_t pgm_done_int_clr:1; 2292 uint32_t reserved_2:30; 2293 }; 2294 uint32_t val; 2295 } efuse_int_clr_reg_t; 2296 2297 2298 /** Group: Version Register */ 2299 /** Type of date register 2300 * eFuse version register. 2301 */ 2302 typedef union { 2303 struct { 2304 /** date : R/W; bitpos: [27:0]; default: 35676928; 2305 * Stores eFuse version. 2306 */ 2307 uint32_t date:28; 2308 uint32_t reserved_28:4; 2309 }; 2310 uint32_t val; 2311 } efuse_date_reg_t; 2312 2313 2314 typedef struct { 2315 volatile efuse_pgm_data0_reg_t pgm_data0; 2316 volatile efuse_pgm_data1_reg_t pgm_data1; 2317 volatile efuse_pgm_data2_reg_t pgm_data2; 2318 volatile efuse_pgm_data3_reg_t pgm_data3; 2319 volatile efuse_pgm_data4_reg_t pgm_data4; 2320 volatile efuse_pgm_data5_reg_t pgm_data5; 2321 volatile efuse_pgm_data6_reg_t pgm_data6; 2322 volatile efuse_pgm_data7_reg_t pgm_data7; 2323 volatile efuse_pgm_check_value0_reg_t pgm_check_value0; 2324 volatile efuse_pgm_check_value1_reg_t pgm_check_value1; 2325 volatile efuse_pgm_check_value2_reg_t pgm_check_value2; 2326 volatile efuse_rd_wr_dis_reg_t rd_wr_dis; 2327 volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0; 2328 volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1; 2329 volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2; 2330 volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3; 2331 volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4; 2332 volatile efuse_rd_mac_spi_sys_0_reg_t rd_mac_spi_sys_0; 2333 volatile efuse_rd_mac_spi_sys_1_reg_t rd_mac_spi_sys_1; 2334 volatile efuse_rd_mac_spi_sys_2_reg_t rd_mac_spi_sys_2; 2335 volatile efuse_rd_mac_spi_sys_3_reg_t rd_mac_spi_sys_3; 2336 volatile efuse_rd_mac_spi_sys_4_reg_t rd_mac_spi_sys_4; 2337 volatile efuse_rd_mac_spi_sys_5_reg_t rd_mac_spi_sys_5; 2338 volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0; 2339 volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1; 2340 volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2; 2341 volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3; 2342 volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4; 2343 volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5; 2344 volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6; 2345 volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7; 2346 volatile efuse_rd_usr_data0_reg_t rd_usr_data0; 2347 volatile efuse_rd_usr_data1_reg_t rd_usr_data1; 2348 volatile efuse_rd_usr_data2_reg_t rd_usr_data2; 2349 volatile efuse_rd_usr_data3_reg_t rd_usr_data3; 2350 volatile efuse_rd_usr_data4_reg_t rd_usr_data4; 2351 volatile efuse_rd_usr_data5_reg_t rd_usr_data5; 2352 volatile efuse_rd_usr_data6_reg_t rd_usr_data6; 2353 volatile efuse_rd_usr_data7_reg_t rd_usr_data7; 2354 volatile efuse_rd_key0_data0_reg_t rd_key0_data0; 2355 volatile efuse_rd_key0_data1_reg_t rd_key0_data1; 2356 volatile efuse_rd_key0_data2_reg_t rd_key0_data2; 2357 volatile efuse_rd_key0_data3_reg_t rd_key0_data3; 2358 volatile efuse_rd_key0_data4_reg_t rd_key0_data4; 2359 volatile efuse_rd_key0_data5_reg_t rd_key0_data5; 2360 volatile efuse_rd_key0_data6_reg_t rd_key0_data6; 2361 volatile efuse_rd_key0_data7_reg_t rd_key0_data7; 2362 volatile efuse_rd_key1_data0_reg_t rd_key1_data0; 2363 volatile efuse_rd_key1_data1_reg_t rd_key1_data1; 2364 volatile efuse_rd_key1_data2_reg_t rd_key1_data2; 2365 volatile efuse_rd_key1_data3_reg_t rd_key1_data3; 2366 volatile efuse_rd_key1_data4_reg_t rd_key1_data4; 2367 volatile efuse_rd_key1_data5_reg_t rd_key1_data5; 2368 volatile efuse_rd_key1_data6_reg_t rd_key1_data6; 2369 volatile efuse_rd_key1_data7_reg_t rd_key1_data7; 2370 volatile efuse_rd_key2_data0_reg_t rd_key2_data0; 2371 volatile efuse_rd_key2_data1_reg_t rd_key2_data1; 2372 volatile efuse_rd_key2_data2_reg_t rd_key2_data2; 2373 volatile efuse_rd_key2_data3_reg_t rd_key2_data3; 2374 volatile efuse_rd_key2_data4_reg_t rd_key2_data4; 2375 volatile efuse_rd_key2_data5_reg_t rd_key2_data5; 2376 volatile efuse_rd_key2_data6_reg_t rd_key2_data6; 2377 volatile efuse_rd_key2_data7_reg_t rd_key2_data7; 2378 volatile efuse_rd_key3_data0_reg_t rd_key3_data0; 2379 volatile efuse_rd_key3_data1_reg_t rd_key3_data1; 2380 volatile efuse_rd_key3_data2_reg_t rd_key3_data2; 2381 volatile efuse_rd_key3_data3_reg_t rd_key3_data3; 2382 volatile efuse_rd_key3_data4_reg_t rd_key3_data4; 2383 volatile efuse_rd_key3_data5_reg_t rd_key3_data5; 2384 volatile efuse_rd_key3_data6_reg_t rd_key3_data6; 2385 volatile efuse_rd_key3_data7_reg_t rd_key3_data7; 2386 volatile efuse_rd_key4_data0_reg_t rd_key4_data0; 2387 volatile efuse_rd_key4_data1_reg_t rd_key4_data1; 2388 volatile efuse_rd_key4_data2_reg_t rd_key4_data2; 2389 volatile efuse_rd_key4_data3_reg_t rd_key4_data3; 2390 volatile efuse_rd_key4_data4_reg_t rd_key4_data4; 2391 volatile efuse_rd_key4_data5_reg_t rd_key4_data5; 2392 volatile efuse_rd_key4_data6_reg_t rd_key4_data6; 2393 volatile efuse_rd_key4_data7_reg_t rd_key4_data7; 2394 volatile efuse_rd_key5_data0_reg_t rd_key5_data0; 2395 volatile efuse_rd_key5_data1_reg_t rd_key5_data1; 2396 volatile efuse_rd_key5_data2_reg_t rd_key5_data2; 2397 volatile efuse_rd_key5_data3_reg_t rd_key5_data3; 2398 volatile efuse_rd_key5_data4_reg_t rd_key5_data4; 2399 volatile efuse_rd_key5_data5_reg_t rd_key5_data5; 2400 volatile efuse_rd_key5_data6_reg_t rd_key5_data6; 2401 volatile efuse_rd_key5_data7_reg_t rd_key5_data7; 2402 volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0; 2403 volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1; 2404 volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2; 2405 volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3; 2406 volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4; 2407 volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5; 2408 volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6; 2409 volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7; 2410 volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0; 2411 volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1; 2412 volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2; 2413 volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3; 2414 uint32_t reserved_18c; 2415 volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4; 2416 uint32_t reserved_194[11]; 2417 volatile efuse_rd_rs_err0_reg_t rd_rs_err0; 2418 volatile efuse_rd_rs_err1_reg_t rd_rs_err1; 2419 volatile efuse_clk_reg_t clk; 2420 volatile efuse_conf_reg_t conf; 2421 volatile efuse_status_reg_t status; 2422 volatile efuse_cmd_reg_t cmd; 2423 volatile efuse_int_raw_reg_t int_raw; 2424 volatile efuse_int_st_reg_t int_st; 2425 volatile efuse_int_ena_reg_t int_ena; 2426 volatile efuse_int_clr_reg_t int_clr; 2427 volatile efuse_dac_conf_reg_t dac_conf; 2428 volatile efuse_rd_tim_conf_reg_t rd_tim_conf; 2429 volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1; 2430 volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2; 2431 volatile efuse_wr_tim_conf0_rs_bypass_reg_t wr_tim_conf0_rs_bypass; 2432 volatile efuse_date_reg_t date; 2433 } efuse_dev_t; 2434 2435 extern efuse_dev_t EFUSE; 2436 2437 #ifndef __cplusplus 2438 _Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure"); 2439 #endif 2440 2441 #ifdef __cplusplus 2442 } 2443 #endif 2444