1 /** 2 * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #ifdef __cplusplus 10 extern "C" { 11 #endif 12 13 /** Group: PGM Data Register */ 14 /** Type of pgm_data0 register 15 * Register 0 that stores data to be programmed. 16 */ 17 typedef union { 18 struct { 19 /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; 20 * Configures the 0th 32-bit data to be programmed. 21 */ 22 uint32_t pgm_data_0:32; 23 }; 24 uint32_t val; 25 } efuse_pgm_data0_reg_t; 26 27 /** Type of pgm_data1 register 28 * Register 1 that stores data to be programmed. 29 */ 30 typedef union { 31 struct { 32 /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0; 33 * Configures the 1st 32-bit data to be programmed. 34 */ 35 uint32_t pgm_data_1:32; 36 }; 37 uint32_t val; 38 } efuse_pgm_data1_reg_t; 39 40 /** Type of pgm_data2 register 41 * Register 2 that stores data to be programmed. 42 */ 43 typedef union { 44 struct { 45 /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0; 46 * Configures the 2nd 32-bit data to be programmed. 47 */ 48 uint32_t pgm_data_2:32; 49 }; 50 uint32_t val; 51 } efuse_pgm_data2_reg_t; 52 53 /** Type of pgm_data3 register 54 * Register 3 that stores data to be programmed. 55 */ 56 typedef union { 57 struct { 58 /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0; 59 * Configures the 3rd 32-bit data to be programmed. 60 */ 61 uint32_t pgm_data_3:32; 62 }; 63 uint32_t val; 64 } efuse_pgm_data3_reg_t; 65 66 /** Type of pgm_data4 register 67 * Register 4 that stores data to be programmed. 68 */ 69 typedef union { 70 struct { 71 /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0; 72 * Configures the 4th 32-bit data to be programmed. 73 */ 74 uint32_t pgm_data_4:32; 75 }; 76 uint32_t val; 77 } efuse_pgm_data4_reg_t; 78 79 /** Type of pgm_data5 register 80 * Register 5 that stores data to be programmed. 81 */ 82 typedef union { 83 struct { 84 /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0; 85 * Configures the 5th 32-bit data to be programmed. 86 */ 87 uint32_t pgm_data_5:32; 88 }; 89 uint32_t val; 90 } efuse_pgm_data5_reg_t; 91 92 /** Type of pgm_data6 register 93 * Register 6 that stores data to be programmed. 94 */ 95 typedef union { 96 struct { 97 /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0; 98 * Configures the 6th 32-bit data to be programmed. 99 */ 100 uint32_t pgm_data_6:32; 101 }; 102 uint32_t val; 103 } efuse_pgm_data6_reg_t; 104 105 /** Type of pgm_data7 register 106 * Register 7 that stores data to be programmed. 107 */ 108 typedef union { 109 struct { 110 /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0; 111 * Configures the 7th 32-bit data to be programmed. 112 */ 113 uint32_t pgm_data_7:32; 114 }; 115 uint32_t val; 116 } efuse_pgm_data7_reg_t; 117 118 /** Type of pgm_check_value0 register 119 * Register 0 that stores the RS code to be programmed. 120 */ 121 typedef union { 122 struct { 123 /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0; 124 * Configures the 0th 32-bit RS code to be programmed. 125 */ 126 uint32_t pgm_rs_data_0:32; 127 }; 128 uint32_t val; 129 } efuse_pgm_check_value0_reg_t; 130 131 /** Type of pgm_check_value1 register 132 * Register 1 that stores the RS code to be programmed. 133 */ 134 typedef union { 135 struct { 136 /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0; 137 * Configures the 1st 32-bit RS code to be programmed. 138 */ 139 uint32_t pgm_rs_data_1:32; 140 }; 141 uint32_t val; 142 } efuse_pgm_check_value1_reg_t; 143 144 /** Type of pgm_check_value2 register 145 * Register 2 that stores the RS code to be programmed. 146 */ 147 typedef union { 148 struct { 149 /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0; 150 * Configures the 2nd 32-bit RS code to be programmed. 151 */ 152 uint32_t pgm_rs_data_2:32; 153 }; 154 uint32_t val; 155 } efuse_pgm_check_value2_reg_t; 156 157 158 /** Group: Read Data Register */ 159 /** Type of rd_wr_dis register 160 * BLOCK0 data register 0. 161 */ 162 typedef union { 163 struct { 164 /** wr_dis : RO; bitpos: [31:0]; default: 0; 165 * Represents whether programming of individual eFuse memory bit is disabled or 166 * enabled. 1: Disabled. 0 Enabled. 167 */ 168 uint32_t wr_dis:32; 169 }; 170 uint32_t val; 171 } efuse_rd_wr_dis_reg_t; 172 173 /** Type of rd_repeat_data0 register 174 * BLOCK0 data register 1. 175 */ 176 typedef union { 177 struct { 178 /** rd_dis : RO; bitpos: [6:0]; default: 0; 179 * Represents whether reading of individual eFuse block(block4~block10) is disabled or 180 * enabled. 1: disabled. 0: enabled. 181 */ 182 uint32_t rd_dis:7; 183 /** rpt4_reserved0_4 : RO; bitpos: [7]; default: 0; 184 * Reserved. 185 */ 186 uint32_t rpt4_reserved0_4:1; 187 /** dis_icache : RO; bitpos: [8]; default: 0; 188 * Represents whether icache is disabled or enabled. 1: disabled. 0: enabled. 189 */ 190 uint32_t dis_icache:1; 191 /** dis_usb_jtag : RO; bitpos: [9]; default: 0; 192 * Represents whether the function of usb switch to jtag is disabled or enabled. 1: 193 * disabled. 0: enabled. 194 */ 195 uint32_t dis_usb_jtag:1; 196 /** powerglitch_en : RO; bitpos: [10]; default: 0; 197 * Represents whether power glitch function is enabled. 1: enabled. 0: disabled. 198 */ 199 uint32_t powerglitch_en:1; 200 /** dis_usb_serial_jtag : RO; bitpos: [11]; default: 0; 201 * Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled. 202 */ 203 uint32_t dis_usb_serial_jtag:1; 204 /** dis_force_download : RO; bitpos: [12]; default: 0; 205 * Represents whether the function that forces chip into download mode is disabled or 206 * enabled. 1: disabled. 0: enabled. 207 */ 208 uint32_t dis_force_download:1; 209 /** spi_download_mspi_dis : RO; bitpos: [13]; default: 0; 210 * Represents whether SPI0 controller during boot_mode_download is disabled or 211 * enabled. 1: disabled. 0: enabled. 212 */ 213 uint32_t spi_download_mspi_dis:1; 214 /** dis_twai : RO; bitpos: [14]; default: 0; 215 * Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled. 216 */ 217 uint32_t dis_twai:1; 218 /** jtag_sel_enable : RO; bitpos: [15]; default: 0; 219 * Set this bit to enable selection between usb_to_jtag and pad_to_jtag through 220 * strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 221 */ 222 uint32_t jtag_sel_enable:1; 223 /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0; 224 * Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: 225 * enabled. 226 */ 227 uint32_t soft_dis_jtag:3; 228 /** dis_pad_jtag : RO; bitpos: [19]; default: 0; 229 * Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: 230 * enabled. 231 */ 232 uint32_t dis_pad_jtag:1; 233 /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0; 234 * Represents whether flash encrypt function is disabled or enabled(except in SPI boot 235 * mode). 1: disabled. 0: enabled. 236 */ 237 uint32_t dis_download_manual_encrypt:1; 238 /** usb_drefh : RO; bitpos: [22:21]; default: 0; 239 * Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV. 240 */ 241 uint32_t usb_drefh:2; 242 /** usb_drefl : RO; bitpos: [24:23]; default: 0; 243 * Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV. 244 */ 245 uint32_t usb_drefl:2; 246 /** usb_exchg_pins : RO; bitpos: [25]; default: 0; 247 * Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged. 248 */ 249 uint32_t usb_exchg_pins:1; 250 /** vdd_spi_as_gpio : RO; bitpos: [26]; default: 0; 251 * Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not 252 * functioned. 253 */ 254 uint32_t vdd_spi_as_gpio:1; 255 /** ecdsa_curve_mode : R; bitpos: [28:27]; default: 0; 256 * Configures the curve of ECDSA calculation: 0: only enable P256. 1: only enable 257 * P192. 2: both enable P256 and P192. 3: only enable P256 258 */ 259 uint32_t ecdsa_curve_mode:2; 260 /** ecc_force_const_time : R; bitpos: [29]; default: 0; 261 * Set this bit to permanently turn on ECC const-time mode 262 */ 263 uint32_t ecc_force_const_time:1; 264 /** xts_dpa_pseudo_level : R; bitpos: [31:30]; default: 0; 265 * Set this bit to control the xts pseudo-round anti-dpa attack function: 0: 266 * controlled by register. 1-3: the higher the value is, the more pseudo-rounds are 267 * inserted to the xts-aes calculation 268 */ 269 uint32_t xts_dpa_pseudo_level:2; 270 }; 271 uint32_t val; 272 } efuse_rd_repeat_data0_reg_t; 273 274 /** Type of rd_repeat_data1 register 275 * BLOCK0 data register 2. 276 */ 277 typedef union { 278 struct { 279 /** rpt4_reserved1_1 : RO; bitpos: [15:0]; default: 0; 280 * Reserved. 281 */ 282 uint32_t rpt4_reserved1_1:16; 283 /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0; 284 * Represents whether RTC watchdog timeout threshold is selected at startup. 1: 285 * selected. 0: not selected. 286 */ 287 uint32_t wdt_delay_sel:2; 288 /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0; 289 * Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of 290 * 1: enabled. Even number of 1: disabled. 291 */ 292 uint32_t spi_boot_crypt_cnt:3; 293 /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0; 294 * Represents whether revoking first secure boot key is enabled or disabled. 1: 295 * enabled. 0: disabled. 296 */ 297 uint32_t secure_boot_key_revoke0:1; 298 /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0; 299 * Represents whether revoking second secure boot key is enabled or disabled. 1: 300 * enabled. 0: disabled. 301 */ 302 uint32_t secure_boot_key_revoke1:1; 303 /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0; 304 * Represents whether revoking third secure boot key is enabled or disabled. 1: 305 * enabled. 0: disabled. 306 */ 307 uint32_t secure_boot_key_revoke2:1; 308 /** key_purpose_0 : RO; bitpos: [27:24]; default: 0; 309 * Represents the purpose of Key0. 310 */ 311 uint32_t key_purpose_0:4; 312 /** key_purpose_1 : RO; bitpos: [31:28]; default: 0; 313 * Represents the purpose of Key1. 314 */ 315 uint32_t key_purpose_1:4; 316 }; 317 uint32_t val; 318 } efuse_rd_repeat_data1_reg_t; 319 320 /** Type of rd_repeat_data2 register 321 * BLOCK0 data register 3. 322 */ 323 typedef union { 324 struct { 325 /** key_purpose_2 : RO; bitpos: [3:0]; default: 0; 326 * Represents the purpose of Key2. 327 */ 328 uint32_t key_purpose_2:4; 329 /** key_purpose_3 : RO; bitpos: [7:4]; default: 0; 330 * Represents the purpose of Key3. 331 */ 332 uint32_t key_purpose_3:4; 333 /** key_purpose_4 : RO; bitpos: [11:8]; default: 0; 334 * Represents the purpose of Key4. 335 */ 336 uint32_t key_purpose_4:4; 337 /** key_purpose_5 : RO; bitpos: [15:12]; default: 0; 338 * Represents the purpose of Key5. 339 */ 340 uint32_t key_purpose_5:4; 341 /** sec_dpa_level : RO; bitpos: [17:16]; default: 0; 342 * Represents the spa secure level by configuring the clock random divide mode. 343 */ 344 uint32_t sec_dpa_level:2; 345 /** reserve_0_114 : RO; bitpos: [18]; default: 1; 346 * Reserved 347 */ 348 uint32_t reserve_0_114:1; 349 /** crypt_dpa_enable : RO; bitpos: [19]; default: 1; 350 * Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled. 351 */ 352 uint32_t crypt_dpa_enable:1; 353 /** secure_boot_en : RO; bitpos: [20]; default: 0; 354 * Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled. 355 */ 356 uint32_t secure_boot_en:1; 357 /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0; 358 * Represents whether revoking aggressive secure boot is enabled or disabled. 1: 359 * enabled. 0: disabled. 360 */ 361 uint32_t secure_boot_aggressive_revoke:1; 362 /** powerglitch_en1 : R; bitpos: [26:22]; default: 0; 363 * Set these bits to enable power glitch function when chip power on 364 */ 365 uint32_t powerglitch_en1:5; 366 /** reserved_0_123 : R; bitpos: [27]; default: 0; 367 * reserved 368 */ 369 uint32_t reserved_0_123:1; 370 /** flash_tpuw : RO; bitpos: [31:28]; default: 0; 371 * Represents the flash waiting time after power-up, in unit of ms. When the value 372 * less than 15, the waiting time is the programmed value. Otherwise, the waiting time 373 * is 2 times the programmed value. 374 */ 375 uint32_t flash_tpuw:4; 376 }; 377 uint32_t val; 378 } efuse_rd_repeat_data2_reg_t; 379 380 /** Type of rd_repeat_data3 register 381 * BLOCK0 data register 4. 382 */ 383 typedef union { 384 struct { 385 /** dis_download_mode : RO; bitpos: [0]; default: 0; 386 * Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled. 387 */ 388 uint32_t dis_download_mode:1; 389 /** dis_direct_boot : RO; bitpos: [1]; default: 0; 390 * Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled. 391 */ 392 uint32_t dis_direct_boot:1; 393 /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0; 394 * Set this bit to disable USB-Serial-JTAG print during rom boot. 395 */ 396 uint32_t dis_usb_serial_jtag_rom_print:1; 397 /** rpt4_reserved3_5 : RO; bitpos: [3]; default: 0; 398 * Reserved. 399 */ 400 uint32_t rpt4_reserved3_5:1; 401 /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0; 402 * Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: 403 * disabled. 0: enabled. 404 */ 405 uint32_t dis_usb_serial_jtag_download_mode:1; 406 /** enable_security_download : RO; bitpos: [5]; default: 0; 407 * Represents whether security download is enabled or disabled. 1: enabled. 0: 408 * disabled. 409 */ 410 uint32_t enable_security_download:1; 411 /** uart_print_control : RO; bitpos: [7:6]; default: 0; 412 * Represents the type of UART printing. 00: force enable printing. 01: enable 413 * printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset 414 * at high level. 11: force disable printing. 415 */ 416 uint32_t uart_print_control:2; 417 /** force_send_resume : RO; bitpos: [8]; default: 0; 418 * Represents whether ROM code is forced to send a resume command during SPI boot. 1: 419 * forced. 0:not forced. 420 */ 421 uint32_t force_send_resume:1; 422 /** secure_version : RO; bitpos: [24:9]; default: 0; 423 * Represents the version used by ESP-IDF anti-rollback feature. 424 */ 425 uint32_t secure_version:16; 426 /** secure_boot_disable_fast_wake : RO; bitpos: [25]; default: 0; 427 * Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is 428 * enabled. 1: disabled. 0: enabled. 429 */ 430 uint32_t secure_boot_disable_fast_wake:1; 431 /** hys_en_pad0 : RO; bitpos: [31:26]; default: 0; 432 * Set bits to enable hysteresis function of PAD0~5 433 */ 434 uint32_t hys_en_pad0:6; 435 }; 436 uint32_t val; 437 } efuse_rd_repeat_data3_reg_t; 438 439 /** Type of rd_repeat_data4 register 440 * BLOCK0 data register 5. 441 */ 442 typedef union { 443 struct { 444 /** hys_en_pad1 : RO; bitpos: [21:0]; default: 0; 445 * Set bits to enable hysteresis function of PAD6~27 446 */ 447 uint32_t hys_en_pad1:22; 448 /** rpt4_reserved4_1 : RO; bitpos: [23:22]; default: 0; 449 * Reserved. 450 */ 451 uint32_t rpt4_reserved4_1:2; 452 /** rpt4_reserved4_0 : RO; bitpos: [31:24]; default: 0; 453 * Reserved. 454 */ 455 uint32_t rpt4_reserved4_0:8; 456 }; 457 uint32_t val; 458 } efuse_rd_repeat_data4_reg_t; 459 460 /** Type of rd_mac_sys_0 register 461 * BLOCK1 data register $n. 462 */ 463 typedef union { 464 struct { 465 /** mac_0 : RO; bitpos: [31:0]; default: 0; 466 * Stores the low 32 bits of MAC address. 467 */ 468 uint32_t mac_0:32; 469 }; 470 uint32_t val; 471 } efuse_rd_mac_sys_0_reg_t; 472 473 /** Type of rd_mac_sys_1 register 474 * BLOCK1 data register $n. 475 */ 476 typedef union { 477 struct { 478 /** mac_1 : RO; bitpos: [15:0]; default: 0; 479 * Stores the high 16 bits of MAC address. 480 */ 481 uint32_t mac_1:16; 482 /** mac_ext : RO; bitpos: [31:16]; default: 0; 483 * Stores the extended bits of MAC address. 484 */ 485 uint32_t mac_ext:16; 486 }; 487 uint32_t val; 488 } efuse_rd_mac_sys_1_reg_t; 489 490 /** Type of rd_mac_sys_2 register 491 * BLOCK1 data register $n. 492 */ 493 typedef union { 494 struct { 495 /** rxiq_version : RO; bitpos: [2:0]; default: 0; 496 * Stores RF Calibration data. RXIQ version. 497 */ 498 uint32_t rxiq_version:3; 499 /** rxiq_0 : RO; bitpos: [9:3]; default: 0; 500 * Stores RF Calibration data. RXIQ data 0. 501 */ 502 uint32_t rxiq_0:7; 503 /** rxiq_1 : RO; bitpos: [16:10]; default: 0; 504 * Stores RF Calibration data. RXIQ data 1. 505 */ 506 uint32_t rxiq_1:7; 507 /** active_hp_dbias : RO; bitpos: [21:17]; default: 0; 508 * Stores the PMU active hp dbias. 509 */ 510 uint32_t active_hp_dbias:5; 511 /** active_lp_dbias : RO; bitpos: [26:22]; default: 0; 512 * Stores the PMU active lp dbias. 513 */ 514 uint32_t active_lp_dbias:5; 515 /** dslp_dbias : RO; bitpos: [30:27]; default: 0; 516 * Stores the PMU sleep dbias. 517 */ 518 uint32_t dslp_dbias:4; 519 /** dbias_vol_gap_value1 : RO; bitpos: [31]; default: 0; 520 * Stores the low 1 bit of dbias_vol_gap. 521 */ 522 uint32_t dbias_vol_gap_value1:1; 523 }; 524 uint32_t val; 525 } efuse_rd_mac_sys_2_reg_t; 526 527 /** Type of rd_mac_sys_3 register 528 * BLOCK1 data register $n. 529 */ 530 typedef union { 531 struct { 532 /** dbias_vol_gap_value2 : RO; bitpos: [2:0]; default: 0; 533 * Stores the high 3 bits of dbias_vol_gap. 534 */ 535 uint32_t dbias_vol_gap_value2:3; 536 /** dbias_vol_gap_sign : RO; bitpos: [3]; default: 0; 537 * Stores the sign bit of dbias_vol_gap. 538 */ 539 uint32_t dbias_vol_gap_sign:1; 540 /** mac_reserved_2 : RO; bitpos: [17:4]; default: 0; 541 * Reserved. 542 */ 543 uint32_t mac_reserved_2:14; 544 /** wafer_version_minor : RO; bitpos: [20:18]; default: 0; 545 * Stores the wafer version minor. 546 */ 547 uint32_t wafer_version_minor:3; 548 /** wafer_version_major : RO; bitpos: [22:21]; default: 0; 549 * Stores the wafer version major. 550 */ 551 uint32_t wafer_version_major:2; 552 /** disable_wafer_version_major : RO; bitpos: [23]; default: 0; 553 * Disables check of wafer version major. 554 */ 555 uint32_t disable_wafer_version_major:1; 556 /** flash_cap : RO; bitpos: [26:24]; default: 0; 557 * Stores the flash cap. 558 */ 559 uint32_t flash_cap:3; 560 /** flash_temp : RO; bitpos: [28:27]; default: 0; 561 * Stores the flash temp. 562 */ 563 uint32_t flash_temp:2; 564 /** flash_vendor : RO; bitpos: [31:29]; default: 0; 565 * Stores the flash vendor. 566 */ 567 uint32_t flash_vendor:3; 568 }; 569 uint32_t val; 570 } efuse_rd_mac_sys_3_reg_t; 571 572 /** Type of rd_mac_sys_4 register 573 * BLOCK1 data register $n. 574 */ 575 typedef union { 576 struct { 577 /** pkg_version : R; bitpos: [2:0]; default: 0; 578 * Package version 579 */ 580 uint32_t pkg_version:3; 581 /** reserved_1_131 : R; bitpos: [31:3]; default: 0; 582 * reserved 583 */ 584 uint32_t reserved_1_131:29; 585 }; 586 uint32_t val; 587 } efuse_rd_mac_sys_4_reg_t; 588 589 /** Type of rd_mac_sys_5 register 590 * BLOCK1 data register $n. 591 */ 592 typedef union { 593 struct { 594 /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0; 595 * Stores the second 32 bits of the zeroth part of system data. 596 */ 597 uint32_t sys_data_part0_2:32; 598 }; 599 uint32_t val; 600 } efuse_rd_mac_sys_5_reg_t; 601 602 /** Type of rd_sys_part1_data0 register 603 * Register $n of BLOCK2 (system). 604 */ 605 typedef union { 606 struct { 607 /** optional_unique_id : R; bitpos: [31:0]; default: 0; 608 * Optional unique 128-bit ID 609 */ 610 uint32_t optional_unique_id:32; 611 }; 612 uint32_t val; 613 } efuse_rd_sys_part1_data0_reg_t; 614 615 /** Type of rd_sys_part1_data1 register 616 * Register $n of BLOCK2 (system). 617 */ 618 typedef union { 619 struct { 620 /** optional_unique_id_1 : R; bitpos: [31:0]; default: 0; 621 * Optional unique 128-bit ID 622 */ 623 uint32_t optional_unique_id_1:32; 624 }; 625 uint32_t val; 626 } efuse_rd_sys_part1_data1_reg_t; 627 628 /** Type of rd_sys_part1_data2 register 629 * Register $n of BLOCK2 (system). 630 */ 631 typedef union { 632 struct { 633 /** optional_unique_id_2 : R; bitpos: [31:0]; default: 0; 634 * Optional unique 128-bit ID 635 */ 636 uint32_t optional_unique_id_2:32; 637 }; 638 uint32_t val; 639 } efuse_rd_sys_part1_data2_reg_t; 640 641 /** Type of rd_sys_part1_data3 register 642 * Register $n of BLOCK2 (system). 643 */ 644 typedef union { 645 struct { 646 /** optional_unique_id_3 : R; bitpos: [31:0]; default: 0; 647 * Optional unique 128-bit ID 648 */ 649 uint32_t optional_unique_id_3:32; 650 }; 651 uint32_t val; 652 } efuse_rd_sys_part1_data3_reg_t; 653 654 /** Type of rd_sys_part1_data4 register 655 * Register $n of BLOCK2 (system). 656 */ 657 typedef union { 658 struct { 659 /** reserved_2_128 : R; bitpos: [1:0]; default: 0; 660 * reserved 661 */ 662 uint32_t reserved_2_128:2; 663 /** blk_version_minor : R; bitpos: [4:2]; default: 0; 664 * BLK_VERSION_MINOR of BLOCK2. 1: RF Calibration data in BLOCK1 665 */ 666 uint32_t blk_version_minor:3; 667 /** blk_version_major : R; bitpos: [6:5]; default: 0; 668 * BLK_VERSION_MAJOR of BLOCK2 669 */ 670 uint32_t blk_version_major:2; 671 /** disable_blk_version_major : R; bitpos: [7]; default: 0; 672 * Disables check of blk version major 673 */ 674 uint32_t disable_blk_version_major:1; 675 /** temp_calib : R; bitpos: [16:8]; default: 0; 676 * Temperature calibration data 677 */ 678 uint32_t temp_calib:9; 679 /** adc1_ave_initcode_atten0 : R; bitpos: [26:17]; default: 0; 680 * ADC1 calibration data 681 */ 682 uint32_t adc1_ave_initcode_atten0:10; 683 /** adc1_ave_initcode_atten1 : R; bitpos: [31:27]; default: 0; 684 * ADC1 calibration data 685 */ 686 uint32_t adc1_ave_initcode_atten1:5; 687 }; 688 uint32_t val; 689 } efuse_rd_sys_part1_data4_reg_t; 690 691 /** Type of rd_sys_part1_data5 register 692 * Register $n of BLOCK2 (system). 693 */ 694 typedef union { 695 struct { 696 /** adc1_ave_initcode_atten1_1 : R; bitpos: [4:0]; default: 0; 697 * ADC1 calibration data 698 */ 699 uint32_t adc1_ave_initcode_atten1_1:5; 700 /** adc1_ave_initcode_atten2 : R; bitpos: [14:5]; default: 0; 701 * ADC1 calibration data 702 */ 703 uint32_t adc1_ave_initcode_atten2:10; 704 /** adc1_ave_initcode_atten3 : R; bitpos: [24:15]; default: 0; 705 * ADC1 calibration data 706 */ 707 uint32_t adc1_ave_initcode_atten3:10; 708 /** adc1_hi_dout_atten0 : R; bitpos: [31:25]; default: 0; 709 * ADC1 calibration data 710 */ 711 uint32_t adc1_hi_dout_atten0:7; 712 }; 713 uint32_t val; 714 } efuse_rd_sys_part1_data5_reg_t; 715 716 /** Type of rd_sys_part1_data6 register 717 * Register $n of BLOCK2 (system). 718 */ 719 typedef union { 720 struct { 721 /** adc1_hi_dout_atten0_1 : R; bitpos: [2:0]; default: 0; 722 * ADC1 calibration data 723 */ 724 uint32_t adc1_hi_dout_atten0_1:3; 725 /** adc1_hi_dout_atten1 : R; bitpos: [12:3]; default: 0; 726 * ADC1 calibration data 727 */ 728 uint32_t adc1_hi_dout_atten1:10; 729 /** adc1_hi_dout_atten2 : R; bitpos: [22:13]; default: 0; 730 * ADC1 calibration data 731 */ 732 uint32_t adc1_hi_dout_atten2:10; 733 /** adc1_hi_dout_atten3 : R; bitpos: [31:23]; default: 0; 734 * ADC1 calibration data 735 */ 736 uint32_t adc1_hi_dout_atten3:9; 737 }; 738 uint32_t val; 739 } efuse_rd_sys_part1_data6_reg_t; 740 741 /** Type of rd_sys_part1_data7 register 742 * Register $n of BLOCK2 (system). 743 */ 744 typedef union { 745 struct { 746 /** adc1_hi_dout_atten3_1 : R; bitpos: [0]; default: 0; 747 * ADC1 calibration data 748 */ 749 uint32_t adc1_hi_dout_atten3_1:1; 750 /** adc1_ch0_atten0_initcode_diff : R; bitpos: [4:1]; default: 0; 751 * ADC1 calibration data 752 */ 753 uint32_t adc1_ch0_atten0_initcode_diff:4; 754 /** adc1_ch1_atten0_initcode_diff : R; bitpos: [8:5]; default: 0; 755 * ADC1 calibration data 756 */ 757 uint32_t adc1_ch1_atten0_initcode_diff:4; 758 /** adc1_ch2_atten0_initcode_diff : R; bitpos: [12:9]; default: 0; 759 * ADC1 calibration data 760 */ 761 uint32_t adc1_ch2_atten0_initcode_diff:4; 762 /** adc1_ch3_atten0_initcode_diff : R; bitpos: [16:13]; default: 0; 763 * ADC1 calibration data 764 */ 765 uint32_t adc1_ch3_atten0_initcode_diff:4; 766 /** adc1_ch4_atten0_initcode_diff : R; bitpos: [20:17]; default: 0; 767 * ADC1 calibration data 768 */ 769 uint32_t adc1_ch4_atten0_initcode_diff:4; 770 /** reserved_2_245 : R; bitpos: [31:21]; default: 0; 771 * reserved 772 */ 773 uint32_t reserved_2_245:11; 774 }; 775 uint32_t val; 776 } efuse_rd_sys_part1_data7_reg_t; 777 778 /** Type of rd_usr_data0 register 779 * Register $n of BLOCK3 (user). 780 */ 781 typedef union { 782 struct { 783 /** usr_data0 : RO; bitpos: [31:0]; default: 0; 784 * Stores the zeroth 32 bits of BLOCK3 (user). 785 */ 786 uint32_t usr_data0:32; 787 }; 788 uint32_t val; 789 } efuse_rd_usr_data0_reg_t; 790 791 /** Type of rd_usr_data1 register 792 * Register $n of BLOCK3 (user). 793 */ 794 typedef union { 795 struct { 796 /** usr_data1 : RO; bitpos: [31:0]; default: 0; 797 * Stores the first 32 bits of BLOCK3 (user). 798 */ 799 uint32_t usr_data1:32; 800 }; 801 uint32_t val; 802 } efuse_rd_usr_data1_reg_t; 803 804 /** Type of rd_usr_data2 register 805 * Register $n of BLOCK3 (user). 806 */ 807 typedef union { 808 struct { 809 /** usr_data2 : RO; bitpos: [31:0]; default: 0; 810 * Stores the second 32 bits of BLOCK3 (user). 811 */ 812 uint32_t usr_data2:32; 813 }; 814 uint32_t val; 815 } efuse_rd_usr_data2_reg_t; 816 817 /** Type of rd_usr_data3 register 818 * Register $n of BLOCK3 (user). 819 */ 820 typedef union { 821 struct { 822 /** usr_data3 : RO; bitpos: [31:0]; default: 0; 823 * Stores the third 32 bits of BLOCK3 (user). 824 */ 825 uint32_t usr_data3:32; 826 }; 827 uint32_t val; 828 } efuse_rd_usr_data3_reg_t; 829 830 /** Type of rd_usr_data4 register 831 * Register $n of BLOCK3 (user). 832 */ 833 typedef union { 834 struct { 835 /** usr_data4 : RO; bitpos: [31:0]; default: 0; 836 * Stores the fourth 32 bits of BLOCK3 (user). 837 */ 838 uint32_t usr_data4:32; 839 }; 840 uint32_t val; 841 } efuse_rd_usr_data4_reg_t; 842 843 /** Type of rd_usr_data5 register 844 * Register $n of BLOCK3 (user). 845 */ 846 typedef union { 847 struct { 848 /** usr_data5 : RO; bitpos: [31:0]; default: 0; 849 * Stores the fifth 32 bits of BLOCK3 (user). 850 */ 851 uint32_t usr_data5:32; 852 }; 853 uint32_t val; 854 } efuse_rd_usr_data5_reg_t; 855 856 /** Type of rd_usr_data6 register 857 * Register $n of BLOCK3 (user). 858 */ 859 typedef union { 860 struct { 861 /** reserved_3_192 : R; bitpos: [7:0]; default: 0; 862 * reserved 863 */ 864 uint32_t reserved_3_192:8; 865 /** custom_mac : R; bitpos: [31:8]; default: 0; 866 * Custom MAC 867 */ 868 uint32_t custom_mac:24; 869 }; 870 uint32_t val; 871 } efuse_rd_usr_data6_reg_t; 872 873 /** Type of rd_usr_data7 register 874 * Register $n of BLOCK3 (user). 875 */ 876 typedef union { 877 struct { 878 /** custom_mac_1 : R; bitpos: [23:0]; default: 0; 879 * Custom MAC 880 */ 881 uint32_t custom_mac_1:24; 882 /** reserved_3_248 : R; bitpos: [31:24]; default: 0; 883 * reserved 884 */ 885 uint32_t reserved_3_248:8; 886 }; 887 uint32_t val; 888 } efuse_rd_usr_data7_reg_t; 889 890 /** Type of rd_key0_data0 register 891 * Register $n of BLOCK4 (KEY0). 892 */ 893 typedef union { 894 struct { 895 /** key0_data0 : RO; bitpos: [31:0]; default: 0; 896 * Stores the zeroth 32 bits of KEY0. 897 */ 898 uint32_t key0_data0:32; 899 }; 900 uint32_t val; 901 } efuse_rd_key0_data0_reg_t; 902 903 /** Type of rd_key0_data1 register 904 * Register $n of BLOCK4 (KEY0). 905 */ 906 typedef union { 907 struct { 908 /** key0_data1 : RO; bitpos: [31:0]; default: 0; 909 * Stores the first 32 bits of KEY0. 910 */ 911 uint32_t key0_data1:32; 912 }; 913 uint32_t val; 914 } efuse_rd_key0_data1_reg_t; 915 916 /** Type of rd_key0_data2 register 917 * Register $n of BLOCK4 (KEY0). 918 */ 919 typedef union { 920 struct { 921 /** key0_data2 : RO; bitpos: [31:0]; default: 0; 922 * Stores the second 32 bits of KEY0. 923 */ 924 uint32_t key0_data2:32; 925 }; 926 uint32_t val; 927 } efuse_rd_key0_data2_reg_t; 928 929 /** Type of rd_key0_data3 register 930 * Register $n of BLOCK4 (KEY0). 931 */ 932 typedef union { 933 struct { 934 /** key0_data3 : RO; bitpos: [31:0]; default: 0; 935 * Stores the third 32 bits of KEY0. 936 */ 937 uint32_t key0_data3:32; 938 }; 939 uint32_t val; 940 } efuse_rd_key0_data3_reg_t; 941 942 /** Type of rd_key0_data4 register 943 * Register $n of BLOCK4 (KEY0). 944 */ 945 typedef union { 946 struct { 947 /** key0_data4 : RO; bitpos: [31:0]; default: 0; 948 * Stores the fourth 32 bits of KEY0. 949 */ 950 uint32_t key0_data4:32; 951 }; 952 uint32_t val; 953 } efuse_rd_key0_data4_reg_t; 954 955 /** Type of rd_key0_data5 register 956 * Register $n of BLOCK4 (KEY0). 957 */ 958 typedef union { 959 struct { 960 /** key0_data5 : RO; bitpos: [31:0]; default: 0; 961 * Stores the fifth 32 bits of KEY0. 962 */ 963 uint32_t key0_data5:32; 964 }; 965 uint32_t val; 966 } efuse_rd_key0_data5_reg_t; 967 968 /** Type of rd_key0_data6 register 969 * Register $n of BLOCK4 (KEY0). 970 */ 971 typedef union { 972 struct { 973 /** key0_data6 : RO; bitpos: [31:0]; default: 0; 974 * Stores the sixth 32 bits of KEY0. 975 */ 976 uint32_t key0_data6:32; 977 }; 978 uint32_t val; 979 } efuse_rd_key0_data6_reg_t; 980 981 /** Type of rd_key0_data7 register 982 * Register $n of BLOCK4 (KEY0). 983 */ 984 typedef union { 985 struct { 986 /** key0_data7 : RO; bitpos: [31:0]; default: 0; 987 * Stores the seventh 32 bits of KEY0. 988 */ 989 uint32_t key0_data7:32; 990 }; 991 uint32_t val; 992 } efuse_rd_key0_data7_reg_t; 993 994 /** Type of rd_key1_data0 register 995 * Register $n of BLOCK5 (KEY1). 996 */ 997 typedef union { 998 struct { 999 /** key1_data0 : RO; bitpos: [31:0]; default: 0; 1000 * Stores the zeroth 32 bits of KEY1. 1001 */ 1002 uint32_t key1_data0:32; 1003 }; 1004 uint32_t val; 1005 } efuse_rd_key1_data0_reg_t; 1006 1007 /** Type of rd_key1_data1 register 1008 * Register $n of BLOCK5 (KEY1). 1009 */ 1010 typedef union { 1011 struct { 1012 /** key1_data1 : RO; bitpos: [31:0]; default: 0; 1013 * Stores the first 32 bits of KEY1. 1014 */ 1015 uint32_t key1_data1:32; 1016 }; 1017 uint32_t val; 1018 } efuse_rd_key1_data1_reg_t; 1019 1020 /** Type of rd_key1_data2 register 1021 * Register $n of BLOCK5 (KEY1). 1022 */ 1023 typedef union { 1024 struct { 1025 /** key1_data2 : RO; bitpos: [31:0]; default: 0; 1026 * Stores the second 32 bits of KEY1. 1027 */ 1028 uint32_t key1_data2:32; 1029 }; 1030 uint32_t val; 1031 } efuse_rd_key1_data2_reg_t; 1032 1033 /** Type of rd_key1_data3 register 1034 * Register $n of BLOCK5 (KEY1). 1035 */ 1036 typedef union { 1037 struct { 1038 /** key1_data3 : RO; bitpos: [31:0]; default: 0; 1039 * Stores the third 32 bits of KEY1. 1040 */ 1041 uint32_t key1_data3:32; 1042 }; 1043 uint32_t val; 1044 } efuse_rd_key1_data3_reg_t; 1045 1046 /** Type of rd_key1_data4 register 1047 * Register $n of BLOCK5 (KEY1). 1048 */ 1049 typedef union { 1050 struct { 1051 /** key1_data4 : RO; bitpos: [31:0]; default: 0; 1052 * Stores the fourth 32 bits of KEY1. 1053 */ 1054 uint32_t key1_data4:32; 1055 }; 1056 uint32_t val; 1057 } efuse_rd_key1_data4_reg_t; 1058 1059 /** Type of rd_key1_data5 register 1060 * Register $n of BLOCK5 (KEY1). 1061 */ 1062 typedef union { 1063 struct { 1064 /** key1_data5 : RO; bitpos: [31:0]; default: 0; 1065 * Stores the fifth 32 bits of KEY1. 1066 */ 1067 uint32_t key1_data5:32; 1068 }; 1069 uint32_t val; 1070 } efuse_rd_key1_data5_reg_t; 1071 1072 /** Type of rd_key1_data6 register 1073 * Register $n of BLOCK5 (KEY1). 1074 */ 1075 typedef union { 1076 struct { 1077 /** key1_data6 : RO; bitpos: [31:0]; default: 0; 1078 * Stores the sixth 32 bits of KEY1. 1079 */ 1080 uint32_t key1_data6:32; 1081 }; 1082 uint32_t val; 1083 } efuse_rd_key1_data6_reg_t; 1084 1085 /** Type of rd_key1_data7 register 1086 * Register $n of BLOCK5 (KEY1). 1087 */ 1088 typedef union { 1089 struct { 1090 /** key1_data7 : RO; bitpos: [31:0]; default: 0; 1091 * Stores the seventh 32 bits of KEY1. 1092 */ 1093 uint32_t key1_data7:32; 1094 }; 1095 uint32_t val; 1096 } efuse_rd_key1_data7_reg_t; 1097 1098 /** Type of rd_key2_data0 register 1099 * Register $n of BLOCK6 (KEY2). 1100 */ 1101 typedef union { 1102 struct { 1103 /** key2_data0 : RO; bitpos: [31:0]; default: 0; 1104 * Stores the zeroth 32 bits of KEY2. 1105 */ 1106 uint32_t key2_data0:32; 1107 }; 1108 uint32_t val; 1109 } efuse_rd_key2_data0_reg_t; 1110 1111 /** Type of rd_key2_data1 register 1112 * Register $n of BLOCK6 (KEY2). 1113 */ 1114 typedef union { 1115 struct { 1116 /** key2_data1 : RO; bitpos: [31:0]; default: 0; 1117 * Stores the first 32 bits of KEY2. 1118 */ 1119 uint32_t key2_data1:32; 1120 }; 1121 uint32_t val; 1122 } efuse_rd_key2_data1_reg_t; 1123 1124 /** Type of rd_key2_data2 register 1125 * Register $n of BLOCK6 (KEY2). 1126 */ 1127 typedef union { 1128 struct { 1129 /** key2_data2 : RO; bitpos: [31:0]; default: 0; 1130 * Stores the second 32 bits of KEY2. 1131 */ 1132 uint32_t key2_data2:32; 1133 }; 1134 uint32_t val; 1135 } efuse_rd_key2_data2_reg_t; 1136 1137 /** Type of rd_key2_data3 register 1138 * Register $n of BLOCK6 (KEY2). 1139 */ 1140 typedef union { 1141 struct { 1142 /** key2_data3 : RO; bitpos: [31:0]; default: 0; 1143 * Stores the third 32 bits of KEY2. 1144 */ 1145 uint32_t key2_data3:32; 1146 }; 1147 uint32_t val; 1148 } efuse_rd_key2_data3_reg_t; 1149 1150 /** Type of rd_key2_data4 register 1151 * Register $n of BLOCK6 (KEY2). 1152 */ 1153 typedef union { 1154 struct { 1155 /** key2_data4 : RO; bitpos: [31:0]; default: 0; 1156 * Stores the fourth 32 bits of KEY2. 1157 */ 1158 uint32_t key2_data4:32; 1159 }; 1160 uint32_t val; 1161 } efuse_rd_key2_data4_reg_t; 1162 1163 /** Type of rd_key2_data5 register 1164 * Register $n of BLOCK6 (KEY2). 1165 */ 1166 typedef union { 1167 struct { 1168 /** key2_data5 : RO; bitpos: [31:0]; default: 0; 1169 * Stores the fifth 32 bits of KEY2. 1170 */ 1171 uint32_t key2_data5:32; 1172 }; 1173 uint32_t val; 1174 } efuse_rd_key2_data5_reg_t; 1175 1176 /** Type of rd_key2_data6 register 1177 * Register $n of BLOCK6 (KEY2). 1178 */ 1179 typedef union { 1180 struct { 1181 /** key2_data6 : RO; bitpos: [31:0]; default: 0; 1182 * Stores the sixth 32 bits of KEY2. 1183 */ 1184 uint32_t key2_data6:32; 1185 }; 1186 uint32_t val; 1187 } efuse_rd_key2_data6_reg_t; 1188 1189 /** Type of rd_key2_data7 register 1190 * Register $n of BLOCK6 (KEY2). 1191 */ 1192 typedef union { 1193 struct { 1194 /** key2_data7 : RO; bitpos: [31:0]; default: 0; 1195 * Stores the seventh 32 bits of KEY2. 1196 */ 1197 uint32_t key2_data7:32; 1198 }; 1199 uint32_t val; 1200 } efuse_rd_key2_data7_reg_t; 1201 1202 /** Type of rd_key3_data0 register 1203 * Register $n of BLOCK7 (KEY3). 1204 */ 1205 typedef union { 1206 struct { 1207 /** key3_data0 : RO; bitpos: [31:0]; default: 0; 1208 * Stores the zeroth 32 bits of KEY3. 1209 */ 1210 uint32_t key3_data0:32; 1211 }; 1212 uint32_t val; 1213 } efuse_rd_key3_data0_reg_t; 1214 1215 /** Type of rd_key3_data1 register 1216 * Register $n of BLOCK7 (KEY3). 1217 */ 1218 typedef union { 1219 struct { 1220 /** key3_data1 : RO; bitpos: [31:0]; default: 0; 1221 * Stores the first 32 bits of KEY3. 1222 */ 1223 uint32_t key3_data1:32; 1224 }; 1225 uint32_t val; 1226 } efuse_rd_key3_data1_reg_t; 1227 1228 /** Type of rd_key3_data2 register 1229 * Register $n of BLOCK7 (KEY3). 1230 */ 1231 typedef union { 1232 struct { 1233 /** key3_data2 : RO; bitpos: [31:0]; default: 0; 1234 * Stores the second 32 bits of KEY3. 1235 */ 1236 uint32_t key3_data2:32; 1237 }; 1238 uint32_t val; 1239 } efuse_rd_key3_data2_reg_t; 1240 1241 /** Type of rd_key3_data3 register 1242 * Register $n of BLOCK7 (KEY3). 1243 */ 1244 typedef union { 1245 struct { 1246 /** key3_data3 : RO; bitpos: [31:0]; default: 0; 1247 * Stores the third 32 bits of KEY3. 1248 */ 1249 uint32_t key3_data3:32; 1250 }; 1251 uint32_t val; 1252 } efuse_rd_key3_data3_reg_t; 1253 1254 /** Type of rd_key3_data4 register 1255 * Register $n of BLOCK7 (KEY3). 1256 */ 1257 typedef union { 1258 struct { 1259 /** key3_data4 : RO; bitpos: [31:0]; default: 0; 1260 * Stores the fourth 32 bits of KEY3. 1261 */ 1262 uint32_t key3_data4:32; 1263 }; 1264 uint32_t val; 1265 } efuse_rd_key3_data4_reg_t; 1266 1267 /** Type of rd_key3_data5 register 1268 * Register $n of BLOCK7 (KEY3). 1269 */ 1270 typedef union { 1271 struct { 1272 /** key3_data5 : RO; bitpos: [31:0]; default: 0; 1273 * Stores the fifth 32 bits of KEY3. 1274 */ 1275 uint32_t key3_data5:32; 1276 }; 1277 uint32_t val; 1278 } efuse_rd_key3_data5_reg_t; 1279 1280 /** Type of rd_key3_data6 register 1281 * Register $n of BLOCK7 (KEY3). 1282 */ 1283 typedef union { 1284 struct { 1285 /** key3_data6 : RO; bitpos: [31:0]; default: 0; 1286 * Stores the sixth 32 bits of KEY3. 1287 */ 1288 uint32_t key3_data6:32; 1289 }; 1290 uint32_t val; 1291 } efuse_rd_key3_data6_reg_t; 1292 1293 /** Type of rd_key3_data7 register 1294 * Register $n of BLOCK7 (KEY3). 1295 */ 1296 typedef union { 1297 struct { 1298 /** key3_data7 : RO; bitpos: [31:0]; default: 0; 1299 * Stores the seventh 32 bits of KEY3. 1300 */ 1301 uint32_t key3_data7:32; 1302 }; 1303 uint32_t val; 1304 } efuse_rd_key3_data7_reg_t; 1305 1306 /** Type of rd_key4_data0 register 1307 * Register $n of BLOCK8 (KEY4). 1308 */ 1309 typedef union { 1310 struct { 1311 /** key4_data0 : RO; bitpos: [31:0]; default: 0; 1312 * Stores the zeroth 32 bits of KEY4. 1313 */ 1314 uint32_t key4_data0:32; 1315 }; 1316 uint32_t val; 1317 } efuse_rd_key4_data0_reg_t; 1318 1319 /** Type of rd_key4_data1 register 1320 * Register $n of BLOCK8 (KEY4). 1321 */ 1322 typedef union { 1323 struct { 1324 /** key4_data1 : RO; bitpos: [31:0]; default: 0; 1325 * Stores the first 32 bits of KEY4. 1326 */ 1327 uint32_t key4_data1:32; 1328 }; 1329 uint32_t val; 1330 } efuse_rd_key4_data1_reg_t; 1331 1332 /** Type of rd_key4_data2 register 1333 * Register $n of BLOCK8 (KEY4). 1334 */ 1335 typedef union { 1336 struct { 1337 /** key4_data2 : RO; bitpos: [31:0]; default: 0; 1338 * Stores the second 32 bits of KEY4. 1339 */ 1340 uint32_t key4_data2:32; 1341 }; 1342 uint32_t val; 1343 } efuse_rd_key4_data2_reg_t; 1344 1345 /** Type of rd_key4_data3 register 1346 * Register $n of BLOCK8 (KEY4). 1347 */ 1348 typedef union { 1349 struct { 1350 /** key4_data3 : RO; bitpos: [31:0]; default: 0; 1351 * Stores the third 32 bits of KEY4. 1352 */ 1353 uint32_t key4_data3:32; 1354 }; 1355 uint32_t val; 1356 } efuse_rd_key4_data3_reg_t; 1357 1358 /** Type of rd_key4_data4 register 1359 * Register $n of BLOCK8 (KEY4). 1360 */ 1361 typedef union { 1362 struct { 1363 /** key4_data4 : RO; bitpos: [31:0]; default: 0; 1364 * Stores the fourth 32 bits of KEY4. 1365 */ 1366 uint32_t key4_data4:32; 1367 }; 1368 uint32_t val; 1369 } efuse_rd_key4_data4_reg_t; 1370 1371 /** Type of rd_key4_data5 register 1372 * Register $n of BLOCK8 (KEY4). 1373 */ 1374 typedef union { 1375 struct { 1376 /** key4_data5 : RO; bitpos: [31:0]; default: 0; 1377 * Stores the fifth 32 bits of KEY4. 1378 */ 1379 uint32_t key4_data5:32; 1380 }; 1381 uint32_t val; 1382 } efuse_rd_key4_data5_reg_t; 1383 1384 /** Type of rd_key4_data6 register 1385 * Register $n of BLOCK8 (KEY4). 1386 */ 1387 typedef union { 1388 struct { 1389 /** key4_data6 : RO; bitpos: [31:0]; default: 0; 1390 * Stores the sixth 32 bits of KEY4. 1391 */ 1392 uint32_t key4_data6:32; 1393 }; 1394 uint32_t val; 1395 } efuse_rd_key4_data6_reg_t; 1396 1397 /** Type of rd_key4_data7 register 1398 * Register $n of BLOCK8 (KEY4). 1399 */ 1400 typedef union { 1401 struct { 1402 /** key4_data7 : RO; bitpos: [31:0]; default: 0; 1403 * Stores the seventh 32 bits of KEY4. 1404 */ 1405 uint32_t key4_data7:32; 1406 }; 1407 uint32_t val; 1408 } efuse_rd_key4_data7_reg_t; 1409 1410 /** Type of rd_key5_data0 register 1411 * Register $n of BLOCK9 (KEY5). 1412 */ 1413 typedef union { 1414 struct { 1415 /** key5_data0 : RO; bitpos: [31:0]; default: 0; 1416 * Stores the zeroth 32 bits of KEY5. 1417 */ 1418 uint32_t key5_data0:32; 1419 }; 1420 uint32_t val; 1421 } efuse_rd_key5_data0_reg_t; 1422 1423 /** Type of rd_key5_data1 register 1424 * Register $n of BLOCK9 (KEY5). 1425 */ 1426 typedef union { 1427 struct { 1428 /** key5_data1 : RO; bitpos: [31:0]; default: 0; 1429 * Stores the first 32 bits of KEY5. 1430 */ 1431 uint32_t key5_data1:32; 1432 }; 1433 uint32_t val; 1434 } efuse_rd_key5_data1_reg_t; 1435 1436 /** Type of rd_key5_data2 register 1437 * Register $n of BLOCK9 (KEY5). 1438 */ 1439 typedef union { 1440 struct { 1441 /** key5_data2 : RO; bitpos: [31:0]; default: 0; 1442 * Stores the second 32 bits of KEY5. 1443 */ 1444 uint32_t key5_data2:32; 1445 }; 1446 uint32_t val; 1447 } efuse_rd_key5_data2_reg_t; 1448 1449 /** Type of rd_key5_data3 register 1450 * Register $n of BLOCK9 (KEY5). 1451 */ 1452 typedef union { 1453 struct { 1454 /** key5_data3 : RO; bitpos: [31:0]; default: 0; 1455 * Stores the third 32 bits of KEY5. 1456 */ 1457 uint32_t key5_data3:32; 1458 }; 1459 uint32_t val; 1460 } efuse_rd_key5_data3_reg_t; 1461 1462 /** Type of rd_key5_data4 register 1463 * Register $n of BLOCK9 (KEY5). 1464 */ 1465 typedef union { 1466 struct { 1467 /** key5_data4 : RO; bitpos: [31:0]; default: 0; 1468 * Stores the fourth 32 bits of KEY5. 1469 */ 1470 uint32_t key5_data4:32; 1471 }; 1472 uint32_t val; 1473 } efuse_rd_key5_data4_reg_t; 1474 1475 /** Type of rd_key5_data5 register 1476 * Register $n of BLOCK9 (KEY5). 1477 */ 1478 typedef union { 1479 struct { 1480 /** key5_data5 : RO; bitpos: [31:0]; default: 0; 1481 * Stores the fifth 32 bits of KEY5. 1482 */ 1483 uint32_t key5_data5:32; 1484 }; 1485 uint32_t val; 1486 } efuse_rd_key5_data5_reg_t; 1487 1488 /** Type of rd_key5_data6 register 1489 * Register $n of BLOCK9 (KEY5). 1490 */ 1491 typedef union { 1492 struct { 1493 /** key5_data6 : RO; bitpos: [31:0]; default: 0; 1494 * Stores the sixth 32 bits of KEY5. 1495 */ 1496 uint32_t key5_data6:32; 1497 }; 1498 uint32_t val; 1499 } efuse_rd_key5_data6_reg_t; 1500 1501 /** Type of rd_key5_data7 register 1502 * Register $n of BLOCK9 (KEY5). 1503 */ 1504 typedef union { 1505 struct { 1506 /** key5_data7 : RO; bitpos: [31:0]; default: 0; 1507 * Stores the seventh 32 bits of KEY5. 1508 */ 1509 uint32_t key5_data7:32; 1510 }; 1511 uint32_t val; 1512 } efuse_rd_key5_data7_reg_t; 1513 1514 /** Type of rd_sys_part2_data0 register 1515 * Register $n of BLOCK10 (system). 1516 */ 1517 typedef union { 1518 struct { 1519 /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0; 1520 * Stores the $nth 32 bits of the 2nd part of system data. 1521 */ 1522 uint32_t sys_data_part2_0:32; 1523 }; 1524 uint32_t val; 1525 } efuse_rd_sys_part2_data0_reg_t; 1526 1527 /** Type of rd_sys_part2_data1 register 1528 * Register $n of BLOCK9 (KEY5). 1529 */ 1530 typedef union { 1531 struct { 1532 /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0; 1533 * Stores the $nth 32 bits of the 2nd part of system data. 1534 */ 1535 uint32_t sys_data_part2_1:32; 1536 }; 1537 uint32_t val; 1538 } efuse_rd_sys_part2_data1_reg_t; 1539 1540 /** Type of rd_sys_part2_data2 register 1541 * Register $n of BLOCK10 (system). 1542 */ 1543 typedef union { 1544 struct { 1545 /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0; 1546 * Stores the $nth 32 bits of the 2nd part of system data. 1547 */ 1548 uint32_t sys_data_part2_2:32; 1549 }; 1550 uint32_t val; 1551 } efuse_rd_sys_part2_data2_reg_t; 1552 1553 /** Type of rd_sys_part2_data3 register 1554 * Register $n of BLOCK10 (system). 1555 */ 1556 typedef union { 1557 struct { 1558 /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0; 1559 * Stores the $nth 32 bits of the 2nd part of system data. 1560 */ 1561 uint32_t sys_data_part2_3:32; 1562 }; 1563 uint32_t val; 1564 } efuse_rd_sys_part2_data3_reg_t; 1565 1566 /** Type of rd_sys_part2_data4 register 1567 * Register $n of BLOCK10 (system). 1568 */ 1569 typedef union { 1570 struct { 1571 /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0; 1572 * Stores the $nth 32 bits of the 2nd part of system data. 1573 */ 1574 uint32_t sys_data_part2_4:32; 1575 }; 1576 uint32_t val; 1577 } efuse_rd_sys_part2_data4_reg_t; 1578 1579 /** Type of rd_sys_part2_data5 register 1580 * Register $n of BLOCK10 (system). 1581 */ 1582 typedef union { 1583 struct { 1584 /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0; 1585 * Stores the $nth 32 bits of the 2nd part of system data. 1586 */ 1587 uint32_t sys_data_part2_5:32; 1588 }; 1589 uint32_t val; 1590 } efuse_rd_sys_part2_data5_reg_t; 1591 1592 /** Type of rd_sys_part2_data6 register 1593 * Register $n of BLOCK10 (system). 1594 */ 1595 typedef union { 1596 struct { 1597 /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0; 1598 * Stores the $nth 32 bits of the 2nd part of system data. 1599 */ 1600 uint32_t sys_data_part2_6:32; 1601 }; 1602 uint32_t val; 1603 } efuse_rd_sys_part2_data6_reg_t; 1604 1605 /** Type of rd_sys_part2_data7 register 1606 * Register $n of BLOCK10 (system). 1607 */ 1608 typedef union { 1609 struct { 1610 /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0; 1611 * Stores the $nth 32 bits of the 2nd part of system data. 1612 */ 1613 uint32_t sys_data_part2_7:32; 1614 }; 1615 uint32_t val; 1616 } efuse_rd_sys_part2_data7_reg_t; 1617 1618 1619 /** Group: Report Register */ 1620 /** Type of rd_repeat_err0 register 1621 * Programming error record register 0 of BLOCK0. 1622 */ 1623 typedef union { 1624 struct { 1625 /** rd_dis_err : RO; bitpos: [6:0]; default: 0; 1626 * Indicates a programming error of RD_DIS. 1627 */ 1628 uint32_t rd_dis_err:7; 1629 /** rpt4_reserved0_err_4 : RO; bitpos: [7]; default: 0; 1630 * Reserved. 1631 */ 1632 uint32_t rpt4_reserved0_err_4:1; 1633 /** dis_icache_err : RO; bitpos: [8]; default: 0; 1634 * Indicates a programming error of DIS_ICACHE. 1635 */ 1636 uint32_t dis_icache_err:1; 1637 /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0; 1638 * Indicates a programming error of DIS_USB_JTAG. 1639 */ 1640 uint32_t dis_usb_jtag_err:1; 1641 /** powerglitch_en_err : RO; bitpos: [10]; default: 0; 1642 * Indicates a programming error of POWERGLITCH_EN. 1643 */ 1644 uint32_t powerglitch_en_err:1; 1645 /** dis_usb_serial_jtag_err : RO; bitpos: [11]; default: 0; 1646 * Indicates a programming error of DIS_USB_DEVICE. 1647 */ 1648 uint32_t dis_usb_serial_jtag_err:1; 1649 /** dis_force_download_err : RO; bitpos: [12]; default: 0; 1650 * Indicates a programming error of DIS_FORCE_DOWNLOAD. 1651 */ 1652 uint32_t dis_force_download_err:1; 1653 /** spi_download_mspi_dis_err : RO; bitpos: [13]; default: 0; 1654 * Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. 1655 */ 1656 uint32_t spi_download_mspi_dis_err:1; 1657 /** dis_twai_err : RO; bitpos: [14]; default: 0; 1658 * Indicates a programming error of DIS_CAN. 1659 */ 1660 uint32_t dis_twai_err:1; 1661 /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0; 1662 * Indicates a programming error of JTAG_SEL_ENABLE. 1663 */ 1664 uint32_t jtag_sel_enable_err:1; 1665 /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0; 1666 * Indicates a programming error of SOFT_DIS_JTAG. 1667 */ 1668 uint32_t soft_dis_jtag_err:3; 1669 /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0; 1670 * Indicates a programming error of DIS_PAD_JTAG. 1671 */ 1672 uint32_t dis_pad_jtag_err:1; 1673 /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0; 1674 * Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. 1675 */ 1676 uint32_t dis_download_manual_encrypt_err:1; 1677 /** usb_drefh_err : RO; bitpos: [22:21]; default: 0; 1678 * Indicates a programming error of USB_DREFH. 1679 */ 1680 uint32_t usb_drefh_err:2; 1681 /** usb_drefl_err : RO; bitpos: [24:23]; default: 0; 1682 * Indicates a programming error of USB_DREFL. 1683 */ 1684 uint32_t usb_drefl_err:2; 1685 /** usb_exchg_pins_err : RO; bitpos: [25]; default: 0; 1686 * Indicates a programming error of USB_EXCHG_PINS. 1687 */ 1688 uint32_t usb_exchg_pins_err:1; 1689 /** vdd_spi_as_gpio_err : RO; bitpos: [26]; default: 0; 1690 * Indicates a programming error of VDD_SPI_AS_GPIO. 1691 */ 1692 uint32_t vdd_spi_as_gpio_err:1; 1693 /** rpt4_reserved0_err_2 : RO; bitpos: [28:27]; default: 0; 1694 * Reserved. 1695 */ 1696 uint32_t rpt4_reserved0_err_2:2; 1697 /** rpt4_reserved0_err_1 : RO; bitpos: [29]; default: 0; 1698 * Reserved. 1699 */ 1700 uint32_t rpt4_reserved0_err_1:1; 1701 /** rpt4_reserved0_err_0 : RO; bitpos: [31:30]; default: 0; 1702 * Reserved. 1703 */ 1704 uint32_t rpt4_reserved0_err_0:2; 1705 }; 1706 uint32_t val; 1707 } efuse_rd_repeat_err0_reg_t; 1708 1709 /** Type of rd_repeat_err1 register 1710 * Programming error record register 1 of BLOCK0. 1711 */ 1712 typedef union { 1713 struct { 1714 /** rpt4_reserved1_err_0 : RO; bitpos: [15:0]; default: 0; 1715 * Reserved. 1716 */ 1717 uint32_t rpt4_reserved1_err_0:16; 1718 /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0; 1719 * Indicates a programming error of WDT_DELAY_SEL. 1720 */ 1721 uint32_t wdt_delay_sel_err:2; 1722 /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0; 1723 * Indicates a programming error of SPI_BOOT_CRYPT_CNT. 1724 */ 1725 uint32_t spi_boot_crypt_cnt_err:3; 1726 /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0; 1727 * Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. 1728 */ 1729 uint32_t secure_boot_key_revoke0_err:1; 1730 /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0; 1731 * Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. 1732 */ 1733 uint32_t secure_boot_key_revoke1_err:1; 1734 /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0; 1735 * Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. 1736 */ 1737 uint32_t secure_boot_key_revoke2_err:1; 1738 /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0; 1739 * Indicates a programming error of KEY_PURPOSE_0. 1740 */ 1741 uint32_t key_purpose_0_err:4; 1742 /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0; 1743 * Indicates a programming error of KEY_PURPOSE_1. 1744 */ 1745 uint32_t key_purpose_1_err:4; 1746 }; 1747 uint32_t val; 1748 } efuse_rd_repeat_err1_reg_t; 1749 1750 /** Type of rd_repeat_err2 register 1751 * Programming error record register 2 of BLOCK0. 1752 */ 1753 typedef union { 1754 struct { 1755 /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0; 1756 * Indicates a programming error of KEY_PURPOSE_2. 1757 */ 1758 uint32_t key_purpose_2_err:4; 1759 /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0; 1760 * Indicates a programming error of KEY_PURPOSE_3. 1761 */ 1762 uint32_t key_purpose_3_err:4; 1763 /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0; 1764 * Indicates a programming error of KEY_PURPOSE_4. 1765 */ 1766 uint32_t key_purpose_4_err:4; 1767 /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0; 1768 * Indicates a programming error of KEY_PURPOSE_5. 1769 */ 1770 uint32_t key_purpose_5_err:4; 1771 /** sec_dpa_level_err : RO; bitpos: [17:16]; default: 0; 1772 * Indicates a programming error of SEC_DPA_LEVEL. 1773 */ 1774 uint32_t sec_dpa_level_err:2; 1775 /** rpt4_reserved2_err_1 : RO; bitpos: [18]; default: 0; 1776 * Reserved. 1777 */ 1778 uint32_t rpt4_reserved2_err_1:1; 1779 /** crypt_dpa_enable_err : RO; bitpos: [19]; default: 0; 1780 * Indicates a programming error of CRYPT_DPA_ENABLE. 1781 */ 1782 uint32_t crypt_dpa_enable_err:1; 1783 /** secure_boot_en_err : RO; bitpos: [20]; default: 0; 1784 * Indicates a programming error of SECURE_BOOT_EN. 1785 */ 1786 uint32_t secure_boot_en_err:1; 1787 /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0; 1788 * Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. 1789 */ 1790 uint32_t secure_boot_aggressive_revoke_err:1; 1791 /** rpt4_reserved2_err_0 : RO; bitpos: [27:22]; default: 0; 1792 * Reserved. 1793 */ 1794 uint32_t rpt4_reserved2_err_0:6; 1795 /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0; 1796 * Indicates a programming error of FLASH_TPUW. 1797 */ 1798 uint32_t flash_tpuw_err:4; 1799 }; 1800 uint32_t val; 1801 } efuse_rd_repeat_err2_reg_t; 1802 1803 /** Type of rd_repeat_err3 register 1804 * Programming error record register 3 of BLOCK0. 1805 */ 1806 typedef union { 1807 struct { 1808 /** dis_download_mode_err : RO; bitpos: [0]; default: 0; 1809 * Indicates a programming error of DIS_DOWNLOAD_MODE. 1810 */ 1811 uint32_t dis_download_mode_err:1; 1812 /** dis_direct_boot_err : RO; bitpos: [1]; default: 0; 1813 * Indicates a programming error of DIS_DIRECT_BOOT. 1814 */ 1815 uint32_t dis_direct_boot_err:1; 1816 /** usb_print_err : RO; bitpos: [2]; default: 0; 1817 * Indicates a programming error of UART_PRINT_CHANNEL. 1818 */ 1819 uint32_t usb_print_err:1; 1820 /** rpt4_reserved3_err_5 : RO; bitpos: [3]; default: 0; 1821 * Reserved. 1822 */ 1823 uint32_t rpt4_reserved3_err_5:1; 1824 /** dis_usb_serial_jtag_download_mode_err : RO; bitpos: [4]; default: 0; 1825 * Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. 1826 */ 1827 uint32_t dis_usb_serial_jtag_download_mode_err:1; 1828 /** enable_security_download_err : RO; bitpos: [5]; default: 0; 1829 * Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. 1830 */ 1831 uint32_t enable_security_download_err:1; 1832 /** uart_print_control_err : RO; bitpos: [7:6]; default: 0; 1833 * Indicates a programming error of UART_PRINT_CONTROL. 1834 */ 1835 uint32_t uart_print_control_err:2; 1836 /** force_send_resume_err : RO; bitpos: [8]; default: 0; 1837 * Indicates a programming error of FORCE_SEND_RESUME. 1838 */ 1839 uint32_t force_send_resume_err:1; 1840 /** secure_version_err : RO; bitpos: [24:9]; default: 0; 1841 * Indicates a programming error of SECURE VERSION. 1842 */ 1843 uint32_t secure_version_err:16; 1844 /** secure_boot_disable_fast_wake_err : RO; bitpos: [25]; default: 0; 1845 * Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE. 1846 */ 1847 uint32_t secure_boot_disable_fast_wake_err:1; 1848 /** hys_en_pad0_err : RO; bitpos: [31:26]; default: 0; 1849 * Indicates a programming error of HYS_EN_PAD0. 1850 */ 1851 uint32_t hys_en_pad0_err:6; 1852 }; 1853 uint32_t val; 1854 } efuse_rd_repeat_err3_reg_t; 1855 1856 /** Type of rd_repeat_err4 register 1857 * Programming error record register 4 of BLOCK0. 1858 */ 1859 typedef union { 1860 struct { 1861 /** hys_en_pad1_err : RO; bitpos: [21:0]; default: 0; 1862 * Indicates a programming error of HYS_EN_PAD1. 1863 */ 1864 uint32_t hys_en_pad1_err:22; 1865 /** rpt4_reserved4_err_1 : RO; bitpos: [23:22]; default: 0; 1866 * Reserved. 1867 */ 1868 uint32_t rpt4_reserved4_err_1:2; 1869 /** rpt4_reserved4_err_0 : RO; bitpos: [31:24]; default: 0; 1870 * Reserved. 1871 */ 1872 uint32_t rpt4_reserved4_err_0:8; 1873 }; 1874 uint32_t val; 1875 } efuse_rd_repeat_err4_reg_t; 1876 1877 /** Type of rd_rs_err0 register 1878 * Programming error record register 0 of BLOCK1-10. 1879 */ 1880 typedef union { 1881 struct { 1882 /** mac_spi_8m_err_num : RO; bitpos: [2:0]; default: 0; 1883 * The value of this signal means the number of error bytes. 1884 */ 1885 uint32_t mac_spi_8m_err_num:3; 1886 /** mac_spi_8m_fail : RO; bitpos: [3]; default: 0; 1887 * 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that 1888 * programming user data failed and the number of error bytes is over 6. 1889 */ 1890 uint32_t mac_spi_8m_fail:1; 1891 /** sys_part1_num : RO; bitpos: [6:4]; default: 0; 1892 * The value of this signal means the number of error bytes. 1893 */ 1894 uint32_t sys_part1_num:3; 1895 /** sys_part1_fail : RO; bitpos: [7]; default: 0; 1896 * 0: Means no failure and that the data of system part1 is reliable 1: Means that 1897 * programming user data failed and the number of error bytes is over 6. 1898 */ 1899 uint32_t sys_part1_fail:1; 1900 /** usr_data_err_num : RO; bitpos: [10:8]; default: 0; 1901 * The value of this signal means the number of error bytes. 1902 */ 1903 uint32_t usr_data_err_num:3; 1904 /** usr_data_fail : RO; bitpos: [11]; default: 0; 1905 * 0: Means no failure and that the user data is reliable 1: Means that programming 1906 * user data failed and the number of error bytes is over 6. 1907 */ 1908 uint32_t usr_data_fail:1; 1909 /** key0_err_num : RO; bitpos: [14:12]; default: 0; 1910 * The value of this signal means the number of error bytes. 1911 */ 1912 uint32_t key0_err_num:3; 1913 /** key0_fail : RO; bitpos: [15]; default: 0; 1914 * 0: Means no failure and that the data of key0 is reliable 1: Means that programming 1915 * key0 failed and the number of error bytes is over 6. 1916 */ 1917 uint32_t key0_fail:1; 1918 /** key1_err_num : RO; bitpos: [18:16]; default: 0; 1919 * The value of this signal means the number of error bytes. 1920 */ 1921 uint32_t key1_err_num:3; 1922 /** key1_fail : RO; bitpos: [19]; default: 0; 1923 * 0: Means no failure and that the data of key1 is reliable 1: Means that programming 1924 * key1 failed and the number of error bytes is over 6. 1925 */ 1926 uint32_t key1_fail:1; 1927 /** key2_err_num : RO; bitpos: [22:20]; default: 0; 1928 * The value of this signal means the number of error bytes. 1929 */ 1930 uint32_t key2_err_num:3; 1931 /** key2_fail : RO; bitpos: [23]; default: 0; 1932 * 0: Means no failure and that the data of key2 is reliable 1: Means that programming 1933 * key2 failed and the number of error bytes is over 6. 1934 */ 1935 uint32_t key2_fail:1; 1936 /** key3_err_num : RO; bitpos: [26:24]; default: 0; 1937 * The value of this signal means the number of error bytes. 1938 */ 1939 uint32_t key3_err_num:3; 1940 /** key3_fail : RO; bitpos: [27]; default: 0; 1941 * 0: Means no failure and that the data of key3 is reliable 1: Means that programming 1942 * key3 failed and the number of error bytes is over 6. 1943 */ 1944 uint32_t key3_fail:1; 1945 /** key4_err_num : RO; bitpos: [30:28]; default: 0; 1946 * The value of this signal means the number of error bytes. 1947 */ 1948 uint32_t key4_err_num:3; 1949 /** key4_fail : RO; bitpos: [31]; default: 0; 1950 * 0: Means no failure and that the data of key4 is reliable 1: Means that programming 1951 * key4 failed and the number of error bytes is over 6. 1952 */ 1953 uint32_t key4_fail:1; 1954 }; 1955 uint32_t val; 1956 } efuse_rd_rs_err0_reg_t; 1957 1958 /** Type of rd_rs_err1 register 1959 * Programming error record register 1 of BLOCK1-10. 1960 */ 1961 typedef union { 1962 struct { 1963 /** key5_err_num : RO; bitpos: [2:0]; default: 0; 1964 * The value of this signal means the number of error bytes. 1965 */ 1966 uint32_t key5_err_num:3; 1967 /** key5_fail : RO; bitpos: [3]; default: 0; 1968 * 0: Means no failure and that the data of key5 is reliable 1: Means that programming 1969 * key5 failed and the number of error bytes is over 6. 1970 */ 1971 uint32_t key5_fail:1; 1972 /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0; 1973 * The value of this signal means the number of error bytes. 1974 */ 1975 uint32_t sys_part2_err_num:3; 1976 /** sys_part2_fail : RO; bitpos: [7]; default: 0; 1977 * 0: Means no failure and that the data of system part2 is reliable 1: Means that 1978 * programming user data failed and the number of error bytes is over 6. 1979 */ 1980 uint32_t sys_part2_fail:1; 1981 uint32_t reserved_8:24; 1982 }; 1983 uint32_t val; 1984 } efuse_rd_rs_err1_reg_t; 1985 1986 1987 /** Group: Configuration Register */ 1988 /** Type of clk register 1989 * eFuse clcok configuration register. 1990 */ 1991 typedef union { 1992 struct { 1993 /** mem_force_pd : R/W; bitpos: [0]; default: 0; 1994 * Set this bit to force eFuse SRAM into power-saving mode. 1995 */ 1996 uint32_t mem_force_pd:1; 1997 /** mem_clk_force_on : R/W; bitpos: [1]; default: 1; 1998 * Set this bit and force to activate clock signal of eFuse SRAM. 1999 */ 2000 uint32_t mem_clk_force_on:1; 2001 /** mem_force_pu : R/W; bitpos: [2]; default: 0; 2002 * Set this bit to force eFuse SRAM into working mode. 2003 */ 2004 uint32_t mem_force_pu:1; 2005 uint32_t reserved_3:13; 2006 /** clk_en : R/W; bitpos: [16]; default: 0; 2007 * Set this bit to force enable eFuse register configuration clock signal. 2008 */ 2009 uint32_t clk_en:1; 2010 uint32_t reserved_17:15; 2011 }; 2012 uint32_t val; 2013 } efuse_clk_reg_t; 2014 2015 /** Type of conf register 2016 * eFuse operation mode configuraiton register 2017 */ 2018 typedef union { 2019 struct { 2020 /** op_code : R/W; bitpos: [15:0]; default: 0; 2021 * 0x5A5A: programming operation command 0x5AA5: read operation command. 2022 */ 2023 uint32_t op_code:16; 2024 /** cfg_ecdsa_blk : R/W; bitpos: [19:16]; default: 0; 2025 * Configures which block to use for ECDSA key output. 2026 */ 2027 uint32_t cfg_ecdsa_blk:4; 2028 uint32_t reserved_20:12; 2029 }; 2030 uint32_t val; 2031 } efuse_conf_reg_t; 2032 2033 /** Type of cmd register 2034 * eFuse command register. 2035 */ 2036 typedef union { 2037 struct { 2038 /** read_cmd : R/W/SC; bitpos: [0]; default: 0; 2039 * Set this bit to send read command. 2040 */ 2041 uint32_t read_cmd:1; 2042 /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0; 2043 * Set this bit to send programming command. 2044 */ 2045 uint32_t pgm_cmd:1; 2046 /** blk_num : R/W; bitpos: [5:2]; default: 0; 2047 * The serial number of the block to be programmed. Value 0-10 corresponds to block 2048 * number 0-10, respectively. 2049 */ 2050 uint32_t blk_num:4; 2051 uint32_t reserved_6:26; 2052 }; 2053 uint32_t val; 2054 } efuse_cmd_reg_t; 2055 2056 /** Type of dac_conf register 2057 * Controls the eFuse programming voltage. 2058 */ 2059 typedef union { 2060 struct { 2061 /** dac_clk_div : R/W; bitpos: [7:0]; default: 23; 2062 * Controls the division factor of the rising clock of the programming voltage. 2063 */ 2064 uint32_t dac_clk_div:8; 2065 /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0; 2066 * Don't care. 2067 */ 2068 uint32_t dac_clk_pad_sel:1; 2069 /** dac_num : R/W; bitpos: [16:9]; default: 255; 2070 * Controls the rising period of the programming voltage. 2071 */ 2072 uint32_t dac_num:8; 2073 /** oe_clr : R/W; bitpos: [17]; default: 0; 2074 * Reduces the power supply of the programming voltage. 2075 */ 2076 uint32_t oe_clr:1; 2077 uint32_t reserved_18:14; 2078 }; 2079 uint32_t val; 2080 } efuse_dac_conf_reg_t; 2081 2082 /** Type of rd_tim_conf register 2083 * Configures read timing parameters. 2084 */ 2085 typedef union { 2086 struct { 2087 /** thr_a : R/W; bitpos: [7:0]; default: 1; 2088 * Configures the read hold time. 2089 */ 2090 uint32_t thr_a:8; 2091 /** trd : R/W; bitpos: [15:8]; default: 2; 2092 * Configures the read time. 2093 */ 2094 uint32_t trd:8; 2095 /** tsur_a : R/W; bitpos: [23:16]; default: 1; 2096 * Configures the read setup time. 2097 */ 2098 uint32_t tsur_a:8; 2099 /** read_init_num : R/W; bitpos: [31:24]; default: 15; 2100 * Configures the waiting time of reading eFuse memory. 2101 */ 2102 uint32_t read_init_num:8; 2103 }; 2104 uint32_t val; 2105 } efuse_rd_tim_conf_reg_t; 2106 2107 /** Type of wr_tim_conf1 register 2108 * Configurarion register 1 of eFuse programming timing parameters. 2109 */ 2110 typedef union { 2111 struct { 2112 /** tsup_a : R/W; bitpos: [7:0]; default: 1; 2113 * Configures the programming setup time. 2114 */ 2115 uint32_t tsup_a:8; 2116 /** pwr_on_num : R/W; bitpos: [23:8]; default: 9831; 2117 * Configures the power up time for VDDQ. 2118 */ 2119 uint32_t pwr_on_num:16; 2120 /** thp_a : R/W; bitpos: [31:24]; default: 1; 2121 * Configures the programming hold time. 2122 */ 2123 uint32_t thp_a:8; 2124 }; 2125 uint32_t val; 2126 } efuse_wr_tim_conf1_reg_t; 2127 2128 /** Type of wr_tim_conf2 register 2129 * Configurarion register 2 of eFuse programming timing parameters. 2130 */ 2131 typedef union { 2132 struct { 2133 /** pwr_off_num : R/W; bitpos: [15:0]; default: 320; 2134 * Configures the power outage time for VDDQ. 2135 */ 2136 uint32_t pwr_off_num:16; 2137 /** tpgm : R/W; bitpos: [31:16]; default: 160; 2138 * Configures the active programming time. 2139 */ 2140 uint32_t tpgm:16; 2141 }; 2142 uint32_t val; 2143 } efuse_wr_tim_conf2_reg_t; 2144 2145 /** Type of wr_tim_conf0_rs_bypass register 2146 * Configurarion register0 of eFuse programming time parameters and rs bypass 2147 * operation. 2148 */ 2149 typedef union { 2150 struct { 2151 /** bypass_rs_correction : R/W; bitpos: [0]; default: 0; 2152 * Set this bit to bypass reed solomon correction step. 2153 */ 2154 uint32_t bypass_rs_correction:1; 2155 /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0; 2156 * Configures block number of programming twice operation. 2157 */ 2158 uint32_t bypass_rs_blk_num:11; 2159 /** update : WT; bitpos: [12]; default: 0; 2160 * Set this bit to update multi-bit register signals. 2161 */ 2162 uint32_t update:1; 2163 /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1; 2164 * Configures the inactive programming time. 2165 */ 2166 uint32_t tpgm_inactive:8; 2167 uint32_t reserved_21:11; 2168 }; 2169 uint32_t val; 2170 } efuse_wr_tim_conf0_rs_bypass_reg_t; 2171 2172 2173 /** Group: Status Register */ 2174 /** Type of status register 2175 * eFuse status register. 2176 */ 2177 typedef union { 2178 struct { 2179 /** state : RO; bitpos: [3:0]; default: 0; 2180 * Indicates the state of the eFuse state machine. 2181 */ 2182 uint32_t state:4; 2183 /** otp_load_sw : RO; bitpos: [4]; default: 0; 2184 * The value of OTP_LOAD_SW. 2185 */ 2186 uint32_t otp_load_sw:1; 2187 /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0; 2188 * The value of OTP_VDDQ_C_SYNC2. 2189 */ 2190 uint32_t otp_vddq_c_sync2:1; 2191 /** otp_strobe_sw : RO; bitpos: [6]; default: 0; 2192 * The value of OTP_STROBE_SW. 2193 */ 2194 uint32_t otp_strobe_sw:1; 2195 /** otp_csb_sw : RO; bitpos: [7]; default: 0; 2196 * The value of OTP_CSB_SW. 2197 */ 2198 uint32_t otp_csb_sw:1; 2199 /** otp_pgenb_sw : RO; bitpos: [8]; default: 0; 2200 * The value of OTP_PGENB_SW. 2201 */ 2202 uint32_t otp_pgenb_sw:1; 2203 /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0; 2204 * The value of OTP_VDDQ_IS_SW. 2205 */ 2206 uint32_t otp_vddq_is_sw:1; 2207 /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0; 2208 * Indicates the number of block valid bit. 2209 */ 2210 uint32_t blk0_valid_bit_cnt:10; 2211 /** cur_ecdsa_blk : RO; bitpos: [23:20]; default: 0; 2212 * Indicates which block is used for ECDSA key output. 2213 */ 2214 uint32_t cur_ecdsa_blk:4; 2215 uint32_t reserved_24:8; 2216 }; 2217 uint32_t val; 2218 } efuse_status_reg_t; 2219 2220 2221 /** Group: Interrupt Register */ 2222 /** Type of int_raw register 2223 * eFuse raw interrupt register. 2224 */ 2225 typedef union { 2226 struct { 2227 /** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0; 2228 * The raw bit signal for read_done interrupt. 2229 */ 2230 uint32_t read_done_int_raw:1; 2231 /** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0; 2232 * The raw bit signal for pgm_done interrupt. 2233 */ 2234 uint32_t pgm_done_int_raw:1; 2235 uint32_t reserved_2:30; 2236 }; 2237 uint32_t val; 2238 } efuse_int_raw_reg_t; 2239 2240 /** Type of int_st register 2241 * eFuse interrupt status register. 2242 */ 2243 typedef union { 2244 struct { 2245 /** read_done_int_st : RO; bitpos: [0]; default: 0; 2246 * The status signal for read_done interrupt. 2247 */ 2248 uint32_t read_done_int_st:1; 2249 /** pgm_done_int_st : RO; bitpos: [1]; default: 0; 2250 * The status signal for pgm_done interrupt. 2251 */ 2252 uint32_t pgm_done_int_st:1; 2253 uint32_t reserved_2:30; 2254 }; 2255 uint32_t val; 2256 } efuse_int_st_reg_t; 2257 2258 /** Type of int_ena register 2259 * eFuse interrupt enable register. 2260 */ 2261 typedef union { 2262 struct { 2263 /** read_done_int_ena : R/W; bitpos: [0]; default: 0; 2264 * The enable signal for read_done interrupt. 2265 */ 2266 uint32_t read_done_int_ena:1; 2267 /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0; 2268 * The enable signal for pgm_done interrupt. 2269 */ 2270 uint32_t pgm_done_int_ena:1; 2271 uint32_t reserved_2:30; 2272 }; 2273 uint32_t val; 2274 } efuse_int_ena_reg_t; 2275 2276 /** Type of int_clr register 2277 * eFuse interrupt clear register. 2278 */ 2279 typedef union { 2280 struct { 2281 /** read_done_int_clr : WT; bitpos: [0]; default: 0; 2282 * The clear signal for read_done interrupt. 2283 */ 2284 uint32_t read_done_int_clr:1; 2285 /** pgm_done_int_clr : WT; bitpos: [1]; default: 0; 2286 * The clear signal for pgm_done interrupt. 2287 */ 2288 uint32_t pgm_done_int_clr:1; 2289 uint32_t reserved_2:30; 2290 }; 2291 uint32_t val; 2292 } efuse_int_clr_reg_t; 2293 2294 2295 /** Group: Version Register */ 2296 /** Type of date register 2297 * eFuse version register. 2298 */ 2299 typedef union { 2300 struct { 2301 /** date : R/W; bitpos: [27:0]; default: 35684640; 2302 * Stores eFuse version. 2303 */ 2304 uint32_t date:28; 2305 uint32_t reserved_28:4; 2306 }; 2307 uint32_t val; 2308 } efuse_date_reg_t; 2309 2310 2311 typedef struct { 2312 volatile efuse_pgm_data0_reg_t pgm_data0; 2313 volatile efuse_pgm_data1_reg_t pgm_data1; 2314 volatile efuse_pgm_data2_reg_t pgm_data2; 2315 volatile efuse_pgm_data3_reg_t pgm_data3; 2316 volatile efuse_pgm_data4_reg_t pgm_data4; 2317 volatile efuse_pgm_data5_reg_t pgm_data5; 2318 volatile efuse_pgm_data6_reg_t pgm_data6; 2319 volatile efuse_pgm_data7_reg_t pgm_data7; 2320 volatile efuse_pgm_check_value0_reg_t pgm_check_value0; 2321 volatile efuse_pgm_check_value1_reg_t pgm_check_value1; 2322 volatile efuse_pgm_check_value2_reg_t pgm_check_value2; 2323 volatile efuse_rd_wr_dis_reg_t rd_wr_dis; 2324 volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0; 2325 volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1; 2326 volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2; 2327 volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3; 2328 volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4; 2329 volatile efuse_rd_mac_sys_0_reg_t rd_mac_sys_0; 2330 volatile efuse_rd_mac_sys_1_reg_t rd_mac_sys_1; 2331 volatile efuse_rd_mac_sys_2_reg_t rd_mac_sys_2; 2332 volatile efuse_rd_mac_sys_3_reg_t rd_mac_sys_3; 2333 volatile efuse_rd_mac_sys_4_reg_t rd_mac_sys_4; 2334 volatile efuse_rd_mac_sys_5_reg_t rd_mac_sys_5; 2335 volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0; 2336 volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1; 2337 volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2; 2338 volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3; 2339 volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4; 2340 volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5; 2341 volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6; 2342 volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7; 2343 volatile efuse_rd_usr_data0_reg_t rd_usr_data0; 2344 volatile efuse_rd_usr_data1_reg_t rd_usr_data1; 2345 volatile efuse_rd_usr_data2_reg_t rd_usr_data2; 2346 volatile efuse_rd_usr_data3_reg_t rd_usr_data3; 2347 volatile efuse_rd_usr_data4_reg_t rd_usr_data4; 2348 volatile efuse_rd_usr_data5_reg_t rd_usr_data5; 2349 volatile efuse_rd_usr_data6_reg_t rd_usr_data6; 2350 volatile efuse_rd_usr_data7_reg_t rd_usr_data7; 2351 volatile efuse_rd_key0_data0_reg_t rd_key0_data0; 2352 volatile efuse_rd_key0_data1_reg_t rd_key0_data1; 2353 volatile efuse_rd_key0_data2_reg_t rd_key0_data2; 2354 volatile efuse_rd_key0_data3_reg_t rd_key0_data3; 2355 volatile efuse_rd_key0_data4_reg_t rd_key0_data4; 2356 volatile efuse_rd_key0_data5_reg_t rd_key0_data5; 2357 volatile efuse_rd_key0_data6_reg_t rd_key0_data6; 2358 volatile efuse_rd_key0_data7_reg_t rd_key0_data7; 2359 volatile efuse_rd_key1_data0_reg_t rd_key1_data0; 2360 volatile efuse_rd_key1_data1_reg_t rd_key1_data1; 2361 volatile efuse_rd_key1_data2_reg_t rd_key1_data2; 2362 volatile efuse_rd_key1_data3_reg_t rd_key1_data3; 2363 volatile efuse_rd_key1_data4_reg_t rd_key1_data4; 2364 volatile efuse_rd_key1_data5_reg_t rd_key1_data5; 2365 volatile efuse_rd_key1_data6_reg_t rd_key1_data6; 2366 volatile efuse_rd_key1_data7_reg_t rd_key1_data7; 2367 volatile efuse_rd_key2_data0_reg_t rd_key2_data0; 2368 volatile efuse_rd_key2_data1_reg_t rd_key2_data1; 2369 volatile efuse_rd_key2_data2_reg_t rd_key2_data2; 2370 volatile efuse_rd_key2_data3_reg_t rd_key2_data3; 2371 volatile efuse_rd_key2_data4_reg_t rd_key2_data4; 2372 volatile efuse_rd_key2_data5_reg_t rd_key2_data5; 2373 volatile efuse_rd_key2_data6_reg_t rd_key2_data6; 2374 volatile efuse_rd_key2_data7_reg_t rd_key2_data7; 2375 volatile efuse_rd_key3_data0_reg_t rd_key3_data0; 2376 volatile efuse_rd_key3_data1_reg_t rd_key3_data1; 2377 volatile efuse_rd_key3_data2_reg_t rd_key3_data2; 2378 volatile efuse_rd_key3_data3_reg_t rd_key3_data3; 2379 volatile efuse_rd_key3_data4_reg_t rd_key3_data4; 2380 volatile efuse_rd_key3_data5_reg_t rd_key3_data5; 2381 volatile efuse_rd_key3_data6_reg_t rd_key3_data6; 2382 volatile efuse_rd_key3_data7_reg_t rd_key3_data7; 2383 volatile efuse_rd_key4_data0_reg_t rd_key4_data0; 2384 volatile efuse_rd_key4_data1_reg_t rd_key4_data1; 2385 volatile efuse_rd_key4_data2_reg_t rd_key4_data2; 2386 volatile efuse_rd_key4_data3_reg_t rd_key4_data3; 2387 volatile efuse_rd_key4_data4_reg_t rd_key4_data4; 2388 volatile efuse_rd_key4_data5_reg_t rd_key4_data5; 2389 volatile efuse_rd_key4_data6_reg_t rd_key4_data6; 2390 volatile efuse_rd_key4_data7_reg_t rd_key4_data7; 2391 volatile efuse_rd_key5_data0_reg_t rd_key5_data0; 2392 volatile efuse_rd_key5_data1_reg_t rd_key5_data1; 2393 volatile efuse_rd_key5_data2_reg_t rd_key5_data2; 2394 volatile efuse_rd_key5_data3_reg_t rd_key5_data3; 2395 volatile efuse_rd_key5_data4_reg_t rd_key5_data4; 2396 volatile efuse_rd_key5_data5_reg_t rd_key5_data5; 2397 volatile efuse_rd_key5_data6_reg_t rd_key5_data6; 2398 volatile efuse_rd_key5_data7_reg_t rd_key5_data7; 2399 volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0; 2400 volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1; 2401 volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2; 2402 volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3; 2403 volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4; 2404 volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5; 2405 volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6; 2406 volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7; 2407 volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0; 2408 volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1; 2409 volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2; 2410 volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3; 2411 volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4; 2412 uint32_t reserved_190[12]; 2413 volatile efuse_rd_rs_err0_reg_t rd_rs_err0; 2414 volatile efuse_rd_rs_err1_reg_t rd_rs_err1; 2415 volatile efuse_clk_reg_t clk; 2416 volatile efuse_conf_reg_t conf; 2417 volatile efuse_status_reg_t status; 2418 volatile efuse_cmd_reg_t cmd; 2419 volatile efuse_int_raw_reg_t int_raw; 2420 volatile efuse_int_st_reg_t int_st; 2421 volatile efuse_int_ena_reg_t int_ena; 2422 volatile efuse_int_clr_reg_t int_clr; 2423 volatile efuse_dac_conf_reg_t dac_conf; 2424 volatile efuse_rd_tim_conf_reg_t rd_tim_conf; 2425 volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1; 2426 volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2; 2427 volatile efuse_wr_tim_conf0_rs_bypass_reg_t wr_tim_conf0_rs_bypass; 2428 volatile efuse_date_reg_t date; 2429 } efuse_dev_t; 2430 2431 extern efuse_dev_t EFUSE; 2432 2433 #ifndef __cplusplus 2434 _Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure"); 2435 #endif 2436 2437 #ifdef __cplusplus 2438 } 2439 #endif 2440
