Searched refs:ref_cnt_rst (Results 1 – 12 of 12) sorted by relevance
150 dev->conf_ch[i].conf1.ref_cnt_rst = 1; in rmt_ll_tx_reset_channels_clock_div()321 dev->conf_ch[i].conf1.ref_cnt_rst = 1; in rmt_ll_rx_reset_channels_clock_div()
42 … uint32_t ref_cnt_rst: 1; /*This bit is used to reset divider in channel0-7.*/ member
795 volatile rmt_ref_cnt_rst_reg_t ref_cnt_rst; member
791 volatile rmt_ref_cnt_rst_reg_t ref_cnt_rst; member
238 } ref_cnt_rst; member
155 dev->ref_cnt_rst.val |= channel_mask & 0x0F; in rmt_ll_tx_reset_channels_clock_div()430 dev->ref_cnt_rst.val |= channel_mask & 0x0F; in rmt_ll_rx_reset_channels_clock_div()
157 dev->ref_cnt_rst.val |= channel_mask & 0x0F; in rmt_ll_tx_reset_channels_clock_div()461 dev->ref_cnt_rst.val |= ((channel_mask & 0x0F) << 4); in rmt_ll_rx_reset_channels_clock_div()
159 dev->ref_cnt_rst.val |= channel_mask & 0x03; in rmt_ll_tx_reset_channels_clock_div()451 dev->ref_cnt_rst.val |= ((channel_mask & 0x03) << 2); in rmt_ll_rx_reset_channels_clock_div()
157 dev->ref_cnt_rst.val |= channel_mask & 0x03; in rmt_ll_tx_reset_channels_clock_div()436 dev->ref_cnt_rst.val |= ((channel_mask & 0x03) << 2); in rmt_ll_rx_reset_channels_clock_div()
156 dev->ref_cnt_rst.val |= channel_mask & 0x03; in rmt_ll_tx_reset_channels_clock_div()448 dev->ref_cnt_rst.val |= ((channel_mask & 0x03) << 2); in rmt_ll_rx_reset_channels_clock_div()
1083 volatile rmt_ref_cnt_rst_reg_t ref_cnt_rst; member
