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Searched refs:psram (Results 1 – 9 of 9) sorted by relevance

/hal_espressif-latest/components/esp_psram/
DCMakeLists.txt40 target_compile_options(${COMPONENT_LIB} PUBLIC -mfix-esp32-psram-cache-issue)
42 target_link_libraries(${COMPONENT_LIB} PUBLIC -mfix-esp32-psram-cache-issue)
46 target_compile_options(${COMPONENT_LIB} PUBLIC -mfix-esp32-psram-cache-strategy=dupldst)
47 target_link_libraries(${COMPONENT_LIB} PUBLIC -mfix-esp32-psram-cache-strategy=dupldst)
50 target_compile_options(${COMPONENT_LIB} PUBLIC -mfix-esp32-psram-cache-strategy=memw)
51 target_link_libraries(${COMPONENT_LIB} PUBLIC -mfix-esp32-psram-cache-strategy=memw)
54 target_compile_options(${COMPONENT_LIB} PUBLIC -mfix-esp32-psram-cache-strategy=nops)
55 target_link_libraries(${COMPONENT_LIB} PUBLIC -mfix-esp32-psram-cache-strategy=nops)
Dproject_include.cmake6 idf_build_set_property(COMPILE_OPTIONS "-mfix-esp32-psram-cache-issue" APPEND)
9 idf_build_set_property(COMPILE_OPTIONS "-mfix-esp32-psram-cache-strategy=dupldst" APPEND)
12 idf_build_set_property(COMPILE_OPTIONS "-mfix-esp32-psram-cache-strategy=memw" APPEND)
15 idf_build_set_property(COMPILE_OPTIONS "-mfix-esp32-psram-cache-strategy=nops" APPEND)
DKconfig.spiram.common18 … Normally, if psram initialization is enabled during compile time but not found at runtime, it
/hal_espressif-latest/components/esp_psram/esp32/
Desp_psram_extram_cache.c29 volatile uint8_t *psram=(volatile uint8_t*)SOC_EXTRAM_DATA_LOW; in esp_psram_extram_writeback_cache() local
53 i+=psram[x]; in esp_psram_extram_writeback_cache()
63 i+=psram[x]; in esp_psram_extram_writeback_cache()
64 i+=psram[x+(1024*1024*2)]; in esp_psram_extram_writeback_cache()
DKconfig.spiram71 … fix in the compiler (-mfix-esp32-psram-cache-issue) that makes sure the specific code that is
247 … If spiram 2T mode is enabled, the size of 64Mbit psram will be changed as 32Mbit, so himem will be
301 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
310 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
321 …User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
330 …User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
344 … For ESP32-PICO chip, the psram share clock with flash, so user do not need to configure the clock
361 … ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. The psram only has QPI
/hal_espressif-latest/components/heap/
Dheap_trace_standalone.c60 static void heap_trace_dump_base(bool internal_ram, bool psram);
291 static void heap_trace_dump_base(bool internal_ram, bool psram) in heap_trace_dump_base() argument
315 ((psram && internal_ram) || in heap_trace_dump_base()
317 (psram && esp_ptr_external_ram(r_cur->address))); in heap_trace_dump_base()
/hal_espressif-latest/tools/esptool_py/esptool/targets/
Desp32s3.py231 psram = {
236 if psram is not None:
237 features += [psram + f" ({self.get_psram_vendor()})"]
/hal_espressif-latest/components/newlib/
Desp32-spiram-rom-functions-c.lf9 # and esp32-spiram-rom-functions-psram-workaround.lf is the archive name.
/hal_espressif-latest/tools/esptool_py/
DCHANGELOG.md107 - **xip_psram**: support xip psram feature on esp32p4
127 - **esptool**: Add PICO package for ESP32S3 and flash/psram efuses