1 /*
2 * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #pragma once
8
9 #include <stdbool.h>
10 #include "soc/memprot_defs.h"
11 #include "hal/memprot_types.h"
12
13 #ifdef __cplusplus
14 extern "C" {
15 #endif
16
17 /**
18 * ========================================================================================
19 * === PeriBus1 common
20 * ========================================================================================
21 */
memprot_ll_peri1_clear_intr(void)22 static inline void memprot_ll_peri1_clear_intr(void)
23 {
24 DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_DPORT_6_REG, DPORT_PMS_PRO_DPORT_ILG_CLR);
25 DPORT_CLEAR_PERI_REG_MASK(DPORT_PMS_PRO_DPORT_6_REG, DPORT_PMS_PRO_DPORT_ILG_CLR);
26 }
27
memprot_ll_peri1_get_intr_source_num(void)28 static inline uint32_t memprot_ll_peri1_get_intr_source_num(void)
29 {
30 return ETS_PMS_PRO_DPORT_ILG_INTR_SOURCE;
31 }
32
memprot_ll_peri1_intr_ena(bool enable)33 static inline void memprot_ll_peri1_intr_ena(bool enable)
34 {
35 if (enable) {
36 DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_DPORT_6_REG, DPORT_PMS_PRO_DPORT_ILG_EN);
37 } else {
38 DPORT_CLEAR_PERI_REG_MASK(DPORT_PMS_PRO_DPORT_6_REG, DPORT_PMS_PRO_DPORT_ILG_EN);
39 }
40 }
41
memprot_ll_peri1_get_ctrl_reg(void)42 static inline uint32_t memprot_ll_peri1_get_ctrl_reg(void)
43 {
44 return DPORT_READ_PERI_REG(DPORT_PMS_PRO_DPORT_6_REG);
45 }
46
memprot_ll_peri1_get_fault_reg(void)47 static inline uint32_t memprot_ll_peri1_get_fault_reg(void)
48 {
49 return DPORT_READ_PERI_REG(DPORT_PMS_PRO_DPORT_7_REG);
50 }
51
memprot_ll_peri1_get_fault_op_type(uint32_t * op_type,uint32_t * op_subtype)52 static inline void memprot_ll_peri1_get_fault_op_type(uint32_t *op_type, uint32_t *op_subtype)
53 {
54 uint32_t status_bits = memprot_ll_peri1_get_fault_reg();
55 //*op_type = (uint32_t)status_bits & PERI1_INTR_ST_OP_RW_BIT;
56 *op_type = 0;
57 //! DPORT_PMS_PRO_DPORT_7_REG is missing op_type bit
58 *op_subtype = (uint32_t)status_bits & PERI1_INTR_ST_OP_TYPE_BIT;
59 }
60
memprot_ll_peri1_is_assoc_intr(void)61 static inline bool memprot_ll_peri1_is_assoc_intr(void)
62 {
63 return DPORT_GET_PERI_REG_MASK(DPORT_PMS_PRO_DPORT_7_REG, DPORT_PMS_PRO_DPORT_ILG_INTR) > 0;
64 }
65
memprot_ll_peri1_get_intr_ena_bit(void)66 static inline uint32_t memprot_ll_peri1_get_intr_ena_bit(void)
67 {
68 return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DPORT_6_REG, DPORT_PMS_PRO_DPORT_ILG_EN);
69 }
70
memprot_ll_peri1_get_intr_on_bit(void)71 static inline uint32_t memprot_ll_peri1_get_intr_on_bit(void)
72 {
73 return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DPORT_6_REG, DPORT_PMS_PRO_DPORT_ILG_INTR);
74 }
75
memprot_ll_peri1_get_intr_clr_bit(void)76 static inline uint32_t memprot_ll_peri1_get_intr_clr_bit(void)
77 {
78 return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DPORT_6_REG, DPORT_PMS_PRO_DPORT_ILG_CLR);
79 }
80
memprot_ll_peri1_get_lock_reg(void)81 static inline uint32_t memprot_ll_peri1_get_lock_reg(void)
82 {
83 return DPORT_READ_PERI_REG(DPORT_PMS_PRO_DPORT_0_REG);
84 }
85
86 //resets automatically on CPU restart
memprot_ll_peri1_set_lock(void)87 static inline void memprot_ll_peri1_set_lock(void)
88 {
89 DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_DPORT_0_REG, DPORT_PMS_PRO_DPORT_LOCK);
90 }
91
memprot_ll_peri1_get_lock_bit(void)92 static inline uint32_t memprot_ll_peri1_get_lock_bit(void)
93 {
94 return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DPORT_0_REG, DPORT_PMS_PRO_DPORT_LOCK);
95 }
96
97 /**
98 * ========================================================================================
99 * === PeriBus1 RTC SLOW
100 * ========================================================================================
101 */
memprot_ll_peri1_rtcslow_get_fault_address(void)102 static inline intptr_t memprot_ll_peri1_rtcslow_get_fault_address(void)
103 {
104 uint32_t status_bits = memprot_ll_peri1_get_fault_reg();
105 uint32_t fault_address = (status_bits & PERI1_INTR_ST_FAULTADDR_M) >> PERI1_INTR_ST_FAULTADDR_S;
106 uint32_t high_bits = (status_bits & PERI1_INTR_ST_OP_HIGH_BITS) ? PERI1_RTCSLOW_INTR_ST_FAULTADDR_HI_0 : 0;
107 return (intptr_t)(fault_address | high_bits);
108 }
109
memprot_ll_peri1_rtcslow_is_intr_mine(void)110 static inline bool memprot_ll_peri1_rtcslow_is_intr_mine(void)
111 {
112 if (memprot_ll_dram0_is_assoc_intr()) {
113 uint32_t faulting_address = (uint32_t)memprot_ll_peri1_rtcslow_get_fault_address();
114 return faulting_address >= PERI1_RTCSLOW_ADDRESS_LOW && faulting_address <= PERI1_RTCSLOW_ADDRESS_HIGH;
115 }
116 return false;
117 }
118
memprot_ll_peri1_rtcslow_set_prot(uint32_t * split_addr,bool lw,bool lr,bool hw,bool hr)119 static inline memprot_hal_err_t memprot_ll_peri1_rtcslow_set_prot(uint32_t *split_addr, bool lw, bool lr, bool hw, bool hr)
120 {
121 uint32_t addr = (uint32_t)split_addr;
122
123 //check corresponding range fit & aligment to 32bit boundaries
124 if (addr < PERI1_RTCSLOW_ADDRESS_LOW || addr > PERI1_RTCSLOW_ADDRESS_HIGH) {
125 return MEMP_HAL_ERR_SPLIT_ADDR_INVALID;
126 }
127 if (addr % 0x4 != 0) {
128 return MEMP_HAL_ERR_SPLIT_ADDR_UNALIGNED;
129 }
130
131 uint32_t reg_split_addr = PERI1_RTCSLOW_ADDR_TO_CONF_REG(addr);
132
133 //prepare high & low permission mask
134 uint32_t permission_mask = 0;
135 if (lw) {
136 permission_mask |= DPORT_PMS_PRO_DPORT_RTCSLOW_L_W;
137 }
138 if (lr) {
139 permission_mask |= DPORT_PMS_PRO_DPORT_RTCSLOW_L_R;
140 }
141 if (hw) {
142 permission_mask |= DPORT_PMS_PRO_DPORT_RTCSLOW_H_W;
143 }
144 if (hr) {
145 permission_mask |= DPORT_PMS_PRO_DPORT_RTCSLOW_H_R;
146 }
147
148 //write PERIBUS1 RTC SLOW cfg register
149 DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_DPORT_1_REG, reg_split_addr | permission_mask);
150
151 return MEMP_HAL_OK;
152 }
153
memprot_ll_peri1_rtcslow_get_split_sgnf_bits(bool * lw,bool * lr,bool * hw,bool * hr)154 static inline void memprot_ll_peri1_rtcslow_get_split_sgnf_bits(bool *lw, bool *lr, bool *hw, bool *hr)
155 {
156 *lw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DPORT_1_REG, DPORT_PMS_PRO_DPORT_RTCSLOW_L_W);
157 *lr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DPORT_1_REG, DPORT_PMS_PRO_DPORT_RTCSLOW_L_R);
158 *hw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DPORT_1_REG, DPORT_PMS_PRO_DPORT_RTCSLOW_H_W);
159 *hr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DPORT_1_REG, DPORT_PMS_PRO_DPORT_RTCSLOW_H_R);
160 }
161
memprot_ll_peri1_rtcslow_set_read_perm(bool lr,bool hr)162 static inline void memprot_ll_peri1_rtcslow_set_read_perm(bool lr, bool hr)
163 {
164 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DPORT_1_REG, DPORT_PMS_PRO_DPORT_RTCSLOW_L_R, lr ? 1 : 0);
165 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DPORT_1_REG, DPORT_PMS_PRO_DPORT_RTCSLOW_H_R, hr ? 1 : 0);
166 }
167
memprot_ll_peri1_rtcslow_set_write_perm(bool lw,bool hw)168 static inline void memprot_ll_peri1_rtcslow_set_write_perm(bool lw, bool hw)
169 {
170 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DPORT_1_REG, DPORT_PMS_PRO_DPORT_RTCSLOW_L_W, lw ? 1 : 0);
171 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DPORT_1_REG, DPORT_PMS_PRO_DPORT_RTCSLOW_H_W, hw ? 1 : 0);
172 }
173
memprot_ll_peri1_rtcslow_get_conf_reg(void)174 static inline uint32_t memprot_ll_peri1_rtcslow_get_conf_reg(void)
175 {
176 return DPORT_READ_PERI_REG(DPORT_PMS_PRO_DPORT_1_REG);
177 }
178
179 /**
180 * ========================================================================================
181 * === PeriBus2 common
182 * ========================================================================================
183 */
memprot_ll_peri2_clear_intr(void)184 static inline void memprot_ll_peri2_clear_intr(void)
185 {
186 DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_AHB_3_REG, DPORT_PMS_PRO_AHB_ILG_CLR);
187 DPORT_CLEAR_PERI_REG_MASK(DPORT_PMS_PRO_AHB_3_REG, DPORT_PMS_PRO_AHB_ILG_CLR);
188 }
189
memprot_ll_peri2_get_intr_source_num(void)190 static inline uint32_t memprot_ll_peri2_get_intr_source_num(void)
191 {
192 return ETS_PMS_PRO_AHB_ILG_INTR_SOURCE;
193 }
194
memprot_ll_peri2_intr_ena(bool enable)195 static inline void memprot_ll_peri2_intr_ena(bool enable)
196 {
197 if (enable) {
198 DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_AHB_3_REG, DPORT_PMS_PRO_AHB_ILG_EN);
199 } else {
200 DPORT_CLEAR_PERI_REG_MASK(DPORT_PMS_PRO_AHB_3_REG, DPORT_PMS_PRO_AHB_ILG_EN);
201 }
202 }
203
memprot_ll_peri2_get_ctrl_reg(void)204 static inline uint32_t memprot_ll_peri2_get_ctrl_reg(void)
205 {
206 return DPORT_READ_PERI_REG(DPORT_PMS_PRO_AHB_3_REG);
207 }
208
memprot_ll_peri2_get_fault_reg(void)209 static inline uint32_t memprot_ll_peri2_get_fault_reg(void)
210 {
211 return DPORT_READ_PERI_REG(DPORT_PMS_PRO_AHB_4_REG);
212 }
213
memprot_ll_peri2_get_fault_op_type(uint32_t * op_type,uint32_t * op_subtype)214 static inline void memprot_ll_peri2_get_fault_op_type(uint32_t *op_type, uint32_t *op_subtype)
215 {
216 uint32_t status_bits = memprot_ll_peri2_get_fault_reg();
217 *op_type = (uint32_t)status_bits & PERI2_INTR_ST_OP_RW_BIT;
218 *op_subtype = (uint32_t)status_bits & PERI2_INTR_ST_OP_TYPE_BIT;
219 }
220
memprot_ll_peri2_is_assoc_intr(void)221 static inline bool memprot_ll_peri2_is_assoc_intr(void)
222 {
223 return DPORT_GET_PERI_REG_MASK(DPORT_PMS_PRO_AHB_3_REG, DPORT_PMS_PRO_AHB_ILG_INTR) > 0;
224 }
225
memprot_ll_peri2_get_intr_ena_bit(void)226 static inline uint32_t memprot_ll_peri2_get_intr_ena_bit(void)
227 {
228 return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_3_REG, DPORT_PMS_PRO_AHB_ILG_EN);
229 }
230
memprot_ll_peri2_get_intr_on_bit(void)231 static inline uint32_t memprot_ll_peri2_get_intr_on_bit(void)
232 {
233 return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_3_REG, DPORT_PMS_PRO_AHB_ILG_INTR);
234 }
235
memprot_ll_peri2_get_intr_clr_bit(void)236 static inline uint32_t memprot_ll_peri2_get_intr_clr_bit(void)
237 {
238 return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_3_REG, DPORT_PMS_PRO_AHB_ILG_CLR);
239 }
240
memprot_ll_peri2_get_lock_reg(void)241 static inline uint32_t memprot_ll_peri2_get_lock_reg(void)
242 {
243 return DPORT_READ_PERI_REG(DPORT_PMS_PRO_AHB_0_REG);
244 }
245
246 //resets automatically on CPU restart
memprot_ll_peri2_set_lock(void)247 static inline void memprot_ll_peri2_set_lock(void)
248 {
249 DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_AHB_0_REG, DPORT_PMS_PRO_AHB_LOCK);
250 }
251
memprot_ll_peri2_get_lock_bit(void)252 static inline uint32_t memprot_ll_peri2_get_lock_bit(void)
253 {
254 return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_0_REG, DPORT_PMS_PRO_AHB_LOCK);
255 }
256
memprot_ll_peri2_rtcslow_get_fault_address(void)257 static inline intptr_t memprot_ll_peri2_rtcslow_get_fault_address(void)
258 {
259 uint32_t status_bits = memprot_ll_peri2_get_fault_reg();
260 return (intptr_t)(status_bits & PERI2_INTR_ST_FAULTADDR_M);
261 }
262
263 /**
264 * ========================================================================================
265 * === PeriBus2 RTC SLOW 0 (AHB0)
266 * ========================================================================================
267 */
memprot_ll_peri2_rtcslow_0_is_intr_mine(void)268 static inline bool memprot_ll_peri2_rtcslow_0_is_intr_mine(void)
269 {
270 if (memprot_ll_peri2_is_assoc_intr()) {
271 uint32_t faulting_address = (uint32_t)memprot_ll_peri2_rtcslow_get_fault_address();
272 return faulting_address >= PERI2_RTCSLOW_0_ADDRESS_LOW && faulting_address <= PERI2_RTCSLOW_0_ADDRESS_HIGH;
273 }
274 return false;
275 }
276
memprot_ll_peri2_rtcslow_0_set_prot(uint32_t * split_addr,bool lw,bool lr,bool lx,bool hw,bool hr,bool hx)277 static inline memprot_hal_err_t memprot_ll_peri2_rtcslow_0_set_prot(uint32_t *split_addr, bool lw, bool lr, bool lx, bool hw, bool hr, bool hx)
278 {
279 uint32_t addr = (uint32_t)split_addr;
280
281 //check corresponding range fit & aligment to 32bit boundaries
282 if (addr < PERI2_RTCSLOW_0_ADDRESS_LOW || addr > PERI2_RTCSLOW_0_ADDRESS_HIGH) {
283 return MEMP_HAL_ERR_SPLIT_ADDR_INVALID;
284 }
285 if (addr % 0x4 != 0) {
286 return MEMP_HAL_ERR_SPLIT_ADDR_UNALIGNED;
287 }
288
289 uint32_t reg_split_addr = PERI2_RTCSLOW_0_ADDR_TO_CONF_REG(addr);
290
291 //prepare high & low permission mask
292 uint32_t permission_mask = 0;
293 if (lw) {
294 permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_0_L_W;
295 }
296 if (lr) {
297 permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_0_L_R;
298 }
299 if (lx) {
300 permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_0_L_F;
301 }
302 if (hw) {
303 permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_0_H_W;
304 }
305 if (hr) {
306 permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_0_H_R;
307 }
308 if (hx) {
309 permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_0_H_F;
310 }
311
312 //write PERIBUS1 RTC SLOW cfg register
313 DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_AHB_1_REG, reg_split_addr | permission_mask);
314
315 return MEMP_HAL_OK;
316 }
317
memprot_ll_peri2_rtcslow_0_get_split_sgnf_bits(bool * lw,bool * lr,bool * lx,bool * hw,bool * hr,bool * hx)318 static inline void memprot_ll_peri2_rtcslow_0_get_split_sgnf_bits(bool *lw, bool *lr, bool *lx, bool *hw, bool *hr, bool *hx)
319 {
320 *lw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_L_W);
321 *lr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_L_R);
322 *lx = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_L_F);
323 *hw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_H_W);
324 *hr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_H_R);
325 *hx = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_H_F);
326 }
327
memprot_ll_peri2_rtcslow_0_set_read_perm(bool lr,bool hr)328 static inline void memprot_ll_peri2_rtcslow_0_set_read_perm(bool lr, bool hr)
329 {
330 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_L_R, lr ? 1 : 0);
331 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_H_R, hr ? 1 : 0);
332 }
333
memprot_ll_peri2_rtcslow_0_set_write_perm(bool lw,bool hw)334 static inline void memprot_ll_peri2_rtcslow_0_set_write_perm(bool lw, bool hw)
335 {
336 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_L_W, lw ? 1 : 0);
337 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_H_W, hw ? 1 : 0);
338 }
339
memprot_ll_peri2_rtcslow_0_set_exec_perm(bool lx,bool hx)340 static inline void memprot_ll_peri2_rtcslow_0_set_exec_perm(bool lx, bool hx)
341 {
342 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_L_F, lx ? 1 : 0);
343 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_H_F, hx ? 1 : 0);
344 }
345
memprot_ll_peri2_rtcslow_0_get_conf_reg(void)346 static inline uint32_t memprot_ll_peri2_rtcslow_0_get_conf_reg(void)
347 {
348 return DPORT_READ_PERI_REG(DPORT_PMS_PRO_DPORT_1_REG);
349 }
350
351 /**
352 * ========================================================================================
353 * === PeriBus2 RTC SLOW 1 (AHB1)
354 * ========================================================================================
355 */
memprot_ll_peri2_rtcslow_1_is_intr_mine(void)356 static inline bool memprot_ll_peri2_rtcslow_1_is_intr_mine(void)
357 {
358 if (memprot_ll_peri2_is_assoc_intr()) {
359 uint32_t faulting_address = (uint32_t)memprot_ll_peri2_rtcslow_get_fault_address();
360 return faulting_address >= PERI2_RTCSLOW_1_ADDRESS_LOW && faulting_address <= PERI2_RTCSLOW_1_ADDRESS_HIGH;
361 }
362 return false;
363 }
364
memprot_ll_peri2_rtcslow_1_set_prot(uint32_t * split_addr,bool lw,bool lr,bool lx,bool hw,bool hr,bool hx)365 static inline memprot_hal_err_t memprot_ll_peri2_rtcslow_1_set_prot(uint32_t *split_addr, bool lw, bool lr, bool lx, bool hw, bool hr, bool hx)
366 {
367 uint32_t addr = (uint32_t)split_addr;
368
369 //check corresponding range fit & aligment to 32bit boundaries
370 if (addr < PERI2_RTCSLOW_1_ADDRESS_LOW || addr > PERI2_RTCSLOW_1_ADDRESS_HIGH) {
371 return MEMP_HAL_ERR_SPLIT_ADDR_INVALID;
372 }
373 if (addr % 0x4 != 0) {
374 return MEMP_HAL_ERR_SPLIT_ADDR_UNALIGNED;
375 }
376
377 uint32_t reg_split_addr = PERI2_RTCSLOW_1_ADDR_TO_CONF_REG(addr);
378
379 //prepare high & low permission mask
380 uint32_t permission_mask = 0;
381 if (lw) {
382 permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_1_L_W;
383 }
384 if (lr) {
385 permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_1_L_R;
386 }
387 if (lx) {
388 permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_1_L_F;
389 }
390 if (hw) {
391 permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_1_H_W;
392 }
393 if (hr) {
394 permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_1_H_R;
395 }
396 if (hx) {
397 permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_1_H_F;
398 }
399
400 //write PERIBUS1 RTC SLOW cfg register
401 DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_AHB_2_REG, reg_split_addr | permission_mask);
402
403 return MEMP_HAL_OK;
404 }
405
memprot_ll_peri2_rtcslow_1_get_split_sgnf_bits(bool * lw,bool * lr,bool * lx,bool * hw,bool * hr,bool * hx)406 static inline void memprot_ll_peri2_rtcslow_1_get_split_sgnf_bits(bool *lw, bool *lr, bool *lx, bool *hw, bool *hr, bool *hx)
407 {
408 *lw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_L_W);
409 *lr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_L_R);
410 *lx = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_L_F);
411 *hw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_H_W);
412 *hr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_H_R);
413 *hx = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_H_F);
414 }
415
memprot_ll_peri2_rtcslow_1_set_read_perm(bool lr,bool hr)416 static inline void memprot_ll_peri2_rtcslow_1_set_read_perm(bool lr, bool hr)
417 {
418 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_L_R, lr ? 1 : 0);
419 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_H_R, hr ? 1 : 0);
420 }
421
memprot_ll_peri2_rtcslow_1_set_write_perm(bool lw,bool hw)422 static inline void memprot_ll_peri2_rtcslow_1_set_write_perm(bool lw, bool hw)
423 {
424 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_L_W, lw ? 1 : 0);
425 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_H_W, hw ? 1 : 0);
426 }
427
memprot_ll_peri2_rtcslow_1_set_exec_perm(bool lx,bool hx)428 static inline void memprot_ll_peri2_rtcslow_1_set_exec_perm(bool lx, bool hx)
429 {
430 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_L_F, lx ? 1 : 0);
431 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_H_F, hx ? 1 : 0);
432 }
433
memprot_ll_peri2_rtcslow_1_get_conf_reg(void)434 static inline uint32_t memprot_ll_peri2_rtcslow_1_get_conf_reg(void)
435 {
436 return DPORT_READ_PERI_REG(DPORT_PMS_PRO_DPORT_2_REG);
437 }
438
439 #ifdef __cplusplus
440 }
441 #endif
442
