1 /*
2 * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/kernel.h>
8 #include <zephyr/drivers/timer/system_timer.h>
9
10 #include <stddef.h>
11 #include <string.h>
12 #include <sys/lock.h>
13 #include <sys/param.h>
14
15 #include "esp_attr.h"
16 #include "esp_memory_utils.h"
17 #include "esp_sleep.h"
18 #include "esp_private/esp_sleep_internal.h"
19 #include "esp_private/esp_timer_private.h"
20 #include "esp_private/sleep_event.h"
21 #include "esp_private/system_internal.h"
22 #include "esp_log.h"
23 #include "esp_cpu.h"
24 #include "esp_timer.h"
25 #include "soc/soc_caps.h"
26 #include "driver/rtc_io.h"
27 #include "hal/rtc_io_hal.h"
28
29 #if SOC_SLEEP_SYSTIMER_STALL_WORKAROUND
30 #include "hal/systimer_ll.h"
31 #endif
32
33 #if SOC_SLEEP_TGWDT_STOP_WORKAROUND
34 #include "hal/mwdt_ll.h"
35 #include "hal/timer_ll.h"
36 #endif
37
38 #if SOC_PM_SUPPORT_PMU_MODEM_STATE
39 #include "esp_private/pm_impl.h"
40 #endif
41
42 #if SOC_LP_AON_SUPPORTED
43 #include "hal/lp_aon_hal.h"
44 #else
45 #include "hal/rtc_cntl_ll.h"
46 #include "hal/rtc_hal.h"
47 #endif
48
49 #include "driver/uart.h"
50
51 #include "soc/rtc.h"
52 #include "soc/soc_caps.h"
53 #include "regi2c_ctrl.h" //For `REGI2C_ANA_CALI_PD_WORKAROUND`, temp
54
55 #include "hal/cache_hal.h"
56 #include "hal/wdt_hal.h"
57 #include "hal/uart_hal.h"
58 #if SOC_TOUCH_SENSOR_SUPPORTED
59 #include "hal/touch_sensor_hal.h"
60 #include "driver/touch_sensor.h"
61 #include "driver/touch_sensor_common.h"
62 #endif
63 #include "hal/clk_gate_ll.h"
64
65 #include "sdkconfig.h"
66 #include "esp_rom_uart.h"
67 #include "esp_rom_sys.h"
68 #include "esp_private/brownout.h"
69 #include "esp_private/sleep_console.h"
70 #include "esp_private/sleep_cpu.h"
71 #include "esp_private/sleep_modem.h"
72 #include "esp_private/esp_clk.h"
73 #include "esp_private/esp_task_wdt.h"
74 #include "esp_private/spi_flash_os.h"
75 #include "esp_private/sar_periph_ctrl.h"
76
77 #ifdef CONFIG_IDF_TARGET_ESP32
78 #include "esp32/rom/cache.h"
79 #include "esp32/rom/rtc.h"
80 #include "esp_private/gpio.h"
81 #include "esp_private/sleep_gpio.h"
82 #elif CONFIG_IDF_TARGET_ESP32S2
83 #include "esp32s2/rom/rtc.h"
84 #include "soc/extmem_reg.h"
85 #include "esp_private/gpio.h"
86 #elif CONFIG_IDF_TARGET_ESP32S3
87 #include "esp32s3/rom/rtc.h"
88 #include "esp_private/mspi_timing_tuning.h"
89 #elif CONFIG_IDF_TARGET_ESP32C3
90 #include "esp32c3/rom/rtc.h"
91 #elif CONFIG_IDF_TARGET_ESP32C2
92 #include "esp32c2/rom/rtc.h"
93 #elif CONFIG_IDF_TARGET_ESP32C6
94 #include "esp32c6/rom/rtc.h"
95 #include "hal/gpio_ll.h"
96 #elif CONFIG_IDF_TARGET_ESP32H2
97 #include "esp32h2/rom/rtc.h"
98 #include "esp32h2/rom/cache.h"
99 #include "esp32h2/rom/rtc.h"
100 #include "soc/extmem_reg.h"
101 #include "hal/gpio_ll.h"
102 #endif
103
104 #if SOC_LP_TIMER_SUPPORTED
105 #include "hal/lp_timer_hal.h"
106 #endif
107
108 #if SOC_PMU_SUPPORTED
109 #include "esp_private/esp_pmu.h"
110 #include "esp_private/sleep_sys_periph.h"
111 #include "esp_private/sleep_clock.h"
112 #endif
113
114 #if SOC_PM_RETENTION_SW_TRIGGER_REGDMA
115 #include "esp_private/sleep_retention.h"
116 #endif
117
118 #if (CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND) && !CONFIG_IDF_TARGET_ESP32H2
119 #include "hal/cache_hal.h"
120 #endif
121
122 // If light sleep time is less than that, don't power down flash
123 #define FLASH_PD_MIN_SLEEP_TIME_US 2000
124
125 // Default waiting time for the software to wait for Flash ready after waking up from sleep
126 #define ESP_SLEEP_WAIT_FLASH_READY_DEFAULT_DELAY_US 700
127
128 // Cycles for RTC Timer clock source (internal oscillator) calibrate
129 #define RTC_CLK_SRC_CAL_CYCLES (10)
130 #define FAST_CLK_SRC_CAL_CYCLES (2048) /* ~ 127.4 us */
131
132 #ifdef CONFIG_IDF_TARGET_ESP32
133 #define DEFAULT_SLEEP_OUT_OVERHEAD_US (212)
134 #define DEFAULT_HARDWARE_OUT_OVERHEAD_US (60)
135 #elif CONFIG_IDF_TARGET_ESP32S2
136 #define DEFAULT_SLEEP_OUT_OVERHEAD_US (147)
137 #define DEFAULT_HARDWARE_OUT_OVERHEAD_US (28)
138 #elif CONFIG_IDF_TARGET_ESP32S3
139 #define DEFAULT_SLEEP_OUT_OVERHEAD_US (382)
140 #define DEFAULT_HARDWARE_OUT_OVERHEAD_US (133)
141 #elif CONFIG_IDF_TARGET_ESP32C3
142 #define DEFAULT_SLEEP_OUT_OVERHEAD_US (105)
143 #define DEFAULT_HARDWARE_OUT_OVERHEAD_US (37)
144 #elif CONFIG_IDF_TARGET_ESP32C2
145 #define DEFAULT_SLEEP_OUT_OVERHEAD_US (118)
146 #define DEFAULT_HARDWARE_OUT_OVERHEAD_US (9)
147 #elif CONFIG_IDF_TARGET_ESP32C6
148 #define DEFAULT_SLEEP_OUT_OVERHEAD_US (318)
149 #define DEFAULT_HARDWARE_OUT_OVERHEAD_US (56)
150 #elif CONFIG_IDF_TARGET_ESP32H2
151 #define DEFAULT_SLEEP_OUT_OVERHEAD_US (118)// TODO: IDF-6267
152 #define DEFAULT_HARDWARE_OUT_OVERHEAD_US (9)
153 #endif
154
155 // Actually costs 80us, using the fastest slow clock 150K calculation takes about 16 ticks
156 #define SLEEP_TIMER_ALARM_TO_SLEEP_TICKS (16)
157
158 #define SLEEP_UART_FLUSH_DONE_TO_SLEEP_US (450)
159
160 #if SOC_PM_SUPPORT_TOP_PD
161 // IDF console uses 8 bits data mode without parity, so each char occupy 8(data)+1(start)+1(stop)=10bits
162 #define UART_FLUSH_US_PER_CHAR (10*1000*1000 / CONFIG_ESP_CONSOLE_UART_BAUDRATE)
163 #define CONCATENATE_HELPER(x, y) (x##y)
164 #define CONCATENATE(x, y) CONCATENATE_HELPER(x, y)
165 #define CONSOLE_UART_DEV (&CONCATENATE(UART, CONFIG_ESP_CONSOLE_UART_NUM))
166 #endif
167
168 #define LIGHT_SLEEP_TIME_OVERHEAD_US DEFAULT_HARDWARE_OUT_OVERHEAD_US
169 #ifdef CONFIG_ESP_SYSTEM_RTC_EXT_XTAL
170 #define DEEP_SLEEP_TIME_OVERHEAD_US (650 + 100 * 240 / CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ)
171 #else
172 #define DEEP_SLEEP_TIME_OVERHEAD_US (250 + 100 * 240 / CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ)
173 #endif
174
175 // Minimal amount of time we can sleep for
176 #define LIGHT_SLEEP_MIN_TIME_US 200
177
178 #define RTC_MODULE_SLEEP_PREPARE_CYCLES (6)
179
180 #define CHECK_SOURCE(source, value, mask) ((s_config.wakeup_triggers & mask) && \
181 (source == value))
182
183 #define MAX_DSLP_HOOKS 3
184
185 static esp_deep_sleep_cb_t s_dslp_cb[MAX_DSLP_HOOKS] = {0};
186 static esp_deep_sleep_cb_t s_dslp_phy_cb[MAX_DSLP_HOOKS] = {0};
187
188 /**
189 * Internal structure which holds all requested deep sleep parameters
190 */
191 typedef struct {
192 struct {
193 esp_sleep_pd_option_t pd_option;
194 int16_t refs;
195 uint16_t reserved; /* reserved for 4 bytes aligned */
196 } domain[ESP_PD_DOMAIN_MAX];
197 int lock;
198 uint64_t sleep_duration;
199 uint32_t wakeup_triggers : 15;
200 #if SOC_PM_SUPPORT_EXT1_WAKEUP
201 uint32_t ext1_trigger_mode : 22; // 22 is the maximum RTCIO number in all chips
202 uint32_t ext1_rtc_gpio_mask : 22;
203 #endif
204 #if SOC_PM_SUPPORT_EXT0_WAKEUP
205 uint32_t ext0_trigger_level : 1;
206 uint32_t ext0_rtc_gpio_num : 5;
207 #endif
208 #if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
209 uint32_t gpio_wakeup_mask : 8; // 8 is the maximum RTCIO number in all chips that support GPIO wakeup
210 uint32_t gpio_trigger_mode : 8;
211 #endif
212 uint32_t sleep_time_adjustment;
213 uint32_t ccount_ticks_record;
214 uint32_t sleep_time_overhead_out;
215 uint32_t rtc_clk_cal_period;
216 uint32_t fast_clk_cal_period;
217 uint64_t rtc_ticks_at_sleep_start;
218 } sleep_config_t;
219
220
221 #if CONFIG_ESP_SLEEP_DEBUG
222 static esp_sleep_context_t *s_sleep_ctx = NULL;
223
esp_sleep_set_sleep_context(esp_sleep_context_t * sleep_ctx)224 void esp_sleep_set_sleep_context(esp_sleep_context_t *sleep_ctx)
225 {
226 s_sleep_ctx = sleep_ctx;
227 }
228 #endif
229
230 static uint32_t s_lightsleep_cnt = 0;
231
232 _Static_assert(22 >= SOC_RTCIO_PIN_COUNT, "Chip has more RTCIOs than 22, should increase ext1_rtc_gpio_mask field size");
233
234 static sleep_config_t s_config = {
235 .domain = {
236 [0 ... ESP_PD_DOMAIN_MAX - 1] = {
237 .pd_option = ESP_PD_OPTION_AUTO,
238 .refs = 0
239 }
240 },
241 .ccount_ticks_record = 0,
242 .sleep_time_overhead_out = DEFAULT_SLEEP_OUT_OVERHEAD_US,
243 .wakeup_triggers = 0
244 };
245
246 /* Internal variable used to track if light sleep wakeup sources are to be
247 expected when determining wakeup cause. */
248 static bool s_light_sleep_wakeup = false;
249
250 /* Updating RTC_MEMORY_CRC_REG register via set_rtc_memory_crc()
251 is not thread-safe, so we need to disable interrupts before going to deep sleep. */
252 static int spinlock_rtc_deep_sleep;
253 #define RTC_DEEP_SLEEP_ENTER_CRITICAL() do { spinlock_rtc_deep_sleep = irq_lock(); } while(0)
254 #define RTC_DEEP_SLEEP_EXIT_CRITICAL() irq_unlock(spinlock_rtc_deep_sleep);
255
256 static const char *TAG = "sleep";
257 static RTC_FAST_ATTR bool s_adc_tsen_enabled = false;
258 //in this mode, 2uA is saved, but RTC memory can't use at high temperature, and RTCIO can't be used as INPUT.
259 static bool s_ultra_low_enabled = false;
260
261 static bool s_periph_use_8m_flag = false;
262
esp_sleep_periph_use_8m(bool use_or_not)263 void esp_sleep_periph_use_8m(bool use_or_not)
264 {
265 s_periph_use_8m_flag = use_or_not;
266 }
267
268 static uint32_t get_power_down_flags(void);
269 #if SOC_PM_SUPPORT_EXT0_WAKEUP
270 static void ext0_wakeup_prepare(void);
271 #endif
272 #if SOC_PM_SUPPORT_EXT1_WAKEUP
273 static void ext1_wakeup_prepare(void);
274 #endif
275 static esp_err_t timer_wakeup_prepare(int64_t sleep_duration);
276 #if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
277 static void touch_wakeup_prepare(void);
278 #endif
279 #if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
280 static void gpio_deep_sleep_wakeup_prepare(void);
281 #endif
282
283 #if SOC_RTC_FAST_MEM_SUPPORTED
284 #if SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
285 static RTC_FAST_ATTR esp_deep_sleep_wake_stub_fn_t wake_stub_fn_handler = NULL;
286
esp_wake_stub_start(void)287 static void RTC_IRAM_ATTR __attribute__((used, noinline)) esp_wake_stub_start(void)
288 {
289 if (wake_stub_fn_handler) {
290 (*wake_stub_fn_handler)();
291 }
292 }
293
294 /* We must have a default deep sleep wake stub entry function, which must be
295 * located at the start address of the RTC fast memory, and its implementation
296 * must be simple enough to ensure that there is no litteral data before the
297 * wake stub entry, otherwise, the litteral data before the wake stub entry
298 * will not be CRC checked. */
esp_wake_stub_entry(void)299 static void __attribute__((section(".rtc.entry.text"))) esp_wake_stub_entry(void)
300 {
301 #define _SYM2STR(s) # s
302 #define SYM2STR(s) _SYM2STR(s)
303
304 #ifdef __riscv
305 __asm__ __volatile__ (
306 "addi sp, sp, -16 \n"
307 "sw ra, 0(sp) \n"
308 "jal ra, " SYM2STR(esp_wake_stub_start) "\n"
309 "lw ra, 0(sp) \n"
310 "addi sp, sp, 16 \n"
311 );
312 #else
313 // call4 has a larger effective addressing range (-524284 to 524288 bytes),
314 // which is sufficient for instruction addressing in RTC fast memory.
315 __asm__ __volatile__ ("call4 " SYM2STR(esp_wake_stub_start) "\n");
316 #endif
317
318 }
319
esp_set_deep_sleep_wake_stub_default_entry(void)320 void RTC_IRAM_ATTR esp_set_deep_sleep_wake_stub_default_entry(void)
321 {
322 extern char _rtc_text_start[];
323 #if CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM
324 extern char _rtc_noinit_end[];
325 size_t rtc_fast_length = (size_t)_rtc_noinit_end - (size_t)_rtc_text_start;
326 #else
327 extern char _rtc_force_fast_end[];
328 size_t rtc_fast_length = (size_t)_rtc_force_fast_end - (size_t)_rtc_text_start;
329 #endif
330 esp_rom_set_rtc_wake_addr((esp_rom_wake_func_t)esp_wake_stub_entry, rtc_fast_length);
331 }
332 #endif // SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
333
334 /* Wake from deep sleep stub
335 See esp_deepsleep.h esp_wake_deep_sleep() comments for details.
336 */
esp_get_deep_sleep_wake_stub(void)337 esp_deep_sleep_wake_stub_fn_t esp_get_deep_sleep_wake_stub(void)
338 {
339 #if SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
340 esp_deep_sleep_wake_stub_fn_t stub_ptr = wake_stub_fn_handler;
341 #else
342 esp_deep_sleep_wake_stub_fn_t stub_ptr = (esp_deep_sleep_wake_stub_fn_t) REG_READ(RTC_ENTRY_ADDR_REG);
343 #endif
344 if (!esp_ptr_executable(stub_ptr)) {
345 return NULL;
346 }
347 return stub_ptr;
348 }
349
350 #if CONFIG_IDF_TARGET_ESP32
351 /* APP core of esp32 can't access to RTC FAST MEMORY, do not define it with RTC_IRAM_ATTR */
352 void
353 #else
354 void RTC_IRAM_ATTR
355 #endif
esp_set_deep_sleep_wake_stub(esp_deep_sleep_wake_stub_fn_t new_stub)356 esp_set_deep_sleep_wake_stub(esp_deep_sleep_wake_stub_fn_t new_stub)
357 {
358 #if SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
359 wake_stub_fn_handler = new_stub;
360 #else
361 REG_WRITE(RTC_ENTRY_ADDR_REG, (uint32_t)new_stub);
362 #endif
363 }
364
esp_default_wake_deep_sleep(void)365 void RTC_IRAM_ATTR esp_default_wake_deep_sleep(void)
366 {
367 /* Clear MMU for CPU 0 */
368 #if CONFIG_IDF_TARGET_ESP32
369 _DPORT_REG_WRITE(DPORT_PRO_CACHE_CTRL1_REG,
370 _DPORT_REG_READ(DPORT_PRO_CACHE_CTRL1_REG) | DPORT_PRO_CACHE_MMU_IA_CLR);
371 _DPORT_REG_WRITE(DPORT_PRO_CACHE_CTRL1_REG,
372 _DPORT_REG_READ(DPORT_PRO_CACHE_CTRL1_REG) & (~DPORT_PRO_CACHE_MMU_IA_CLR));
373 #if CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY > 0
374 // ROM code has not started yet, so we need to set delay factor
375 // used by esp_rom_delay_us first.
376 ets_update_cpu_frequency_rom(ets_get_detected_xtal_freq() / 1000000);
377 // Time from VDD_SDIO power up to first flash read in ROM code is 700 us,
378 // for some flash chips is not sufficient, this delay is configured in menuconfig,
379 // it can be used to give the flash chip some extra time to become ready.
380 // For later chips, we have EFUSE_FLASH_TPUW field to configure it and do
381 // this delay in the ROM.
382 esp_rom_delay_us(CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY);
383 #endif
384 #elif CONFIG_IDF_TARGET_ESP32S2
385 REG_SET_BIT(EXTMEM_CACHE_DBG_INT_ENA_REG, EXTMEM_CACHE_DBG_EN);
386 #endif
387 }
388
389 void __attribute__((weak, alias("esp_default_wake_deep_sleep"))) esp_wake_deep_sleep(void);
390 #endif // SOC_RTC_FAST_MEM_SUPPORTED
391
esp_deep_sleep(uint64_t time_in_us)392 void esp_deep_sleep(uint64_t time_in_us)
393 {
394 esp_sleep_enable_timer_wakeup(time_in_us);
395 esp_deep_sleep_start();
396 }
397
esp_deep_sleep_try(uint64_t time_in_us)398 esp_err_t esp_deep_sleep_try(uint64_t time_in_us)
399 {
400 esp_sleep_enable_timer_wakeup(time_in_us);
401 return esp_deep_sleep_try_to_start();
402 }
403
s_sleep_hook_register(esp_deep_sleep_cb_t new_cb,esp_deep_sleep_cb_t s_cb_array[MAX_DSLP_HOOKS])404 static esp_err_t s_sleep_hook_register(esp_deep_sleep_cb_t new_cb, esp_deep_sleep_cb_t s_cb_array[MAX_DSLP_HOOKS])
405 {
406 RTC_DEEP_SLEEP_ENTER_CRITICAL();
407 for (int n = 0; n < MAX_DSLP_HOOKS; n++) {
408 if (s_cb_array[n]==NULL || s_cb_array[n]==new_cb) {
409 s_cb_array[n]=new_cb;
410 RTC_DEEP_SLEEP_EXIT_CRITICAL();
411 return ESP_OK;
412 }
413 }
414 RTC_DEEP_SLEEP_EXIT_CRITICAL();
415 ESP_LOGE(TAG, "Registered deepsleep callbacks exceeds MAX_DSLP_HOOKS");
416 return ESP_ERR_NO_MEM;
417 }
418
s_sleep_hook_deregister(esp_deep_sleep_cb_t old_cb,esp_deep_sleep_cb_t s_cb_array[MAX_DSLP_HOOKS])419 static void s_sleep_hook_deregister(esp_deep_sleep_cb_t old_cb, esp_deep_sleep_cb_t s_cb_array[MAX_DSLP_HOOKS])
420 {
421 RTC_DEEP_SLEEP_ENTER_CRITICAL();
422 for (int n = 0; n < MAX_DSLP_HOOKS; n++) {
423 if(s_cb_array[n] == old_cb) {
424 s_cb_array[n] = NULL;
425 }
426 }
427 RTC_DEEP_SLEEP_EXIT_CRITICAL();
428 }
429
esp_deep_sleep_register_hook(esp_deep_sleep_cb_t new_dslp_cb)430 esp_err_t esp_deep_sleep_register_hook(esp_deep_sleep_cb_t new_dslp_cb)
431 {
432 return s_sleep_hook_register(new_dslp_cb, s_dslp_cb);
433 }
434
esp_deep_sleep_deregister_hook(esp_deep_sleep_cb_t old_dslp_cb)435 void esp_deep_sleep_deregister_hook(esp_deep_sleep_cb_t old_dslp_cb)
436 {
437 s_sleep_hook_deregister(old_dslp_cb, s_dslp_cb);
438 }
439
esp_deep_sleep_register_phy_hook(esp_deep_sleep_cb_t new_dslp_cb)440 esp_err_t esp_deep_sleep_register_phy_hook(esp_deep_sleep_cb_t new_dslp_cb)
441 {
442 return s_sleep_hook_register(new_dslp_cb, s_dslp_phy_cb);
443 }
444
esp_deep_sleep_deregister_phy_hook(esp_deep_sleep_cb_t old_dslp_cb)445 void esp_deep_sleep_deregister_phy_hook(esp_deep_sleep_cb_t old_dslp_cb)
446 {
447 s_sleep_hook_deregister(old_dslp_cb, s_dslp_phy_cb);
448 }
449
s_do_deep_sleep_phy_callback(void)450 static void s_do_deep_sleep_phy_callback(void)
451 {
452 for (int n = 0; n < MAX_DSLP_HOOKS; n++) {
453 if (s_dslp_phy_cb[n] != NULL) {
454 s_dslp_phy_cb[n]();
455 }
456 }
457 }
458
459 static int s_cache_suspend_cnt = 0;
460
suspend_cache(void)461 static void IRAM_ATTR suspend_cache(void) {
462 s_cache_suspend_cnt++;
463 if (s_cache_suspend_cnt == 1) {
464 cache_hal_suspend(CACHE_TYPE_ALL);
465 }
466 }
467
resume_cache(void)468 static void IRAM_ATTR resume_cache(void) {
469 s_cache_suspend_cnt--;
470 assert(s_cache_suspend_cnt >= 0 && "cache resume doesn't match suspend ops");
471 if (s_cache_suspend_cnt == 0) {
472 cache_hal_resume(CACHE_TYPE_ALL);
473 }
474 }
475
476 #if SOC_SLEEP_TGWDT_STOP_WORKAROUND
477 static uint32_t s_stopped_tgwdt_bmap = 0;
478 #endif
479
480 // Must be called from critical sections.
suspend_timers(uint32_t pd_flags)481 static void IRAM_ATTR suspend_timers(uint32_t pd_flags) {
482 if (!(pd_flags & RTC_SLEEP_PD_XTAL)) {
483 #if SOC_SLEEP_TGWDT_STOP_WORKAROUND
484 /* If timegroup implemented task watchdog or interrupt watchdog is running, we have to stop it. */
485 for (uint32_t tg_num = 0; tg_num < SOC_TIMER_GROUPS; ++tg_num) {
486 if (mwdt_ll_check_if_enabled(TIMER_LL_GET_HW(tg_num))) {
487 mwdt_ll_write_protect_disable(TIMER_LL_GET_HW(tg_num));
488 mwdt_ll_disable(TIMER_LL_GET_HW(tg_num));
489 mwdt_ll_write_protect_enable(TIMER_LL_GET_HW(tg_num));
490 s_stopped_tgwdt_bmap |= BIT(tg_num);
491 }
492 }
493 #endif
494 #if SOC_SLEEP_SYSTIMER_STALL_WORKAROUND
495 for (uint32_t counter_id = 0; counter_id < SOC_SYSTIMER_COUNTER_NUM; ++counter_id) {
496 systimer_ll_enable_counter(&SYSTIMER, counter_id, false);
497 }
498 #endif
499 }
500 }
501
502 // Must be called from critical sections.
resume_timers(uint32_t pd_flags)503 static void IRAM_ATTR resume_timers(uint32_t pd_flags) {
504 if (!(pd_flags & RTC_SLEEP_PD_XTAL)) {
505 #if SOC_SLEEP_SYSTIMER_STALL_WORKAROUND
506 for (uint32_t counter_id = 0; counter_id < SOC_SYSTIMER_COUNTER_NUM; ++counter_id) {
507 systimer_ll_enable_counter(&SYSTIMER, counter_id, true);
508 }
509 #endif
510 #if SOC_SLEEP_TGWDT_STOP_WORKAROUND
511 for (uint32_t tg_num = 0; tg_num < SOC_TIMER_GROUPS; ++tg_num) {
512 if (s_stopped_tgwdt_bmap & BIT(tg_num)) {
513 mwdt_ll_write_protect_disable(TIMER_LL_GET_HW(tg_num));
514 mwdt_ll_enable(TIMER_LL_GET_HW(tg_num));
515 mwdt_ll_write_protect_enable(TIMER_LL_GET_HW(tg_num));
516 }
517 }
518 #endif
519 }
520 }
521
522 // [refactor-todo] provide target logic for body of uart functions below
flush_uarts(void)523 static void IRAM_ATTR flush_uarts(void)
524 {
525 for (int i = 0; i < SOC_UART_NUM; ++i) {
526 #ifdef CONFIG_IDF_TARGET_ESP32
527 esp_rom_uart_tx_wait_idle(i);
528 #else
529 if (periph_ll_periph_enabled(PERIPH_UART0_MODULE + i)) {
530 esp_rom_uart_tx_wait_idle(i);
531 }
532 #endif
533 }
534 }
535
536 static uint32_t s_suspended_uarts_bmap = 0;
537
538 /**
539 * Suspend enabled uarts and return suspended uarts bit map
540 */
suspend_uarts(void)541 static IRAM_ATTR void suspend_uarts(void)
542 {
543 s_suspended_uarts_bmap = 0;
544 for (int i = 0; i < SOC_UART_NUM; ++i) {
545 #ifndef CONFIG_IDF_TARGET_ESP32
546 if (!periph_ll_periph_enabled(PERIPH_UART0_MODULE + i)) {
547 continue;
548 }
549 #endif
550 uart_ll_force_xoff(i);
551 s_suspended_uarts_bmap |= BIT(i);
552 #if SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
553 uint32_t uart_fsm = 0;
554 do {
555 uart_fsm = uart_ll_get_fsm_status(i);
556 } while (!(uart_fsm == UART_LL_FSM_IDLE || uart_fsm == UART_LL_FSM_TX_WAIT_SEND));
557 #else
558 while (uart_ll_get_fsm_status(i) != 0) {}
559 #endif
560 }
561 }
562
resume_uarts(void)563 static void IRAM_ATTR resume_uarts(void)
564 {
565 for (int i = 0; i < SOC_UART_NUM; ++i) {
566 if (s_suspended_uarts_bmap & 0x1) {
567 uart_ll_force_xon(i);
568 }
569 s_suspended_uarts_bmap >>= 1;
570 }
571 }
572
573 /*
574 UART prepare strategy in sleep:
575 Deepsleep : flush the fifo before enter sleep to avoid data loss
576
577 Lightsleep:
578 Chips not support PD_TOP: Suspend uart before cpu freq switch
579
580 Chips support PD_TOP:
581 For sleep which will not power down the TOP domain (uart belongs it), we can just suspend the UART.
582
583 For sleep which will power down the TOP domain, we need to consider whether the uart flushing will
584 block the sleep process and cause the rtos target tick to be missed upon waking up. It's need to
585 estimate the flush time based on the number of bytes in the uart FIFO, if the predicted flush
586 completion time has exceeded the wakeup time, we should abandon the flush, skip the sleep and
587 return ESP_ERR_SLEEP_REJECT.
588 */
light_sleep_uart_prepare(uint32_t pd_flags,int64_t sleep_duration)589 static bool light_sleep_uart_prepare(uint32_t pd_flags, int64_t sleep_duration)
590 {
591 bool should_skip_sleep = false;
592 #if !SOC_PM_SUPPORT_TOP_PD || !CONFIG_ESP_CONSOLE_UART
593 suspend_uarts();
594 #else
595 #ifdef CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION
596 #define FORCE_FLUSH_CONSOLE_UART 1
597 #else
598 #define FORCE_FLUSH_CONSOLE_UART 0
599 #endif
600 if (FORCE_FLUSH_CONSOLE_UART || (pd_flags & PMU_SLEEP_PD_TOP)) {
601 if ((s_config.wakeup_triggers & RTC_TIMER_TRIG_EN) &&
602 // +1 is for cover the last character flush time
603 (sleep_duration < (int64_t)((UART_LL_FIFO_DEF_LEN - uart_ll_get_txfifo_len(CONSOLE_UART_DEV) + 1) * UART_FLUSH_US_PER_CHAR) + SLEEP_UART_FLUSH_DONE_TO_SLEEP_US)) {
604 should_skip_sleep = true;
605 } else {
606 /* Only flush the uart_num configured to console, the transmission integrity of
607 other uarts is guaranteed by the UART driver */
608 esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
609 }
610 } else {
611 suspend_uarts();
612 }
613 #endif
614 return should_skip_sleep;
615 }
616
617 /**
618 * These save-restore workaround should be moved to lower layer
619 */
misc_modules_sleep_prepare(bool deep_sleep)620 inline static void IRAM_ATTR misc_modules_sleep_prepare(bool deep_sleep)
621 {
622 if (deep_sleep){
623 for (int n = 0; n < MAX_DSLP_HOOKS; n++) {
624 if (s_dslp_cb[n] != NULL) {
625 s_dslp_cb[n]();
626 }
627 }
628 } else {
629 #if SOC_USB_SERIAL_JTAG_SUPPORTED && !SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP
630 // Only avoid USJ pad leakage here, USB OTG pad leakage is prevented through USB Host driver.
631 sleep_console_usj_pad_backup_and_disable();
632 #endif
633 #if CONFIG_MAC_BB_PD
634 mac_bb_power_down_cb_execute();
635 #endif
636 #if CONFIG_GPIO_ESP32_SUPPORT_SWITCH_SLP_PULL
637 gpio_sleep_mode_config_apply();
638 #endif
639 #if SOC_PM_SUPPORT_CPU_PD && SOC_PM_CPU_RETENTION_BY_RTCCNTL
640 sleep_enable_cpu_retention();
641 #endif
642 #if REGI2C_ANA_CALI_PD_WORKAROUND
643 regi2c_analog_cali_reg_read();
644 #endif
645 }
646
647 // TODO: IDF-7370
648 if (!(deep_sleep && s_adc_tsen_enabled)){
649 sar_periph_ctrl_power_disable();
650 }
651 }
652
653 /**
654 * These save-restore workaround should be moved to lower layer
655 */
misc_modules_wake_prepare(void)656 inline static void IRAM_ATTR misc_modules_wake_prepare(void)
657 {
658 #if SOC_USB_SERIAL_JTAG_SUPPORTED && !SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP
659 sleep_console_usj_pad_restore();
660 #endif
661 sar_periph_ctrl_power_enable();
662 #if SOC_PM_SUPPORT_CPU_PD && SOC_PM_CPU_RETENTION_BY_RTCCNTL
663 sleep_disable_cpu_retention();
664 #endif
665 #if CONFIG_GPIO_ESP32_SUPPORT_SWITCH_SLP_PULL
666 gpio_sleep_mode_config_unapply();
667 #endif
668 #if CONFIG_MAC_BB_PD
669 mac_bb_power_up_cb_execute();
670 #endif
671 #if REGI2C_ANA_CALI_PD_WORKAROUND
672 regi2c_analog_cali_reg_write();
673 #endif
674 }
675
sleep_low_power_clock_calibration(bool is_dslp)676 static IRAM_ATTR void sleep_low_power_clock_calibration(bool is_dslp)
677 {
678 // Calibrate rtc slow clock
679 #ifdef CONFIG_ESP_SYSTEM_RTC_EXT_XTAL
680 if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
681 uint64_t time_per_us = 1000000ULL;
682 s_config.rtc_clk_cal_period = (time_per_us << RTC_CLK_CAL_FRACT) / rtc_clk_slow_freq_get_hz();
683 } else {
684 // If the external 32 kHz XTAL does not exist, use the internal 150 kHz RC oscillator
685 // as the RTC slow clock source.
686 s_config.rtc_clk_cal_period = rtc_clk_cal(RTC_CAL_RTC_MUX, RTC_CLK_SRC_CAL_CYCLES);
687 esp_clk_slowclk_cal_set(s_config.rtc_clk_cal_period);
688 }
689 #elif CONFIG_RTC_CLK_SRC_INT_RC && CONFIG_IDF_TARGET_ESP32S2
690 s_config.rtc_clk_cal_period = rtc_clk_cal_cycling(RTC_CAL_RTC_MUX, RTC_CLK_SRC_CAL_CYCLES);
691 esp_clk_slowclk_cal_set(s_config.rtc_clk_cal_period);
692 #else
693 s_config.rtc_clk_cal_period = rtc_clk_cal(RTC_CAL_RTC_MUX, RTC_CLK_SRC_CAL_CYCLES);
694 esp_clk_slowclk_cal_set(s_config.rtc_clk_cal_period);
695 #endif
696
697 // Calibrate rtc fast clock, only PMU supported chips sleep process is needed.
698 #if SOC_PMU_SUPPORTED
699 s_config.fast_clk_cal_period = rtc_clk_cal(RTC_CAL_RC_FAST, FAST_CLK_SRC_CAL_CYCLES);
700 #endif
701 }
702
703
704 inline static uint32_t call_rtc_sleep_start(uint32_t reject_triggers, uint32_t lslp_mem_inf_fpu, bool dslp);
705
esp_sleep_start(uint32_t pd_flags,esp_sleep_mode_t mode,bool allow_sleep_rejection)706 static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t mode, bool allow_sleep_rejection)
707 {
708 // Stop UART output so that output is not lost due to APB frequency change.
709 // For light sleep, suspend UART output — it will resume after wakeup.
710 // For deep sleep, wait for the contents of UART FIFO to be sent.
711 bool deep_sleep = (mode == ESP_SLEEP_MODE_DEEP_SLEEP);
712 bool should_skip_sleep = false;
713
714 int64_t sleep_duration = (int64_t) s_config.sleep_duration - (int64_t) s_config.sleep_time_adjustment;
715
716 #if SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256
717 //Keep the RTC8M_CLK on if RTC clock is rc_fast_d256.
718 bool rtc_using_8md256 = (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256);
719 #else
720 bool rtc_using_8md256 = false;
721 #endif
722 //Keep the RTC8M_CLK on if the ledc low-speed channel is clocked by RTC8M_CLK in lightsleep mode
723 bool periph_using_8m = !deep_sleep && s_periph_use_8m_flag;
724
725 //Override user-configured power modes.
726 if (rtc_using_8md256 || periph_using_8m) {
727 pd_flags &= ~RTC_SLEEP_PD_INT_8M;
728 }
729
730 // Will switch to XTAL turn down MSPI speed
731 #if SOC_SPI_MEM_SUPPORT_TIME_TUNING
732 mspi_timing_change_speed_mode_cache_safe(true);
733 #endif
734
735 // Set mspi clock to a low-power one.
736 #if SOC_MEMSPI_CLOCK_IS_INDEPENDENT
737 spi_flash_set_clock_src(MSPI_CLK_SRC_ROM_DEFAULT);
738 #endif
739
740 // Sleep UART prepare
741 if (deep_sleep) {
742 flush_uarts();
743 } else {
744 should_skip_sleep = light_sleep_uart_prepare(pd_flags, sleep_duration);
745 }
746
747 // Do deep-sleep PHY related callback, which need to be executed when the PLL clock is exists.
748 // For light-sleep, PHY state is managed by the upper layer of the wifi/bt protocol stack.
749 if (deep_sleep) {
750 s_do_deep_sleep_phy_callback();
751 }
752
753 #if SOC_PM_RETENTION_SW_TRIGGER_REGDMA
754 if (!deep_sleep && (pd_flags & PMU_SLEEP_PD_TOP)) {
755 sleep_retention_do_system_retention(true);
756 }
757 #endif
758
759 // Save current frequency and switch to XTAL
760 rtc_cpu_freq_config_t cpu_freq_config;
761 rtc_clk_cpu_freq_get_config(&cpu_freq_config);
762 rtc_clk_cpu_freq_set_xtal();
763
764 #if SOC_PM_SUPPORT_EXT0_WAKEUP
765 // Configure pins for external wakeup
766 if (s_config.wakeup_triggers & RTC_EXT0_TRIG_EN) {
767 ext0_wakeup_prepare();
768 }
769 #endif
770 #if SOC_PM_SUPPORT_EXT1_WAKEUP
771 if (s_config.wakeup_triggers & RTC_EXT1_TRIG_EN) {
772 ext1_wakeup_prepare();
773 }
774 #endif
775
776 #if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
777 if (deep_sleep && (s_config.wakeup_triggers & RTC_GPIO_TRIG_EN)) {
778 gpio_deep_sleep_wakeup_prepare();
779 }
780 #endif
781
782 #if CONFIG_ULP_COPROC_ENABLED
783 // Enable ULP wakeup
784 #if CONFIG_ULP_COPROC_TYPE_FSM
785 if (s_config.wakeup_triggers & RTC_ULP_TRIG_EN) {
786 #elif CONFIG_ULP_COPROC_TYPE_RISCV
787 if (s_config.wakeup_triggers & (RTC_COCPU_TRIG_EN | RTC_COCPU_TRAP_TRIG_EN)) {
788 #elif CONFIG_ULP_COPROC_TYPE_LP_CORE
789 if (s_config.wakeup_triggers & RTC_LP_CORE_TRIG_EN) {
790 #endif
791 #ifdef CONFIG_IDF_TARGET_ESP32
792 rtc_hal_ulp_wakeup_enable();
793 #elif CONFIG_ULP_COPROC_TYPE_LP_CORE
794 pmu_ll_hp_clear_sw_intr_status(&PMU);
795 #else
796 rtc_hal_ulp_int_clear();
797 #endif
798 }
799 #endif // CONFIG_ULP_COPROC_ENABLED
800
801 misc_modules_sleep_prepare(deep_sleep);
802
803 #if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
804 if (deep_sleep) {
805 if (s_config.wakeup_triggers & RTC_TOUCH_TRIG_EN) {
806 touch_wakeup_prepare();
807 #if CONFIG_IDF_TARGET_ESP32S2
808 /* Workaround: In deep sleep, for ESP32S2, Power down the RTC_PERIPH will change the slope configuration of Touch sensor sleep pad.
809 * The configuration change will change the reading of the sleep pad, which will cause the touch wake-up sensor to trigger falsely.
810 */
811 pd_flags &= ~RTC_SLEEP_PD_RTC_PERIPH;
812 #endif
813 }
814 } else {
815 /* In light sleep, the RTC_PERIPH power domain should be in the power-on state (Power on the touch circuit in light sleep),
816 * otherwise the touch sensor FSM will be cleared, causing touch sensor false triggering.
817 */
818 if (touch_ll_get_fsm_state()) { // Check if the touch sensor is working properly.
819 pd_flags &= ~RTC_SLEEP_PD_RTC_PERIPH;
820 }
821 }
822 #endif
823
824 uint32_t reject_triggers = allow_sleep_rejection ? (s_config.wakeup_triggers & RTC_SLEEP_REJECT_MASK) : 0;
825
826 if (!deep_sleep) {
827 /* Enable sleep reject for faster return from this function,
828 * in case the wakeup is already triggerred.
829 */
830 reject_triggers |= sleep_modem_reject_triggers();
831 }
832
833 //Append some flags in addition to power domains
834 uint32_t sleep_flags = pd_flags;
835 if (s_adc_tsen_enabled) {
836 sleep_flags |= RTC_SLEEP_USE_ADC_TESEN_MONITOR;
837 }
838 if (!s_ultra_low_enabled) {
839 sleep_flags |= RTC_SLEEP_NO_ULTRA_LOW;
840 }
841 if (periph_using_8m) {
842 sleep_flags |= RTC_SLEEP_DIG_USE_8M;
843 }
844
845 #if CONFIG_ESP_SLEEP_DEBUG
846 if (s_sleep_ctx != NULL) {
847 s_sleep_ctx->sleep_flags = sleep_flags;
848 }
849 #endif
850
851 // Enter sleep
852 esp_err_t result;
853 #if SOC_PMU_SUPPORTED
854 pmu_sleep_config_t config;
855 pmu_sleep_init(pmu_sleep_config_default(&config, sleep_flags, s_config.sleep_time_adjustment,
856 s_config.rtc_clk_cal_period, s_config.fast_clk_cal_period,
857 deep_sleep), deep_sleep);
858 #else
859 rtc_sleep_config_t config;
860 rtc_sleep_get_default_config(sleep_flags, &config);
861 rtc_sleep_init(config);
862
863 // Set state machine time for light sleep
864 if (!deep_sleep) {
865 rtc_sleep_low_init(s_config.rtc_clk_cal_period);
866 }
867 #endif
868
869 // Configure timer wakeup
870 if (!should_skip_sleep && (s_config.wakeup_triggers & RTC_TIMER_TRIG_EN)) {
871 if (timer_wakeup_prepare(sleep_duration) != ESP_OK) {
872 should_skip_sleep = allow_sleep_rejection ? true : false;
873 }
874 }
875
876
877 if (should_skip_sleep) {
878 result = ESP_ERR_SLEEP_REJECT;
879 } else {
880 #if CONFIG_ESP_SLEEP_DEBUG
881 if (s_sleep_ctx != NULL) {
882 s_sleep_ctx->wakeup_triggers = s_config.wakeup_triggers;
883 }
884 #endif
885 if (deep_sleep) {
886 #if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
887 esp_sleep_isolate_digital_gpio();
888 #endif
889
890 #if SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
891 esp_set_deep_sleep_wake_stub_default_entry();
892 // Enter Deep Sleep
893 #if SOC_PMU_SUPPORTED
894 result = call_rtc_sleep_start(reject_triggers, config.power.hp_sys.dig_power.mem_dslp, deep_sleep);
895 #else
896 result = call_rtc_sleep_start(reject_triggers, config.lslp_mem_inf_fpu, deep_sleep);
897 #endif
898 #else
899 #if !CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
900 /* If not possible stack is in RTC FAST memory, use the ROM function to calculate the CRC and save ~140 bytes IRAM */
901 #if SOC_RTC_FAST_MEM_SUPPORTED
902 set_rtc_memory_crc();
903 #endif
904 result = call_rtc_sleep_start(reject_triggers, config.lslp_mem_inf_fpu, deep_sleep);
905 #else
906 /* Otherwise, need to call the dedicated soc function for this */
907 result = rtc_deep_sleep_start(s_config.wakeup_triggers, reject_triggers);
908 #endif
909 #endif // SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
910 } else {
911 suspend_timers(pd_flags);
912 /* Cache Suspend 1: will wait cache idle in cache suspend to avoid cache load wrong data after spi io isolation */
913 suspend_cache();
914 /* On esp32c6, only the lp_aon pad hold function can only hold the GPIO state in the active mode.
915 In order to avoid the leakage of the SPI cs pin, hold it here */
916 #if (CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND)
917 #if !CONFIG_IDF_TARGET_ESP32H2 // ESP32H2 TODO IDF-7359: related rtcio ll func not supported yet
918 if(!(pd_flags & PMU_SLEEP_PD_VDDSDIO)) {
919 gpio_ll_hold_en(&GPIO, SPI_CS0_GPIO_NUM);
920 }
921 #endif
922 #endif
923
924 #if SOC_PMU_SUPPORTED
925 #if SOC_PM_CPU_RETENTION_BY_SW
926 esp_sleep_execute_event_callbacks(SLEEP_EVENT_HW_GOTO_SLEEP, (void *)0);
927 if (pd_flags & PMU_SLEEP_PD_CPU) {
928 result = esp_sleep_cpu_retention(pmu_sleep_start, s_config.wakeup_triggers, reject_triggers, config.power.hp_sys.dig_power.mem_dslp, deep_sleep);
929 } else
930 #endif
931 {
932 result = call_rtc_sleep_start(reject_triggers, config.power.hp_sys.dig_power.mem_dslp, deep_sleep);
933 }
934 esp_sleep_execute_event_callbacks(SLEEP_EVENT_HW_EXIT_SLEEP, (void *)0);
935 #else
936 result = call_rtc_sleep_start(reject_triggers, config.lslp_mem_inf_fpu, deep_sleep);
937 #endif
938
939 /* Unhold the SPI CS pin */
940 #if (CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND)
941 #if !CONFIG_IDF_TARGET_ESP32H2 // ESP32H2 TODO IDF-7359: related rtcio ll func not supported yet
942 if(!(pd_flags & PMU_SLEEP_PD_VDDSDIO)) {
943 gpio_ll_hold_dis(&GPIO, SPI_CS0_GPIO_NUM);
944 }
945 #endif
946 #endif
947 /* Cache Resume 1: Resume cache for continue running*/
948 resume_cache();
949 resume_timers(pd_flags);
950 }
951 }
952
953 #if CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION
954 if (pd_flags & RTC_SLEEP_PD_VDDSDIO) {
955 /* Cache Suspend 2: If previous sleep powerdowned the flash, suspend cache here so that the
956 access to flash before flash ready can be explicitly exposed. */
957 suspend_cache();
958 }
959 #endif
960
961 // Restore CPU frequency
962 #if SOC_PM_SUPPORT_PMU_MODEM_STATE
963 if (pmu_sleep_pll_already_enabled()) {
964 rtc_clk_cpu_freq_to_pll_and_pll_lock_release(esp_pm_impl_get_cpu_freq(PM_MODE_CPU_MAX));
965 } else
966 #endif
967 {
968 rtc_clk_cpu_freq_set_config(&cpu_freq_config);
969 }
970
971 esp_sleep_execute_event_callbacks(SLEEP_EVENT_SW_CLK_READY, (void *)0);
972
973 if (!deep_sleep) {
974 if (result == ESP_OK) {
975 s_config.ccount_ticks_record = esp_cpu_get_cycle_count();
976 #if SOC_PM_RETENTION_SW_TRIGGER_REGDMA
977 if (pd_flags & PMU_SLEEP_PD_TOP) {
978 sleep_retention_do_system_retention(false);
979 }
980 #endif
981 }
982 misc_modules_wake_prepare();
983 }
984
985 // Set mspi clock to ROM default one.
986 if (cpu_freq_config.source == SOC_CPU_CLK_SRC_PLL) {
987 #if SOC_MEMSPI_CLOCK_IS_INDEPENDENT
988 spi_flash_set_clock_src(MSPI_CLK_SRC_DEFAULT);
989 #endif
990 #if SOC_SPI_MEM_SUPPORT_TIME_TUNING
991 // Turn up MSPI speed if switch to PLL
992 mspi_timing_change_speed_mode_cache_safe(false);
993 #endif
994 }
995
996 // re-enable UART output
997 resume_uarts();
998 return result ? ESP_ERR_SLEEP_REJECT : ESP_OK;
999 }
1000
1001 inline static uint32_t IRAM_ATTR call_rtc_sleep_start(uint32_t reject_triggers, uint32_t lslp_mem_inf_fpu, bool dslp)
1002 {
1003 #ifdef CONFIG_IDF_TARGET_ESP32
1004 return rtc_sleep_start(s_config.wakeup_triggers, reject_triggers);
1005 #elif SOC_PMU_SUPPORTED
1006 return pmu_sleep_start(s_config.wakeup_triggers, reject_triggers, lslp_mem_inf_fpu, dslp);
1007 #else
1008 return rtc_sleep_start(s_config.wakeup_triggers, reject_triggers, lslp_mem_inf_fpu);
1009 #endif
1010 }
1011
1012 static esp_err_t IRAM_ATTR deep_sleep_start(bool allow_sleep_rejection)
1013 {
1014 #if CONFIG_IDF_TARGET_ESP32S2
1015 /* Due to hardware limitations, on S2 the brownout detector sometimes trigger during deep sleep
1016 to circumvent this we disable the brownout detector before sleeping */
1017 esp_brownout_disable();
1018 #endif //CONFIG_IDF_TARGET_ESP32S2
1019
1020 // esp_sync_timekeeping_timers();
1021
1022 /* Disable interrupts and stall another core in case another task writes
1023 * to RTC memory while we calculate RTC memory CRC.
1024 */
1025 RTC_DEEP_SLEEP_ENTER_CRITICAL();
1026
1027 // record current RTC time
1028 s_config.rtc_ticks_at_sleep_start = rtc_time_get();
1029
1030 #if SOC_RTC_FAST_MEM_SUPPORTED
1031 // Configure wake stub
1032 if (esp_get_deep_sleep_wake_stub() == NULL) {
1033 esp_set_deep_sleep_wake_stub(esp_wake_deep_sleep);
1034 }
1035 #endif // SOC_RTC_FAST_MEM_SUPPORTED
1036
1037 // Decide which power domains can be powered down
1038 uint32_t pd_flags = get_power_down_flags();
1039
1040 // Re-calibrate the RTC clock
1041 sleep_low_power_clock_calibration(true);
1042
1043 // Correct the sleep time
1044 s_config.sleep_time_adjustment = DEEP_SLEEP_TIME_OVERHEAD_US;
1045
1046 #if SOC_PMU_SUPPORTED
1047 uint32_t force_pd_flags = PMU_SLEEP_PD_TOP | PMU_SLEEP_PD_VDDSDIO | PMU_SLEEP_PD_MODEM | PMU_SLEEP_PD_HP_PERIPH \
1048 | PMU_SLEEP_PD_CPU | PMU_SLEEP_PD_MEM | PMU_SLEEP_PD_XTAL;
1049 #if SOC_PM_SUPPORT_HP_AON_PD
1050 force_pd_flags |= PMU_SLEEP_PD_HP_AON;
1051 #endif
1052 #else
1053 uint32_t force_pd_flags = RTC_SLEEP_PD_DIG | RTC_SLEEP_PD_VDDSDIO | RTC_SLEEP_PD_INT_8M | RTC_SLEEP_PD_XTAL;
1054 #endif
1055 /**
1056 * If all wireless modules share one power domain, we name this power domain "modem".
1057 * If wireless modules have their own power domain, we give these power domains separate
1058 * names.
1059 */
1060 #if SOC_PM_SUPPORT_MODEM_PD
1061 force_pd_flags |= RTC_SLEEP_PD_MODEM;
1062 #endif
1063
1064 #if SOC_PM_SUPPORT_WIFI_PD
1065 force_pd_flags |= RTC_SLEEP_PD_WIFI;
1066 #endif
1067
1068 #if SOC_PM_SUPPORT_BT_PD
1069 force_pd_flags |= RTC_SLEEP_PD_BT;
1070 #endif
1071
1072 // Enter sleep
1073 esp_err_t err = ESP_OK;
1074 if (esp_sleep_start(force_pd_flags | pd_flags, ESP_SLEEP_MODE_DEEP_SLEEP, allow_sleep_rejection) == ESP_ERR_SLEEP_REJECT) {
1075 err = ESP_ERR_SLEEP_REJECT;
1076 #if CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION
1077 /* Cache Resume 2: if CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION is enabled, cache has been suspended in esp_sleep_start */
1078 resume_cache();
1079 #endif
1080 ESP_EARLY_LOGE(TAG, "Deep sleep request is rejected");
1081 } else {
1082 // Because RTC is in a slower clock domain than the CPU, it
1083 // can take several CPU cycles for the sleep mode to start.
1084 while (1) {
1085 ;
1086 }
1087 }
1088 // Never returns here, except that the sleep is rejected.
1089 // esp_ipc_isr_release_other_cpu(); // Zephyr: only for SMP mode
1090 RTC_DEEP_SLEEP_EXIT_CRITICAL();
1091 return err;
1092 }
1093
1094 void IRAM_ATTR esp_deep_sleep_start(void)
1095 {
1096 bool allow_sleep_rejection = true;
1097 deep_sleep_start(!allow_sleep_rejection);
1098 // Never returns here
1099 abort();
1100 }
1101
1102 esp_err_t IRAM_ATTR esp_deep_sleep_try_to_start(void)
1103 {
1104 bool allow_sleep_rejection = true;
1105 return deep_sleep_start(allow_sleep_rejection);
1106 }
1107
1108 /**
1109 * Helper function which handles entry to and exit from light sleep
1110 * Placed into IRAM as flash may need some time to be powered on.
1111 */
1112 static esp_err_t esp_light_sleep_inner(uint32_t pd_flags,
1113 uint32_t flash_enable_time_us) IRAM_ATTR __attribute__((noinline));
1114
1115 static esp_err_t esp_light_sleep_inner(uint32_t pd_flags,
1116 uint32_t flash_enable_time_us)
1117 {
1118 #if SOC_CONFIGURABLE_VDDSDIO_SUPPORTED
1119 rtc_vddsdio_config_t vddsdio_config = rtc_vddsdio_get_config();
1120 #endif
1121
1122 // Enter sleep
1123 esp_err_t reject = esp_sleep_start(pd_flags, ESP_SLEEP_MODE_LIGHT_SLEEP, true);
1124
1125 #if SOC_CONFIGURABLE_VDDSDIO_SUPPORTED
1126 // If VDDSDIO regulator was controlled by RTC registers before sleep,
1127 // restore the configuration.
1128 if (vddsdio_config.force) {
1129 rtc_vddsdio_set_config(vddsdio_config);
1130 }
1131 #endif
1132
1133 // If SPI flash was powered down, wait for it to become ready
1134 if (!reject && (pd_flags & RTC_SLEEP_PD_VDDSDIO)) {
1135 #if SOC_PM_SUPPORT_TOP_PD
1136 if (pd_flags & PMU_SLEEP_PD_TOP) {
1137 uint32_t flash_ready_hw_waited_time_us = pmu_sleep_get_wakup_retention_cost();
1138 uint32_t flash_ready_sw_waited_time_us = (esp_cpu_get_cycle_count() - s_config.ccount_ticks_record) / (esp_clk_cpu_freq() / MHZ(1));
1139 uint32_t flash_ready_waited_time_us = flash_ready_hw_waited_time_us + flash_ready_sw_waited_time_us;
1140 if (flash_enable_time_us > flash_ready_waited_time_us){
1141 flash_enable_time_us -= flash_ready_waited_time_us;
1142 } else {
1143 flash_enable_time_us = 0;
1144 }
1145 }
1146 #endif
1147 // Wait for the flash chip to start up
1148 esp_rom_delay_us(flash_enable_time_us);
1149 }
1150
1151 #if CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION
1152 if (pd_flags & RTC_SLEEP_PD_VDDSDIO) {
1153 /* Cache Resume 2: flash is ready now, we can resume the cache and access flash safely after */
1154 resume_cache();
1155 }
1156 #endif
1157
1158 return reject;
1159 }
1160
1161 /**
1162 * vddsdio is used for power supply of spi flash
1163 *
1164 * pd flash via menuconfig | pd flash via `esp_sleep_pd_config` | result
1165 * ---------------------------------------------------------------------------------------------------
1166 * 0 | 0 | no pd flash
1167 * x | 1 | pd flash with relaxed conditions(force_pd)
1168 * 1 | 0 | pd flash with strict conditions(safe_pd)
1169 */
1170 static inline bool can_power_down_vddsdio(uint32_t pd_flags, const uint32_t vddsdio_pd_sleep_duration)
1171 {
1172 bool force_pd = !(s_config.wakeup_triggers & RTC_TIMER_TRIG_EN) || (s_config.sleep_duration > vddsdio_pd_sleep_duration);
1173 bool safe_pd = (s_config.wakeup_triggers == RTC_TIMER_TRIG_EN) && (s_config.sleep_duration > vddsdio_pd_sleep_duration);
1174 return (pd_flags & RTC_SLEEP_PD_VDDSDIO) ? force_pd : safe_pd;
1175 }
1176
1177 esp_err_t esp_light_sleep_start(void)
1178 {
1179 s_config.ccount_ticks_record = esp_cpu_get_cycle_count();
1180 esp_sleep_execute_event_callbacks(SLEEP_EVENT_SW_GOTO_SLEEP, (void *)0);
1181 #if CONFIG_ESP_TASK_WDT_USE_ESP_TIMER
1182 esp_err_t timerret = ESP_OK;
1183
1184 /* If a task watchdog timer is running, we have to stop it. */
1185 timerret = esp_task_wdt_stop();
1186 #endif // CONFIG_ESP_TASK_WDT_USE_ESP_TIMER
1187
1188 s_config.lock = irq_lock();
1189 /*
1190 Note: We are about to stall the other CPU via the esp_ipc_isr_stall_other_cpu(). However, there is a chance of
1191 deadlock if after stalling the other CPU, we attempt to take spinlocks already held by the other CPU that is.
1192
1193 Thus any functions that we call after stalling the other CPU will need to have the locks taken first to avoid
1194 deadlock.
1195
1196 Todo: IDF-5257
1197 */
1198
1199 /* We will be calling esp_timer_private_set inside DPORT access critical
1200 * section. Make sure the code on the other CPU is not holding esp_timer
1201 * lock, otherwise there will be deadlock.
1202 */
1203 esp_timer_private_lock();
1204
1205 /* We will be calling esp_rtc_get_time_us() below. Make sure the code on the other CPU is not holding the
1206 * esp_rtc_get_time_us() lock, otherwise there will be deadlock. esp_rtc_get_time_us() is called via:
1207 *
1208 * - esp_clk_slowclk_cal_set() -> esp_rtc_get_time_us()
1209 */
1210 esp_clk_private_lock();
1211
1212 s_config.rtc_ticks_at_sleep_start = rtc_time_get();
1213 uint32_t ccount_at_sleep_start = esp_cpu_get_cycle_count();
1214 esp_sleep_execute_event_callbacks(SLEEP_EVENT_HW_TIME_START, (void *)0);
1215 uint64_t high_res_time_at_start = esp_timer_get_time();
1216 uint32_t sleep_time_overhead_in = (ccount_at_sleep_start - s_config.ccount_ticks_record) / (esp_clk_cpu_freq() / 1000000ULL);
1217
1218 #if CONFIG_ESP_SLEEP_DEBUG
1219 if (s_sleep_ctx != NULL) {
1220 s_sleep_ctx->sleep_in_rtc_time_stamp = s_config.rtc_ticks_at_sleep_start;
1221 }
1222 #endif
1223
1224 // Decide which power domains can be powered down
1225 uint32_t pd_flags = get_power_down_flags();
1226
1227 #ifdef CONFIG_ESP_SLEEP_RTC_BUS_ISO_WORKAROUND
1228 pd_flags &= ~RTC_SLEEP_PD_RTC_PERIPH;
1229 #endif
1230
1231 // Re-calibrate the RTC clock
1232 sleep_low_power_clock_calibration(false);
1233
1234 /*
1235 * Adjustment time consists of parts below:
1236 * 1. Hardware time waiting for internal 8M oscilate clock and XTAL;
1237 * 2. Hardware state swithing time of the rtc main state machine;
1238 * 3. Code execution time when clock is not stable;
1239 * 4. Code execution time which can be measured;
1240 */
1241 #if SOC_PMU_SUPPORTED
1242 int sleep_time_sw_adjustment = LIGHT_SLEEP_TIME_OVERHEAD_US + sleep_time_overhead_in + s_config.sleep_time_overhead_out;
1243 int sleep_time_hw_adjustment = pmu_sleep_calculate_hw_wait_time(pd_flags, s_config.rtc_clk_cal_period, s_config.fast_clk_cal_period);
1244 s_config.sleep_time_adjustment = sleep_time_sw_adjustment + sleep_time_hw_adjustment;
1245 #else
1246 uint32_t rtc_cntl_xtl_buf_wait_slp_cycles = rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, s_config.rtc_clk_cal_period);
1247 s_config.sleep_time_adjustment = LIGHT_SLEEP_TIME_OVERHEAD_US + sleep_time_overhead_in + s_config.sleep_time_overhead_out
1248 + rtc_time_slowclk_to_us(rtc_cntl_xtl_buf_wait_slp_cycles + RTC_CNTL_CK8M_WAIT_SLP_CYCLES + RTC_CNTL_WAKEUP_DELAY_CYCLES, s_config.rtc_clk_cal_period);
1249 #endif
1250
1251 // Decide if VDD_SDIO needs to be powered down;
1252 // If it needs to be powered down, adjust sleep time.
1253 const uint32_t flash_enable_time_us = ESP_SLEEP_WAIT_FLASH_READY_DEFAULT_DELAY_US + CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY;
1254
1255 /**
1256 * If VDD_SDIO power domain is requested to be turned off, bit `RTC_SLEEP_PD_VDDSDIO`
1257 * will be set in `pd_flags`.
1258 */
1259 if (pd_flags & RTC_SLEEP_PD_VDDSDIO) {
1260 /*
1261 * When VDD_SDIO power domain has to be turned off, the minimum sleep time of the
1262 * system needs to meet the sum below:
1263 * 1. Wait time for the flash power-on after waking up;
1264 * 2. The execution time of codes between RTC Timer get start time
1265 * with hardware starts to switch state to sleep;
1266 * 3. The hardware state switching time of the rtc state machine during
1267 * sleep and wake-up. This process requires 6 cycles to complete.
1268 * The specific hardware state switching process and the cycles
1269 * consumed are rtc_cpu_run_stall(1), cut_pll_rtl(2), cut_8m(1),
1270 * min_protect(2);
1271 * 4. All the adjustment time which is s_config.sleep_time_adjustment below.
1272 */
1273 const uint32_t vddsdio_pd_sleep_duration = MAX(FLASH_PD_MIN_SLEEP_TIME_US,
1274 flash_enable_time_us + LIGHT_SLEEP_MIN_TIME_US + s_config.sleep_time_adjustment
1275 + rtc_time_slowclk_to_us(RTC_MODULE_SLEEP_PREPARE_CYCLES, s_config.rtc_clk_cal_period));
1276
1277 if (can_power_down_vddsdio(pd_flags, vddsdio_pd_sleep_duration)) {
1278 if (s_config.sleep_time_overhead_out < flash_enable_time_us) {
1279 s_config.sleep_time_adjustment += flash_enable_time_us;
1280 }
1281 } else {
1282 /**
1283 * Minimum sleep time is not enough, then keep the VDD_SDIO power
1284 * domain on.
1285 */
1286 pd_flags &= ~RTC_SLEEP_PD_VDDSDIO;
1287 if (s_config.sleep_time_overhead_out > flash_enable_time_us) {
1288 s_config.sleep_time_adjustment -= flash_enable_time_us;
1289 }
1290 }
1291 }
1292
1293 periph_inform_out_light_sleep_overhead(s_config.sleep_time_adjustment - sleep_time_overhead_in);
1294
1295 // Safety net: enable WDT in case exit from light sleep fails
1296 wdt_hal_context_t rtc_wdt_ctx = RWDT_HAL_CONTEXT_DEFAULT();
1297 bool wdt_was_enabled = wdt_hal_is_enabled(&rtc_wdt_ctx); // If WDT was enabled in the user code, then do not change it here.
1298 if (!wdt_was_enabled) {
1299 wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false);
1300 uint32_t stage_timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
1301 wdt_hal_write_protect_disable(&rtc_wdt_ctx);
1302 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
1303 wdt_hal_enable(&rtc_wdt_ctx);
1304 wdt_hal_write_protect_enable(&rtc_wdt_ctx);
1305 }
1306
1307 esp_err_t err = ESP_OK;
1308 int64_t final_sleep_duration_us = (int64_t)s_config.sleep_duration - (int64_t)s_config.sleep_time_adjustment;
1309 int64_t min_sleep_duration_us = rtc_time_slowclk_to_us(RTC_CNTL_MIN_SLP_VAL_MIN, s_config.rtc_clk_cal_period);
1310
1311 // reset light sleep wakeup flag before a new light sleep
1312 s_light_sleep_wakeup = false;
1313
1314 s_lightsleep_cnt++;
1315 #if CONFIG_ESP_SLEEP_DEBUG
1316 if (s_sleep_ctx != NULL) {
1317 s_sleep_ctx->lightsleep_cnt = s_lightsleep_cnt;
1318 }
1319 #endif
1320
1321 // if rtc timer wakeup source is enabled, need to compare final sleep duration and min sleep duration to avoid late wakeup
1322 if ((s_config.wakeup_triggers & RTC_TIMER_TRIG_EN) && (final_sleep_duration_us <= min_sleep_duration_us)) {
1323 err = ESP_ERR_SLEEP_TOO_SHORT_SLEEP_DURATION;
1324 } else {
1325 // Enter sleep, then wait for flash to be ready on wakeup
1326 err = esp_light_sleep_inner(pd_flags, flash_enable_time_us);
1327 }
1328
1329 // light sleep wakeup flag only makes sense after a successful light sleep
1330 s_light_sleep_wakeup = (err == ESP_OK);
1331
1332 // System timer has been stopped for the duration of the sleep, correct for that.
1333 uint64_t rtc_ticks_at_end = rtc_time_get();
1334
1335 if (s_light_sleep_wakeup) {
1336 uint64_t rtc_time_diff = rtc_time_slowclk_to_us(rtc_ticks_at_end - s_config.rtc_ticks_at_sleep_start, s_config.rtc_clk_cal_period);
1337 /**
1338 * If sleep duration is too small(less than 1 rtc_slow_clk cycle), rtc_time_diff will be zero.
1339 * In this case, just ignore the time compensation and keep esp_timer monotonic.
1340 */
1341 if (rtc_time_diff > 0) {
1342 esp_timer_private_set(high_res_time_at_start + rtc_time_diff);
1343 }
1344 // esp_set_time_from_rtc();
1345 }
1346
1347 esp_clk_private_unlock();
1348 esp_timer_private_unlock();
1349
1350 if (!wdt_was_enabled) {
1351 wdt_hal_write_protect_disable(&rtc_wdt_ctx);
1352 wdt_hal_disable(&rtc_wdt_ctx);
1353 wdt_hal_write_protect_enable(&rtc_wdt_ctx);
1354 }
1355
1356 #if CONFIG_ESP_TASK_WDT_USE_ESP_TIMER
1357 /* Restart the Task Watchdog timer as it was stopped before sleeping. */
1358 if (timerret == ESP_OK) {
1359 esp_task_wdt_restart();
1360 }
1361 #endif // CONFIG_ESP_TASK_WDT_USE_ESP_TIMER
1362
1363 esp_sleep_execute_event_callbacks(SLEEP_EVENT_SW_EXIT_SLEEP, (void *)0);
1364
1365 #if CONFIG_ESP_SLEEP_DEBUG
1366 if (s_sleep_ctx != NULL) {
1367 s_sleep_ctx->sleep_out_rtc_time_stamp = rtc_ticks_at_end;
1368 s_sleep_ctx->sleep_request_result = err;
1369 }
1370 #endif
1371
1372 if (s_light_sleep_wakeup) {
1373 s_config.sleep_time_overhead_out = (esp_cpu_get_cycle_count() - s_config.ccount_ticks_record) / (esp_clk_cpu_freq() / 1000000ULL);
1374 }
1375
1376 irq_unlock(s_config.lock);
1377 return err;
1378 }
1379
1380 esp_err_t esp_sleep_disable_wakeup_source(esp_sleep_source_t source)
1381 {
1382 // For most of sources it is enough to set trigger mask in local
1383 // configuration structure. The actual RTC wake up options
1384 // will be updated by esp_sleep_start().
1385 if (source == ESP_SLEEP_WAKEUP_ALL) {
1386 s_config.wakeup_triggers = 0;
1387 } else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_TIMER, RTC_TIMER_TRIG_EN)) {
1388 s_config.wakeup_triggers &= ~RTC_TIMER_TRIG_EN;
1389 s_config.sleep_duration = 0;
1390 #if SOC_PM_SUPPORT_EXT0_WAKEUP
1391 } else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_EXT0, RTC_EXT0_TRIG_EN)) {
1392 s_config.ext0_rtc_gpio_num = 0;
1393 s_config.ext0_trigger_level = 0;
1394 s_config.wakeup_triggers &= ~RTC_EXT0_TRIG_EN;
1395 #endif
1396 #if SOC_PM_SUPPORT_EXT1_WAKEUP
1397 } else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_EXT1, RTC_EXT1_TRIG_EN)) {
1398 s_config.ext1_rtc_gpio_mask = 0;
1399 s_config.ext1_trigger_mode = 0;
1400 s_config.wakeup_triggers &= ~RTC_EXT1_TRIG_EN;
1401 #endif
1402 #if SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP
1403 } else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_TOUCHPAD, RTC_TOUCH_TRIG_EN)) {
1404 s_config.wakeup_triggers &= ~RTC_TOUCH_TRIG_EN;
1405 #endif
1406 } else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_GPIO, RTC_GPIO_TRIG_EN)) {
1407 s_config.wakeup_triggers &= ~RTC_GPIO_TRIG_EN;
1408 } else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_UART, (RTC_UART0_TRIG_EN | RTC_UART1_TRIG_EN))) {
1409 s_config.wakeup_triggers &= ~(RTC_UART0_TRIG_EN | RTC_UART1_TRIG_EN);
1410 }
1411 #if CONFIG_ULP_COPROC_TYPE_FSM
1412 else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_ULP, RTC_ULP_TRIG_EN)) {
1413 s_config.wakeup_triggers &= ~RTC_ULP_TRIG_EN;
1414 }
1415 #endif
1416 else {
1417 ESP_LOGE(TAG, "Incorrect wakeup source (%d) to disable.", (int) source);
1418 return ESP_ERR_INVALID_STATE;
1419 }
1420 return ESP_OK;
1421 }
1422
1423 esp_err_t esp_sleep_enable_ulp_wakeup(void)
1424 {
1425 #ifndef CONFIG_ULP_COPROC_ENABLED
1426 return ESP_ERR_INVALID_STATE;
1427 #endif // CONFIG_ULP_COPROC_ENABLED
1428 #if CONFIG_IDF_TARGET_ESP32
1429 #if ((defined CONFIG_RTC_EXT_CRYST_ADDIT_CURRENT) || (defined CONFIG_RTC_EXT_CRYST_ADDIT_CURRENT_V2))
1430 ESP_LOGE(TAG, "Failed to enable wakeup when provide current to external 32kHz crystal");
1431 return ESP_ERR_NOT_SUPPORTED;
1432 #endif
1433 if (s_config.wakeup_triggers & RTC_EXT0_TRIG_EN) {
1434 ESP_LOGE(TAG, "Conflicting wake-up trigger: ext0");
1435 return ESP_ERR_INVALID_STATE;
1436 }
1437 #endif //CONFIG_IDF_TARGET_ESP32
1438
1439 #if CONFIG_ULP_COPROC_TYPE_FSM
1440 s_config.wakeup_triggers |= RTC_ULP_TRIG_EN;
1441 return ESP_OK;
1442 #elif CONFIG_ULP_COPROC_TYPE_RISCV
1443 s_config.wakeup_triggers |= (RTC_COCPU_TRIG_EN | RTC_COCPU_TRAP_TRIG_EN);
1444 return ESP_OK;
1445 #elif CONFIG_ULP_COPROC_TYPE_LP_CORE
1446 s_config.wakeup_triggers |= RTC_LP_CORE_TRIG_EN;
1447 return ESP_OK;
1448 #else
1449 return ESP_ERR_NOT_SUPPORTED;
1450 #endif //CONFIG_ULP_COPROC_TYPE_FSM
1451 }
1452
1453 esp_err_t esp_sleep_enable_timer_wakeup(uint64_t time_in_us)
1454 {
1455 s_config.wakeup_triggers |= RTC_TIMER_TRIG_EN;
1456 s_config.sleep_duration = time_in_us;
1457 return ESP_OK;
1458 }
1459
1460 static esp_err_t timer_wakeup_prepare(int64_t sleep_duration)
1461 {
1462 if (sleep_duration < 0) {
1463 sleep_duration = 0;
1464 }
1465
1466 int64_t ticks = rtc_time_us_to_slowclk(sleep_duration, s_config.rtc_clk_cal_period);
1467 int64_t target_wakeup_tick = s_config.rtc_ticks_at_sleep_start + ticks;
1468
1469 #if SOC_LP_TIMER_SUPPORTED
1470 #if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
1471 // Last timer wake-up validity check
1472 if ((sleep_duration == 0) || \
1473 (target_wakeup_tick < rtc_time_get() + SLEEP_TIMER_ALARM_TO_SLEEP_TICKS)) {
1474 // Treat too short sleep duration setting as timer reject
1475 return ESP_ERR_SLEEP_REJECT;
1476 }
1477 #endif
1478 lp_timer_hal_set_alarm_target(0, target_wakeup_tick);
1479 #else
1480 rtc_hal_set_wakeup_timer(target_wakeup_tick);
1481 #endif
1482
1483 return ESP_OK;
1484 }
1485
1486 #if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
1487 /* In deep sleep mode, only the sleep channel is supported, and other touch channels should be turned off. */
1488 static void touch_wakeup_prepare(void)
1489 {
1490 uint16_t sleep_cycle = 0;
1491 uint16_t meas_times = 0;
1492 touch_pad_t touch_num = TOUCH_PAD_NUM0;
1493 touch_ll_sleep_get_channel_num(&touch_num); // Check if the sleep pad is enabled.
1494 if ((touch_num > TOUCH_PAD_NUM0) && (touch_num < TOUCH_PAD_MAX) && touch_ll_get_fsm_state()) {
1495 touch_ll_stop_fsm();
1496 touch_ll_clear_channel_mask(TOUCH_PAD_BIT_MASK_ALL);
1497 touch_ll_intr_clear(TOUCH_PAD_INTR_MASK_ALL); // Clear state from previous wakeup
1498 touch_hal_sleep_channel_get_work_time(&sleep_cycle, &meas_times);
1499 touch_ll_set_meas_times(meas_times);
1500 touch_ll_set_sleep_time(sleep_cycle);
1501 touch_ll_set_channel_mask(BIT(touch_num));
1502 touch_ll_start_fsm();
1503 }
1504 }
1505 #endif
1506
1507 #if SOC_TOUCH_SENSOR_SUPPORTED
1508
1509 esp_err_t esp_sleep_enable_touchpad_wakeup(void)
1510 {
1511 #if CONFIG_IDF_TARGET_ESP32
1512 #if ((defined CONFIG_RTC_EXT_CRYST_ADDIT_CURRENT) || (defined CONFIG_RTC_EXT_CRYST_ADDIT_CURRENT_V2))
1513 ESP_LOGE(TAG, "Failed to enable wakeup when provide current to external 32kHz crystal");
1514 return ESP_ERR_NOT_SUPPORTED;
1515 #endif
1516 if (s_config.wakeup_triggers & (RTC_EXT0_TRIG_EN)) {
1517 ESP_LOGE(TAG, "Conflicting wake-up trigger: ext0");
1518 return ESP_ERR_INVALID_STATE;
1519 }
1520 #endif //CONFIG_IDF_TARGET_ESP32
1521
1522 s_config.wakeup_triggers |= RTC_TOUCH_TRIG_EN;
1523 return ESP_OK;
1524 }
1525
1526 touch_pad_t esp_sleep_get_touchpad_wakeup_status(void)
1527 {
1528 if (esp_sleep_get_wakeup_cause() != ESP_SLEEP_WAKEUP_TOUCHPAD) {
1529 return TOUCH_PAD_MAX;
1530 }
1531 touch_pad_t pad_num;
1532 esp_err_t ret = touch_pad_get_wakeup_status(&pad_num); //TODO 723diff commit id:fda9ada1b
1533 assert(ret == ESP_OK && "wakeup reason is RTC_TOUCH_TRIG_EN but SENS_TOUCH_MEAS_EN is zero");
1534 return (ret == ESP_OK) ? pad_num : TOUCH_PAD_MAX;
1535 }
1536
1537 #endif // SOC_TOUCH_SENSOR_SUPPORTED
1538
1539 bool esp_sleep_is_valid_wakeup_gpio(gpio_num_t gpio_num)
1540 {
1541 #if SOC_RTCIO_PIN_COUNT > 0
1542 return RTC_GPIO_IS_VALID_GPIO(gpio_num);
1543 #else
1544 return GPIO_IS_DEEP_SLEEP_WAKEUP_VALID_GPIO(gpio_num);
1545 #endif
1546 }
1547
1548 #if SOC_PM_SUPPORT_EXT0_WAKEUP
1549 esp_err_t esp_sleep_enable_ext0_wakeup(gpio_num_t gpio_num, int level)
1550 {
1551 if (level < 0 || level > 1) {
1552 return ESP_ERR_INVALID_ARG;
1553 }
1554 if (!esp_sleep_is_valid_wakeup_gpio(gpio_num)) {
1555 return ESP_ERR_INVALID_ARG;
1556 }
1557 #if CONFIG_IDF_TARGET_ESP32
1558 if (s_config.wakeup_triggers & (RTC_TOUCH_TRIG_EN | RTC_ULP_TRIG_EN)) {
1559 ESP_LOGE(TAG, "Conflicting wake-up triggers: touch / ULP");
1560 return ESP_ERR_INVALID_STATE;
1561 }
1562 #endif //CONFIG_IDF_TARGET_ESP32
1563
1564 s_config.ext0_rtc_gpio_num = rtc_io_number_get(gpio_num);
1565 s_config.ext0_trigger_level = level;
1566 s_config.wakeup_triggers |= RTC_EXT0_TRIG_EN;
1567 return ESP_OK;
1568 }
1569
1570 static void ext0_wakeup_prepare(void)
1571 {
1572 int rtc_gpio_num = s_config.ext0_rtc_gpio_num;
1573 rtcio_hal_ext0_set_wakeup_pin(rtc_gpio_num, s_config.ext0_trigger_level);
1574 rtcio_hal_function_select(rtc_gpio_num, RTCIO_FUNC_RTC);
1575 rtcio_hal_input_enable(rtc_gpio_num);
1576 }
1577 #endif // SOC_PM_SUPPORT_EXT0_WAKEUP
1578
1579 #if SOC_PM_SUPPORT_EXT1_WAKEUP
1580 esp_err_t esp_sleep_enable_ext1_wakeup(uint64_t io_mask, esp_sleep_ext1_wakeup_mode_t level_mode)
1581 {
1582 if (io_mask == 0 && level_mode > ESP_EXT1_WAKEUP_ANY_HIGH) {
1583 return ESP_ERR_INVALID_ARG;
1584 }
1585 // Reset all EXT1 configs
1586 esp_sleep_disable_ext1_wakeup_io(0);
1587
1588 return esp_sleep_enable_ext1_wakeup_io(io_mask, level_mode);
1589 }
1590
1591
1592 esp_err_t esp_sleep_enable_ext1_wakeup_io(uint64_t io_mask, esp_sleep_ext1_wakeup_mode_t level_mode)
1593 {
1594 if (io_mask == 0 && level_mode > ESP_EXT1_WAKEUP_ANY_HIGH) {
1595 return ESP_ERR_INVALID_ARG;
1596 }
1597 // Translate bit map of GPIO numbers into the bit map of RTC IO numbers
1598 uint32_t rtc_gpio_mask = 0;
1599 for (int gpio = 0; io_mask; ++gpio, io_mask >>= 1) {
1600 if ((io_mask & 1) == 0) {
1601 continue;
1602 }
1603 if (!esp_sleep_is_valid_wakeup_gpio(gpio)) {
1604 ESP_LOGE(TAG, "Not an RTC IO: GPIO%d", gpio);
1605 return ESP_ERR_INVALID_ARG;
1606 }
1607 rtc_gpio_mask |= BIT(rtc_io_number_get(gpio));
1608 }
1609
1610 #if !SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN
1611 uint32_t ext1_rtc_gpio_mask = 0;
1612 uint32_t ext1_trigger_mode = 0;
1613
1614 ext1_rtc_gpio_mask = s_config.ext1_rtc_gpio_mask | rtc_gpio_mask;
1615 if (level_mode) {
1616 ext1_trigger_mode = s_config.ext1_trigger_mode | rtc_gpio_mask;
1617 } else {
1618 ext1_trigger_mode = s_config.ext1_trigger_mode & (~rtc_gpio_mask);
1619 }
1620 if (((ext1_rtc_gpio_mask & ext1_trigger_mode) != ext1_rtc_gpio_mask) &&
1621 ((ext1_rtc_gpio_mask & ext1_trigger_mode) != 0)) {
1622 return ESP_ERR_NOT_SUPPORTED;
1623 }
1624 #endif
1625
1626 s_config.ext1_rtc_gpio_mask |= rtc_gpio_mask;
1627 if (level_mode) {
1628 s_config.ext1_trigger_mode |= rtc_gpio_mask;
1629 } else {
1630 s_config.ext1_trigger_mode &= (~rtc_gpio_mask);
1631 }
1632 s_config.wakeup_triggers |= RTC_EXT1_TRIG_EN;
1633 return ESP_OK;
1634 }
1635
1636 esp_err_t esp_sleep_disable_ext1_wakeup_io(uint64_t io_mask)
1637 {
1638 if (io_mask == 0) {
1639 s_config.ext1_rtc_gpio_mask = 0;
1640 s_config.ext1_trigger_mode = 0;
1641 } else {
1642 // Translate bit map of GPIO numbers into the bit map of RTC IO numbers
1643 uint32_t rtc_gpio_mask = 0;
1644 for (int gpio = 0; io_mask; ++gpio, io_mask >>= 1) {
1645 if ((io_mask & 1) == 0) {
1646 continue;
1647 }
1648 if (!esp_sleep_is_valid_wakeup_gpio(gpio)) {
1649 ESP_LOGE(TAG, "Not an RTC IO Considering io_mask: GPIO%d", gpio);
1650 return ESP_ERR_INVALID_ARG;
1651 }
1652 rtc_gpio_mask |= BIT(rtc_io_number_get(gpio));
1653 }
1654 s_config.ext1_rtc_gpio_mask &= (~rtc_gpio_mask);
1655 s_config.ext1_trigger_mode &= (~rtc_gpio_mask);
1656 }
1657
1658 if (s_config.ext1_rtc_gpio_mask == 0) {
1659 s_config.wakeup_triggers &= (~RTC_EXT1_TRIG_EN);
1660 }
1661 return ESP_OK;
1662 }
1663
1664 #if SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN
1665 esp_err_t esp_sleep_enable_ext1_wakeup_with_level_mask(uint64_t io_mask, uint64_t level_mask)
1666 {
1667 if ((level_mask & io_mask) != level_mask) {
1668 return ESP_ERR_INVALID_ARG;
1669 }
1670 // Translate bit map of GPIO numbers into the bit map of RTC IO numbers
1671 // Translate bit map of GPIO wakeup mode into the bit map of RTC IO wakeup mode
1672 uint32_t rtc_gpio_mask = 0, rtc_gpio_wakeup_mode_mask = 0;
1673 for (int gpio = 0; io_mask; ++gpio, io_mask >>= 1, level_mask >>= 1) {
1674 if ((io_mask & 1) == 0) {
1675 continue;
1676 }
1677 if (!esp_sleep_is_valid_wakeup_gpio(gpio)) {
1678 ESP_LOGE(TAG, "Not an RTC IO Considering io_mask: GPIO%d", gpio);
1679 return ESP_ERR_INVALID_ARG;
1680 }
1681 rtc_gpio_mask |= BIT(rtc_io_number_get(gpio));
1682 if ((level_mask & 1) == 1) {
1683 rtc_gpio_wakeup_mode_mask |= BIT(rtc_io_number_get(gpio));
1684 }
1685 }
1686 s_config.ext1_rtc_gpio_mask = rtc_gpio_mask;
1687 s_config.ext1_trigger_mode = rtc_gpio_wakeup_mode_mask;
1688 s_config.wakeup_triggers |= RTC_EXT1_TRIG_EN;
1689 return ESP_OK;
1690 }
1691 #endif
1692
1693 static void ext1_wakeup_prepare(void)
1694 {
1695 // Configure all RTC IOs selected as ext1 wakeup inputs
1696 uint32_t rtc_gpio_mask = s_config.ext1_rtc_gpio_mask;
1697 for (int gpio = 0; gpio < GPIO_PIN_COUNT && rtc_gpio_mask != 0; ++gpio) {
1698 int rtc_pin = rtc_io_number_get(gpio);
1699 if ((rtc_gpio_mask & BIT(rtc_pin)) == 0) {
1700 continue;
1701 }
1702 #if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
1703 // Route pad to RTC
1704 rtcio_hal_function_select(rtc_pin, RTCIO_FUNC_RTC);
1705 // set input enable in sleep mode
1706 rtcio_hal_input_enable(rtc_pin);
1707 #if SOC_PM_SUPPORT_RTC_PERIPH_PD
1708 // Pad configuration depends on RTC_PERIPH state in sleep mode
1709 if (s_config.domain[ESP_PD_DOMAIN_RTC_PERIPH].pd_option != ESP_PD_OPTION_ON) {
1710 rtcio_hal_hold_enable(rtc_pin);
1711 }
1712 #endif
1713 #else
1714 /* ESP32H2 use hp iomux to config rtcio, and there is no complete
1715 * rtcio functionality. In the case of EXT1 wakeup, rtcio only provides
1716 * a pathway to EXT1. */
1717
1718 // Route pad to DIGITAL
1719 rtcio_hal_function_select(rtc_pin, RTCIO_FUNC_DIGITAL);
1720 // set input enable
1721 gpio_ll_input_enable(&GPIO, gpio);
1722 // hold rtc_pin to use it during sleep state
1723 rtcio_hal_hold_enable(rtc_pin);
1724 #endif
1725 // Keep track of pins which are processed to bail out early
1726 rtc_gpio_mask &= ~BIT(rtc_pin);
1727 }
1728
1729 // Clear state from previous wakeup
1730 rtc_hal_ext1_clear_wakeup_status();
1731 // Set RTC IO pins and mode to be used for wakeup
1732 rtc_hal_ext1_set_wakeup_pins(s_config.ext1_rtc_gpio_mask, s_config.ext1_trigger_mode);
1733 }
1734
1735 uint64_t esp_sleep_get_ext1_wakeup_status(void)
1736 {
1737 if (esp_sleep_get_wakeup_cause() != ESP_SLEEP_WAKEUP_EXT1) {
1738 return 0;
1739 }
1740 uint32_t status = rtc_hal_ext1_get_wakeup_status();
1741 // Translate bit map of RTC IO numbers into the bit map of GPIO numbers
1742 uint64_t gpio_mask = 0;
1743 for (int gpio = 0; gpio < GPIO_PIN_COUNT; ++gpio) {
1744 if (!esp_sleep_is_valid_wakeup_gpio(gpio)) {
1745 continue;
1746 }
1747 int rtc_pin = rtc_io_number_get(gpio);
1748 if ((status & BIT(rtc_pin)) == 0) {
1749 continue;
1750 }
1751 gpio_mask |= 1ULL << gpio;
1752 }
1753 return gpio_mask;
1754 }
1755
1756 #endif // SOC_PM_SUPPORT_EXT1_WAKEUP
1757
1758 #if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
1759 uint64_t esp_sleep_get_gpio_wakeup_status(void)
1760 {
1761 if (esp_sleep_get_wakeup_cause() != ESP_SLEEP_WAKEUP_GPIO) {
1762 return 0;
1763 }
1764 return rtc_hal_gpio_get_wakeup_status();
1765 }
1766
1767 static void gpio_deep_sleep_wakeup_prepare(void)
1768 {
1769 for (gpio_num_t gpio_idx = GPIO_NUM_0; gpio_idx < GPIO_NUM_MAX; gpio_idx++) {
1770 if (((1ULL << gpio_idx) & s_config.gpio_wakeup_mask) == 0) {
1771 continue;
1772 }
1773 #if CONFIG_ESP_SLEEP_GPIO_ENABLE_INTERNAL_RESISTORS
1774 if (s_config.gpio_trigger_mode & BIT(gpio_idx)) {
1775 ESP_ERROR_CHECK(gpio_pullup_dis(gpio_idx));
1776 ESP_ERROR_CHECK(gpio_pulldown_en(gpio_idx));
1777 } else {
1778 ESP_ERROR_CHECK(gpio_pullup_en(gpio_idx));
1779 ESP_ERROR_CHECK(gpio_pulldown_dis(gpio_idx));
1780 }
1781 #endif
1782 ESP_ERROR_CHECK(gpio_hold_en(gpio_idx));
1783 }
1784 // Clear state from previous wakeup
1785 rtc_hal_gpio_clear_wakeup_status();
1786 }
1787
1788 esp_err_t esp_deep_sleep_enable_gpio_wakeup(uint64_t gpio_pin_mask, esp_deepsleep_gpio_wake_up_mode_t mode)
1789 {
1790 if (mode > ESP_GPIO_WAKEUP_GPIO_HIGH) {
1791 ESP_LOGE(TAG, "invalid mode");
1792 return ESP_ERR_INVALID_ARG;
1793 }
1794 gpio_int_type_t intr_type = ((mode == ESP_GPIO_WAKEUP_GPIO_LOW) ? GPIO_INTR_LOW_LEVEL : GPIO_INTR_HIGH_LEVEL);
1795 esp_err_t err = ESP_OK;
1796 for (gpio_num_t gpio_idx = GPIO_NUM_0; gpio_idx < GPIO_NUM_MAX; gpio_idx++, gpio_pin_mask >>= 1) {
1797 if ((gpio_pin_mask & 1) == 0) {
1798 continue;
1799 }
1800 if (!esp_sleep_is_valid_wakeup_gpio(gpio_idx)) {
1801 ESP_LOGE(TAG, "gpio %d is an invalid deep sleep wakeup IO", gpio_idx);
1802 return ESP_ERR_INVALID_ARG;
1803 }
1804 err = gpio_deep_sleep_wakeup_enable(gpio_idx, intr_type);
1805
1806 s_config.gpio_wakeup_mask |= BIT(gpio_idx);
1807 if (mode == ESP_GPIO_WAKEUP_GPIO_HIGH) {
1808 s_config.gpio_trigger_mode |= (mode << gpio_idx);
1809 } else {
1810 s_config.gpio_trigger_mode &= ~(mode << gpio_idx);
1811 }
1812 }
1813 s_config.wakeup_triggers |= RTC_GPIO_TRIG_EN;
1814 return err;
1815 }
1816
1817 #endif //SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
1818
1819 esp_err_t esp_sleep_enable_gpio_wakeup(void)
1820 {
1821 #if CONFIG_IDF_TARGET_ESP32
1822 if (s_config.wakeup_triggers & (RTC_TOUCH_TRIG_EN | RTC_ULP_TRIG_EN)) {
1823 ESP_LOGE(TAG, "Conflicting wake-up triggers: touch / ULP");
1824 return ESP_ERR_INVALID_STATE;
1825 }
1826 #endif
1827 s_config.wakeup_triggers |= RTC_GPIO_TRIG_EN;
1828 return ESP_OK;
1829 }
1830
1831 esp_err_t esp_sleep_enable_uart_wakeup(int uart_num)
1832 {
1833 if (uart_num == UART_NUM_0) {
1834 s_config.wakeup_triggers |= RTC_UART0_TRIG_EN;
1835 } else if (uart_num == UART_NUM_1) {
1836 s_config.wakeup_triggers |= RTC_UART1_TRIG_EN;
1837 } else {
1838 return ESP_ERR_INVALID_ARG;
1839 }
1840
1841 return ESP_OK;
1842 }
1843
1844 esp_err_t esp_sleep_enable_wifi_wakeup(void)
1845 {
1846 #if SOC_PM_SUPPORT_WIFI_WAKEUP
1847 s_config.wakeup_triggers |= RTC_WIFI_TRIG_EN;
1848 return ESP_OK;
1849 #else
1850 return ESP_ERR_NOT_SUPPORTED;
1851 #endif
1852 }
1853
1854 esp_err_t esp_sleep_disable_wifi_wakeup(void)
1855 {
1856 #if SOC_PM_SUPPORT_WIFI_WAKEUP
1857 s_config.wakeup_triggers &= (~RTC_WIFI_TRIG_EN);
1858 return ESP_OK;
1859 #else
1860 return ESP_ERR_NOT_SUPPORTED;
1861 #endif
1862 }
1863
1864 esp_err_t esp_sleep_enable_wifi_beacon_wakeup(void)
1865 {
1866 #if SOC_PM_SUPPORT_BEACON_WAKEUP
1867 s_config.wakeup_triggers |= PMU_WIFI_BEACON_WAKEUP_EN;
1868 return ESP_OK;
1869 #else
1870 return ESP_ERR_NOT_SUPPORTED;
1871 #endif
1872 }
1873
1874 esp_err_t esp_sleep_disable_wifi_beacon_wakeup(void)
1875 {
1876 #if SOC_PM_SUPPORT_BEACON_WAKEUP
1877 s_config.wakeup_triggers &= (~PMU_WIFI_BEACON_WAKEUP_EN);
1878 return ESP_OK;
1879 #else
1880 return ESP_ERR_NOT_SUPPORTED;
1881 #endif
1882 }
1883
1884 esp_err_t esp_sleep_enable_bt_wakeup(void)
1885 {
1886 #if SOC_PM_SUPPORT_BT_WAKEUP
1887 s_config.wakeup_triggers |= RTC_BT_TRIG_EN;
1888 return ESP_OK;
1889 #else
1890 return ESP_ERR_NOT_SUPPORTED;
1891 #endif
1892 }
1893
1894 esp_err_t esp_sleep_disable_bt_wakeup(void)
1895 {
1896 #if SOC_PM_SUPPORT_BT_WAKEUP
1897 s_config.wakeup_triggers &= (~RTC_BT_TRIG_EN);
1898 return ESP_OK;
1899 #else
1900 return ESP_ERR_NOT_SUPPORTED;
1901 #endif
1902 }
1903
1904 esp_sleep_wakeup_cause_t esp_sleep_get_wakeup_cause(void)
1905 {
1906 if (esp_rom_get_reset_reason(0) != RESET_REASON_CORE_DEEP_SLEEP && !s_light_sleep_wakeup) {
1907 return ESP_SLEEP_WAKEUP_UNDEFINED;
1908 }
1909
1910 #if SOC_PMU_SUPPORTED
1911 uint32_t wakeup_cause = pmu_ll_hp_get_wakeup_cause(&PMU);
1912 #else
1913 uint32_t wakeup_cause = rtc_cntl_ll_get_wakeup_cause();
1914 #endif
1915
1916 if (wakeup_cause & RTC_TIMER_TRIG_EN) {
1917 return ESP_SLEEP_WAKEUP_TIMER;
1918 } else if (wakeup_cause & RTC_GPIO_TRIG_EN) {
1919 return ESP_SLEEP_WAKEUP_GPIO;
1920 } else if (wakeup_cause & (RTC_UART0_TRIG_EN | RTC_UART1_TRIG_EN)) {
1921 return ESP_SLEEP_WAKEUP_UART;
1922 #if SOC_PM_SUPPORT_EXT0_WAKEUP
1923 } else if (wakeup_cause & RTC_EXT0_TRIG_EN) {
1924 return ESP_SLEEP_WAKEUP_EXT0;
1925 #endif
1926 #if SOC_PM_SUPPORT_EXT1_WAKEUP
1927 } else if (wakeup_cause & RTC_EXT1_TRIG_EN) {
1928 return ESP_SLEEP_WAKEUP_EXT1;
1929 #endif
1930 #if SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP
1931 } else if (wakeup_cause & RTC_TOUCH_TRIG_EN) {
1932 return ESP_SLEEP_WAKEUP_TOUCHPAD;
1933 #endif
1934 #if SOC_ULP_FSM_SUPPORTED
1935 } else if (wakeup_cause & RTC_ULP_TRIG_EN) {
1936 return ESP_SLEEP_WAKEUP_ULP;
1937 #endif
1938 #if SOC_PM_SUPPORT_WIFI_WAKEUP
1939 } else if (wakeup_cause & RTC_WIFI_TRIG_EN) {
1940 return ESP_SLEEP_WAKEUP_WIFI;
1941 #endif
1942 #if SOC_PM_SUPPORT_BT_WAKEUP
1943 } else if (wakeup_cause & RTC_BT_TRIG_EN) {
1944 return ESP_SLEEP_WAKEUP_BT;
1945 #endif
1946 #if SOC_RISCV_COPROC_SUPPORTED
1947 } else if (wakeup_cause & RTC_COCPU_TRIG_EN) {
1948 return ESP_SLEEP_WAKEUP_ULP;
1949 } else if (wakeup_cause & RTC_COCPU_TRAP_TRIG_EN) {
1950 return ESP_SLEEP_WAKEUP_COCPU_TRAP_TRIG;
1951 #endif
1952 #if SOC_LP_CORE_SUPPORTED
1953 } else if (wakeup_cause & RTC_LP_CORE_TRIG_EN) {
1954 return ESP_SLEEP_WAKEUP_ULP;
1955 #endif
1956 } else {
1957 return ESP_SLEEP_WAKEUP_UNDEFINED;
1958 }
1959 }
1960
1961 esp_err_t esp_sleep_pd_config(esp_sleep_pd_domain_t domain, esp_sleep_pd_option_t option)
1962 {
1963 if (domain >= ESP_PD_DOMAIN_MAX || option > ESP_PD_OPTION_AUTO) {
1964 return ESP_ERR_INVALID_ARG;
1965 }
1966 s_config.lock = irq_lock();
1967
1968 int refs = (option == ESP_PD_OPTION_ON) ? s_config.domain[domain].refs++ \
1969 : (option == ESP_PD_OPTION_OFF) ? --s_config.domain[domain].refs \
1970 : s_config.domain[domain].refs;
1971 if (refs == 0) {
1972 s_config.domain[domain].pd_option = option;
1973 }
1974 irq_unlock(s_config.lock);
1975 assert(refs >= 0);
1976 return ESP_OK;
1977 }
1978
1979 /**
1980 * The modules in the CPU and modem power domains still depend on the top power domain.
1981 * To be safe, the CPU and Modem power domains must also be powered off and saved when
1982 * the TOP is powered off. If not power down XTAL, power down TOP is meaningless, and
1983 * the XTAL clock control of some chips(esp32c6/esp32h2) depends on the top domain.
1984 */
1985 #if SOC_PM_SUPPORT_TOP_PD
1986 static inline bool top_domain_pd_allowed(void) {
1987 return (cpu_domain_pd_allowed() && \
1988 clock_domain_pd_allowed() && \
1989 peripheral_domain_pd_allowed() && \
1990 modem_domain_pd_allowed() && \
1991 s_config.domain[ESP_PD_DOMAIN_XTAL].pd_option != ESP_PD_OPTION_ON);
1992 }
1993 #endif
1994
1995 static uint32_t get_power_down_flags(void)
1996 {
1997 // Where needed, convert AUTO options to ON. Later interpret AUTO as OFF.
1998
1999 // RTC_SLOW_MEM is needed for the ULP, so keep RTC_SLOW_MEM powered up if ULP
2000 // is used and RTC_SLOW_MEM is Auto.
2001 // If there is any data placed into .rtc.data or .rtc.bss segments, and
2002 // RTC_SLOW_MEM is Auto, keep it powered up as well.
2003
2004 #if SOC_PM_SUPPORT_RTC_SLOW_MEM_PD && SOC_ULP_SUPPORTED && !CONFIG_SOC_ESP32_APPCPU && !CONFIG_SOC_ESP32S3_APPCPU
2005 // Labels are defined in the linker script
2006 extern int _rtc_slow_length;
2007 int _rtc_reserved_length = 0;
2008 /**
2009 * Compiler considers "(size_t) &_rtc_slow_length > 0" to always be true.
2010 * So use a volatile variable to prevent compiler from doing this optimization.
2011 */
2012 volatile size_t rtc_slow_mem_used = (size_t)&_rtc_slow_length + (size_t)&_rtc_reserved_length;
2013
2014 if ((s_config.domain[ESP_PD_DOMAIN_RTC_SLOW_MEM].pd_option == ESP_PD_OPTION_AUTO) &&
2015 (rtc_slow_mem_used > 0 || (s_config.wakeup_triggers & RTC_ULP_TRIG_EN))) {
2016 s_config.domain[ESP_PD_DOMAIN_RTC_SLOW_MEM].pd_option = ESP_PD_OPTION_ON;
2017 }
2018 #endif
2019
2020 #if SOC_PM_SUPPORT_RTC_FAST_MEM_PD
2021 #if !CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
2022 /* RTC_FAST_MEM is needed for deep sleep stub.
2023 If RTC_FAST_MEM is Auto, keep it powered on, so that deep sleep stub can run.
2024 In the new chip revision, deep sleep stub will be optional, and this can be changed. */
2025 if (s_config.domain[ESP_PD_DOMAIN_RTC_FAST_MEM].pd_option == ESP_PD_OPTION_AUTO) {
2026 s_config.domain[ESP_PD_DOMAIN_RTC_FAST_MEM].pd_option = ESP_PD_OPTION_ON;
2027 }
2028 #else
2029 /* If RTC_FAST_MEM is used for heap, force RTC_FAST_MEM to be powered on. */
2030 s_config.domain[ESP_PD_DOMAIN_RTC_FAST_MEM].pd_option = ESP_PD_OPTION_ON;
2031 #endif
2032 #endif
2033
2034 #if SOC_PM_SUPPORT_RTC_PERIPH_PD
2035 // RTC_PERIPH is needed for EXT0 wakeup and GPIO wakeup.
2036 // If RTC_PERIPH is left auto (EXT0/GPIO aren't enabled), RTC_PERIPH will be powered off by default.
2037 if (s_config.domain[ESP_PD_DOMAIN_RTC_PERIPH].pd_option == ESP_PD_OPTION_AUTO) {
2038 if (s_config.wakeup_triggers & (RTC_EXT0_TRIG_EN | RTC_GPIO_TRIG_EN)) {
2039 s_config.domain[ESP_PD_DOMAIN_RTC_PERIPH].pd_option = ESP_PD_OPTION_ON;
2040 }
2041 #if CONFIG_IDF_TARGET_ESP32
2042 else if (s_config.wakeup_triggers & (RTC_TOUCH_TRIG_EN | RTC_ULP_TRIG_EN)) {
2043 // On ESP32, forcing power up of RTC_PERIPH
2044 // prevents ULP timer and touch FSMs from working correctly.
2045 s_config.domain[ESP_PD_DOMAIN_RTC_PERIPH].pd_option = ESP_PD_OPTION_OFF;
2046 }
2047 #endif //CONFIG_IDF_TARGET_ESP32
2048 #if SOC_LP_CORE_SUPPORTED
2049 else if (s_config.wakeup_triggers & RTC_LP_CORE_TRIG_EN) {
2050 // Need to keep RTC_PERIPH on to allow lp core to wakeup during sleep (e.g. from lp timer)
2051 s_config.domain[ESP_PD_DOMAIN_RTC_PERIPH].pd_option = ESP_PD_OPTION_ON;
2052 }
2053 #endif //CONFIG_IDF_TARGET_ESP32
2054 }
2055 #endif // SOC_PM_SUPPORT_RTC_PERIPH_PD
2056
2057 /**
2058 * VDD_SDIO power domain shall be kept on during the light sleep
2059 * when CONFIG_ESP_SLEEP_POWER_DOWN_FLASH is not set and off when it is set.
2060 * The application can still force the power domain to remain on by calling
2061 * `esp_sleep_pd_config` before getting into light sleep mode.
2062 *
2063 * In deep sleep mode, the power domain will be turned off, regardless the
2064 * value of this field.
2065 */
2066 #if SOC_PM_SUPPORT_VDDSDIO_PD
2067 if (s_config.domain[ESP_PD_DOMAIN_VDDSDIO].pd_option == ESP_PD_OPTION_AUTO) {
2068 #ifndef CONFIG_ESP_SLEEP_POWER_DOWN_FLASH
2069 s_config.domain[ESP_PD_DOMAIN_VDDSDIO].pd_option = ESP_PD_OPTION_ON;
2070 #endif
2071 }
2072 #endif
2073
2074 #ifdef CONFIG_IDF_TARGET_ESP32
2075 s_config.domain[ESP_PD_DOMAIN_XTAL].pd_option = ESP_PD_OPTION_OFF;
2076 #endif
2077
2078 const __attribute__((unused)) char *option_str[] = {"OFF", "ON", "AUTO(OFF)" /* Auto works as OFF */};
2079 /* This function is called from a critical section, log with ESP_EARLY_LOGD. */
2080 #if SOC_PM_SUPPORT_RTC_PERIPH_PD
2081 ESP_EARLY_LOGD(TAG, "RTC_PERIPH: %s", option_str[s_config.domain[ESP_PD_DOMAIN_RTC_PERIPH].pd_option]);
2082 #endif
2083 #if SOC_PM_SUPPORT_RTC_SLOW_MEM_PD
2084 ESP_EARLY_LOGD(TAG, "RTC_SLOW_MEM: %s", option_str[s_config.domain[ESP_PD_DOMAIN_RTC_SLOW_MEM].pd_option]);
2085 #endif
2086 #if SOC_PM_SUPPORT_RTC_FAST_MEM_PD
2087 ESP_EARLY_LOGD(TAG, "RTC_FAST_MEM: %s", option_str[s_config.domain[ESP_PD_DOMAIN_RTC_FAST_MEM].pd_option]);
2088 #endif
2089
2090 // Prepare flags based on the selected options
2091 uint32_t pd_flags = 0;
2092 #if SOC_PM_SUPPORT_RTC_FAST_MEM_PD
2093 if (s_config.domain[ESP_PD_DOMAIN_RTC_FAST_MEM].pd_option != ESP_PD_OPTION_ON) {
2094 pd_flags |= RTC_SLEEP_PD_RTC_FAST_MEM;
2095 }
2096 #endif
2097 #if SOC_PM_SUPPORT_RTC_SLOW_MEM_PD
2098 if (s_config.domain[ESP_PD_DOMAIN_RTC_SLOW_MEM].pd_option != ESP_PD_OPTION_ON) {
2099 pd_flags |= RTC_SLEEP_PD_RTC_SLOW_MEM;
2100 }
2101 #endif
2102 #if SOC_PM_SUPPORT_RTC_PERIPH_PD
2103 if (s_config.domain[ESP_PD_DOMAIN_RTC_PERIPH].pd_option != ESP_PD_OPTION_ON) {
2104 pd_flags |= RTC_SLEEP_PD_RTC_PERIPH;
2105 }
2106 #endif
2107
2108 #if SOC_PM_SUPPORT_CPU_PD
2109 if ((s_config.domain[ESP_PD_DOMAIN_CPU].pd_option != ESP_PD_OPTION_ON) && cpu_domain_pd_allowed()) {
2110 pd_flags |= RTC_SLEEP_PD_CPU;
2111 }
2112 #endif
2113 #if SOC_PM_SUPPORT_XTAL32K_PD
2114 if (s_config.domain[ESP_PD_DOMAIN_XTAL32K].pd_option != ESP_PD_OPTION_ON) {
2115 pd_flags |= PMU_SLEEP_PD_XTAL32K;
2116 }
2117 #endif
2118 #if SOC_PM_SUPPORT_RC32K_PD
2119 if (s_config.domain[ESP_PD_DOMAIN_RC32K].pd_option != ESP_PD_OPTION_ON) {
2120 pd_flags |= PMU_SLEEP_PD_RC32K;
2121 }
2122 #endif
2123 #if SOC_PM_SUPPORT_RC_FAST_PD
2124 if (s_config.domain[ESP_PD_DOMAIN_RC_FAST].pd_option != ESP_PD_OPTION_ON) {
2125 pd_flags |= RTC_SLEEP_PD_INT_8M;
2126 }
2127 #endif
2128 if (s_config.domain[ESP_PD_DOMAIN_XTAL].pd_option != ESP_PD_OPTION_ON) {
2129 pd_flags |= RTC_SLEEP_PD_XTAL;
2130 }
2131 #if SOC_PM_SUPPORT_TOP_PD
2132 if ((s_config.domain[ESP_PD_DOMAIN_TOP].pd_option != ESP_PD_OPTION_ON) && top_domain_pd_allowed()) {
2133 pd_flags |= PMU_SLEEP_PD_TOP;
2134 }
2135 #endif
2136
2137 #if SOC_PM_SUPPORT_MODEM_PD
2138 if ((s_config.domain[ESP_PD_DOMAIN_MODEM].pd_option != ESP_PD_OPTION_ON) && modem_domain_pd_allowed()
2139 #if SOC_PM_MODEM_RETENTION_BY_REGDMA
2140 && clock_domain_pd_allowed()
2141 #endif
2142 ) {
2143 pd_flags |= RTC_SLEEP_PD_MODEM;
2144 }
2145 #endif
2146
2147 #if SOC_PM_SUPPORT_VDDSDIO_PD
2148 if (s_config.domain[ESP_PD_DOMAIN_VDDSDIO].pd_option != ESP_PD_OPTION_ON) {
2149 pd_flags |= RTC_SLEEP_PD_VDDSDIO;
2150 }
2151 #endif
2152
2153 #if ((defined CONFIG_RTC_CLK_SRC_EXT_CRYS) && (defined CONFIG_RTC_EXT_CRYST_ADDIT_CURRENT) && (SOC_PM_SUPPORT_RTC_PERIPH_PD))
2154 if ((s_config.wakeup_triggers & (RTC_TOUCH_TRIG_EN | RTC_ULP_TRIG_EN)) == 0) {
2155 // If enabled EXT1 only and enable the additional current by touch, should be keep RTC_PERIPH power on.
2156 pd_flags &= ~RTC_SLEEP_PD_RTC_PERIPH;
2157 }
2158 #endif
2159
2160 return pd_flags;
2161 }
2162
2163 #if CONFIG_IDF_TARGET_ESP32
2164 /* APP core of esp32 can't access to RTC FAST MEMORY, do not define it with RTC_IRAM_ATTR */
2165 void
2166 #else
2167 void RTC_IRAM_ATTR
2168 #endif
2169 esp_deep_sleep_disable_rom_logging(void)
2170 {
2171 rtc_suppress_rom_log();
2172 }
2173
2174 void esp_sleep_enable_adc_tsens_monitor(bool enable)
2175 {
2176 s_adc_tsen_enabled = enable;
2177 }
2178
2179 void rtc_sleep_enable_ultra_low(bool enable)
2180 {
2181 s_ultra_low_enabled = enable;
2182 }
2183
