Searched refs:ibus_mask (Results 1 – 6 of 6) sorted by relevance
| /hal_espressif-latest/components/hal/esp32s2/include/hal/ |
| D | cache_ll.h | 115 uint32_t ibus_mask = 0; in cache_ll_l1_enable_bus() local
116 ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_PRO_ICACHE_MASK_IRAM0 : 0; in cache_ll_l1_enable_bus()
117 ibus_mask |= (mask & CACHE_BUS_IBUS1) ? EXTMEM_PRO_ICACHE_MASK_IRAM1 : 0; in cache_ll_l1_enable_bus()
118 ibus_mask |= (mask & CACHE_BUS_IBUS2) ? EXTMEM_PRO_ICACHE_MASK_DROM0 : 0; in cache_ll_l1_enable_bus()
119 REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, ibus_mask); in cache_ll_l1_enable_bus()
139 uint32_t ibus_mask = 0; in cache_ll_l1_disable_bus() local
140 ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_PRO_ICACHE_MASK_IRAM0 : 0; in cache_ll_l1_disable_bus()
141 ibus_mask |= (mask & CACHE_BUS_IBUS1) ? EXTMEM_PRO_ICACHE_MASK_IRAM1 : 0; in cache_ll_l1_disable_bus()
142 ibus_mask |= (mask & CACHE_BUS_IBUS2) ? EXTMEM_PRO_ICACHE_MASK_DROM0 : 0; in cache_ll_l1_disable_bus()
143 REG_SET_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, ibus_mask); in cache_ll_l1_disable_bus()
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| /hal_espressif-latest/components/hal/esp32s3/include/hal/ |
| D | cache_ll.h | 110 uint32_t ibus_mask = 0; in cache_ll_l1_enable_bus() local
112 ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE0_BUS : 0; in cache_ll_l1_enable_bus()
114 ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE1_BUS : 0; in cache_ll_l1_enable_bus()
116 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask); in cache_ll_l1_enable_bus()
141 uint32_t ibus_mask = REG_READ(EXTMEM_ICACHE_CTRL1_REG); in cache_ll_l1_get_enabled_bus() local
143 mask |= (!(ibus_mask & EXTMEM_ICACHE_SHUT_CORE0_BUS)) ? CACHE_BUS_IBUS0 : 0; in cache_ll_l1_get_enabled_bus()
145 mask |= (!(ibus_mask & EXTMEM_ICACHE_SHUT_CORE1_BUS)) ? CACHE_BUS_IBUS0 : 0; in cache_ll_l1_get_enabled_bus()
171 uint32_t ibus_mask = 0; in cache_ll_l1_disable_bus() local
173 ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE0_BUS : 0; in cache_ll_l1_disable_bus()
175 ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE1_BUS : 0; in cache_ll_l1_disable_bus()
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| /hal_espressif-latest/components/hal/esp32h2/include/hal/ |
| D | cache_ll.h | 72 uint32_t ibus_mask = 0; in cache_ll_l1_enable_bus() local
73 ibus_mask |= (mask & CACHE_BUS_IBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0; in cache_ll_l1_enable_bus()
74 REG_CLR_BIT(CACHE_L1_CACHE_CTRL_REG, ibus_mask); in cache_ll_l1_enable_bus()
94 uint32_t ibus_mask = 0; in cache_ll_l1_disable_bus() local
95 ibus_mask |= (mask & CACHE_BUS_IBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0; in cache_ll_l1_disable_bus()
96 REG_SET_BIT(CACHE_L1_CACHE_CTRL_REG, ibus_mask); in cache_ll_l1_disable_bus()
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| /hal_espressif-latest/components/hal/esp32c6/include/hal/ |
| D | cache_ll.h | 72 uint32_t ibus_mask = 0; in cache_ll_l1_enable_bus() local
73 ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_L1_CACHE_SHUT_IBUS : 0; in cache_ll_l1_enable_bus()
74 REG_CLR_BIT(EXTMEM_L1_CACHE_CTRL_REG, ibus_mask); in cache_ll_l1_enable_bus()
94 uint32_t ibus_mask = 0; in cache_ll_l1_disable_bus() local
95 ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_L1_CACHE_SHUT_IBUS : 0; in cache_ll_l1_disable_bus()
96 REG_SET_BIT(EXTMEM_L1_CACHE_CTRL_REG, ibus_mask); in cache_ll_l1_disable_bus()
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| /hal_espressif-latest/components/hal/esp32c2/include/hal/ |
| D | cache_ll.h | 98 uint32_t ibus_mask = 0; in cache_ll_l1_enable_bus() local
99 ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0; in cache_ll_l1_enable_bus()
100 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask); in cache_ll_l1_enable_bus()
120 uint32_t ibus_mask = 0; in cache_ll_l1_disable_bus() local
121 ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0; in cache_ll_l1_disable_bus()
122 REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask); in cache_ll_l1_disable_bus()
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| /hal_espressif-latest/components/hal/esp32c3/include/hal/ |
| D | cache_ll.h | 99 uint32_t ibus_mask = 0; in cache_ll_l1_enable_bus() local
100 ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0; in cache_ll_l1_enable_bus()
101 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask); in cache_ll_l1_enable_bus()
121 uint32_t ibus_mask = 0; in cache_ll_l1_disable_bus() local
122 ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0; in cache_ll_l1_disable_bus()
123 REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask); in cache_ll_l1_disable_bus()
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