1 /*
2 * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <stdlib.h>
8 #include <string.h>
9 #include <sys/param.h> // For MIN/MAX
10 #include "spi_flash_chip_generic.h"
11 #include "spi_flash_defs.h"
12 #include "hal/spi_flash_encrypt_hal.h"
13 #include "esp_log.h"
14 #include "esp_attr.h"
15 #include "esp_private/spi_flash_os.h"
16 #include "esp_rom_caps.h"
17
18 typedef struct flash_chip_dummy {
19 uint8_t dio_dummy_bitlen;
20 uint8_t qio_dummy_bitlen;
21 uint8_t qout_dummy_bitlen;
22 uint8_t dout_dummy_bitlen;
23 uint8_t fastrd_dummy_bitlen;
24 uint8_t slowrd_dummy_bitlen;
25 } flash_chip_dummy_t;
26
27 // These parameters can be placed in the ROM. For now we use the code in IDF.
28 DRAM_ATTR const static flash_chip_dummy_t default_flash_chip_dummy = {
29 .dio_dummy_bitlen = SPI_FLASH_DIO_DUMMY_BITLEN,
30 .qio_dummy_bitlen = SPI_FLASH_QIO_DUMMY_BITLEN,
31 .qout_dummy_bitlen = SPI_FLASH_QOUT_DUMMY_BITLEN,
32 .dout_dummy_bitlen = SPI_FLASH_DOUT_DUMMY_BITLEN,
33 .fastrd_dummy_bitlen = SPI_FLASH_FASTRD_DUMMY_BITLEN,
34 .slowrd_dummy_bitlen = SPI_FLASH_SLOWRD_DUMMY_BITLEN,
35 };
36
37 DRAM_ATTR const static flash_chip_dummy_t hpm_flash_chip_dummy = {
38 .dio_dummy_bitlen = SPI_FLASH_DIO_HPM_DUMMY_BITLEN,
39 .qio_dummy_bitlen = SPI_FLASH_QIO_HPM_DUMMY_BITLEN,
40 .qout_dummy_bitlen = SPI_FLASH_QOUT_DUMMY_BITLEN,
41 .dout_dummy_bitlen = SPI_FLASH_DOUT_DUMMY_BITLEN,
42 .fastrd_dummy_bitlen = SPI_FLASH_FASTRD_DUMMY_BITLEN,
43 .slowrd_dummy_bitlen = SPI_FLASH_SLOWRD_DUMMY_BITLEN,
44 };
45
46
47 DRAM_ATTR flash_chip_dummy_t *rom_flash_chip_dummy = (flash_chip_dummy_t *)&default_flash_chip_dummy;
48
49 DRAM_ATTR flash_chip_dummy_t *rom_flash_chip_dummy_hpm = (flash_chip_dummy_t *)&hpm_flash_chip_dummy;
50
51 // These are the pointer to HW flash encryption. Default using hardware encryption.
52 DRAM_ATTR static spi_flash_encryption_t esp_flash_encryption_default __attribute__((__unused__)) = {
53 .flash_encryption_enable = spi_flash_encryption_hal_enable,
54 .flash_encryption_disable = spi_flash_encryption_hal_disable,
55 .flash_encryption_data_prepare = spi_flash_encryption_hal_prepare,
56 .flash_encryption_done = spi_flash_encryption_hal_done,
57 .flash_encryption_destroy = spi_flash_encryption_hal_destroy,
58 .flash_encryption_check = spi_flash_encryption_hal_check,
59 };
60
61 #define SPI_FLASH_DEFAULT_IDLE_TIMEOUT_MS 200
62 #define SPI_FLASH_GENERIC_CHIP_ERASE_TIMEOUT_MS 4000
63 #define SPI_FLASH_GENERIC_SECTOR_ERASE_TIMEOUT_MS 600 //according to GD25Q127(125°) + 100ms
64 #define SPI_FLASH_GENERIC_BLOCK_ERASE_TIMEOUT_MS 4100 //according to GD25Q127(125°) + 100ms
65 #define SPI_FLASH_GENERIC_PAGE_PROGRAM_TIMEOUT_MS 500
66
67 #define HOST_DELAY_INTERVAL_US 1
68 #define CHIP_WAIT_IDLE_INTERVAL_US 20
69
70 #define SPI_FLASH_LINEAR_DENSITY_LAST_VALUE (0x19)
71 #define SPI_FLASH_HEX_A_F_RANGE (6)
72
73 const DRAM_ATTR flash_chip_op_timeout_t spi_flash_chip_generic_timeout = {
74 .idle_timeout = SPI_FLASH_DEFAULT_IDLE_TIMEOUT_MS * 1000,
75 .chip_erase_timeout = SPI_FLASH_GENERIC_CHIP_ERASE_TIMEOUT_MS * 1000,
76 .block_erase_timeout = SPI_FLASH_GENERIC_BLOCK_ERASE_TIMEOUT_MS * 1000,
77 .sector_erase_timeout = SPI_FLASH_GENERIC_SECTOR_ERASE_TIMEOUT_MS * 1000,
78 .page_program_timeout = SPI_FLASH_GENERIC_PAGE_PROGRAM_TIMEOUT_MS * 1000,
79 };
80
81 #define SET_FLASH_ERASE_STATUS(CHIP, status) do { \
82 if (CHIP->os_func->set_flash_op_status) { \
83 CHIP->os_func->set_flash_op_status(status); \
84 } \
85 } while(0)
86
87 static const char TAG[] = "chip_generic";
88
spi_flash_chip_generic_detect_size(esp_flash_t * chip,uint32_t * size)89 esp_err_t spi_flash_chip_generic_detect_size(esp_flash_t *chip, uint32_t *size)
90 {
91 uint32_t id = chip->chip_id;
92 *size = 0;
93
94 /* Can't detect size unless the high byte of the product ID matches the same convention, which is usually 0x40 or
95 * 0xC0 or similar. */
96 if (((id & 0xFFFF) == 0x0000) || ((id & 0xFFFF) == 0xFFFF)) {
97 return ESP_ERR_FLASH_UNSUPPORTED_CHIP;
98 }
99
100 /* Get flash capacity from flash chip id depends on different vendors. According to majority of flash datasheets,
101 Flash 256Mb to 512Mb directly from 0x19 to 0x20, instead of from 0x19 to 0x1a. So here we leave the common behavior.
102 However, some other flash vendors also have their own rule, we will add them in chip specific files.
103 */
104 uint32_t mem_density = (id & 0xFF);
105 if (mem_density > SPI_FLASH_LINEAR_DENSITY_LAST_VALUE ) {
106 mem_density -= SPI_FLASH_HEX_A_F_RANGE;
107 }
108
109 *size = 1 << mem_density;
110 return ESP_OK;
111 }
112
113 #ifndef CONFIG_SPI_FLASH_ROM_IMPL
114
spi_flash_chip_generic_probe(esp_flash_t * chip,uint32_t flash_id)115 esp_err_t spi_flash_chip_generic_probe(esp_flash_t *chip, uint32_t flash_id)
116 {
117 // This is the catch-all probe function, claim the chip always if nothing
118 // else has claimed it yet.
119 return ESP_OK;
120 }
121
spi_flash_chip_generic_reset(esp_flash_t * chip)122 esp_err_t spi_flash_chip_generic_reset(esp_flash_t *chip)
123 {
124 //this is written following the winbond spec..
125 spi_flash_trans_t t;
126 t = (spi_flash_trans_t) {
127 .command = CMD_RST_EN,
128 };
129 esp_err_t err = chip->host->driver->common_command(chip->host, &t);
130 if (err != ESP_OK) {
131 return err;
132 }
133
134 t = (spi_flash_trans_t) {
135 .command = CMD_RST_DEV,
136 };
137 err = chip->host->driver->common_command(chip->host, &t);
138 if (err != ESP_OK) {
139 return err;
140 }
141
142 err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->idle_timeout);
143 return err;
144 }
145
spi_flash_chip_generic_erase_chip(esp_flash_t * chip)146 esp_err_t spi_flash_chip_generic_erase_chip(esp_flash_t *chip)
147 {
148 esp_err_t err;
149
150 err = chip->chip_drv->set_chip_write_protect(chip, false);
151 if (err == ESP_OK) {
152 err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->idle_timeout);
153 }
154 //The chip didn't accept the previous write command. Ignore this in preparation stage.
155 if (err == ESP_OK || err == ESP_ERR_NOT_SUPPORTED) {
156 SET_FLASH_ERASE_STATUS(chip, SPI_FLASH_OS_IS_ERASING_STATUS_FLAG);
157 chip->host->driver->erase_chip(chip->host);
158 chip->busy = 1;
159 #ifdef CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED
160 err = chip->chip_drv->wait_idle(chip, ESP_FLASH_CHIP_GENERIC_NO_TIMEOUT);
161 #else
162 err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->chip_erase_timeout);
163 #endif
164 SET_FLASH_ERASE_STATUS(chip, 0);
165 }
166 // Ensure WEL is 0, even if the erase failed.
167 if (err == ESP_ERR_NOT_SUPPORTED) {
168 err = chip->chip_drv->set_chip_write_protect(chip, true);
169 }
170
171 return err;
172 }
173
spi_flash_chip_generic_erase_sector(esp_flash_t * chip,uint32_t start_address)174 esp_err_t spi_flash_chip_generic_erase_sector(esp_flash_t *chip, uint32_t start_address)
175 {
176 esp_err_t err = chip->chip_drv->set_chip_write_protect(chip, false);
177 if (err == ESP_OK) {
178 err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->idle_timeout);
179 }
180 //The chip didn't accept the previous write command. Ignore this in preparationstage.
181 if (err == ESP_OK || err == ESP_ERR_NOT_SUPPORTED) {
182 SET_FLASH_ERASE_STATUS(chip, SPI_FLASH_OS_IS_ERASING_STATUS_FLAG);
183 chip->host->driver->erase_sector(chip->host, start_address);
184 chip->busy = 1;
185 #ifdef CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED
186 err = chip->chip_drv->wait_idle(chip, ESP_FLASH_CHIP_GENERIC_NO_TIMEOUT);
187 #else
188 err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->sector_erase_timeout);
189 #endif
190 SET_FLASH_ERASE_STATUS(chip, 0);
191 }
192 // Ensure WEL is 0, even if the erase failed.
193 if (err == ESP_ERR_NOT_SUPPORTED) {
194 err = chip->chip_drv->set_chip_write_protect(chip, true);
195 }
196
197 return err;
198 }
199
spi_flash_chip_generic_erase_block(esp_flash_t * chip,uint32_t start_address)200 esp_err_t spi_flash_chip_generic_erase_block(esp_flash_t *chip, uint32_t start_address)
201 {
202 esp_err_t err = chip->chip_drv->set_chip_write_protect(chip, false);
203 if (err == ESP_OK) {
204 err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->idle_timeout);
205 }
206 //The chip didn't accept the previous write command. Ignore this in preparationstage.
207 if (err == ESP_OK || err == ESP_ERR_NOT_SUPPORTED) {
208 SET_FLASH_ERASE_STATUS(chip, SPI_FLASH_OS_IS_ERASING_STATUS_FLAG);
209 chip->host->driver->erase_block(chip->host, start_address);
210 chip->busy = 1;
211 #ifdef CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED
212 err = chip->chip_drv->wait_idle(chip, ESP_FLASH_CHIP_GENERIC_NO_TIMEOUT);
213 #else
214 err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->block_erase_timeout);
215 #endif
216 SET_FLASH_ERASE_STATUS(chip, 0);
217 }
218 // Ensure WEL is 0, even if the erase failed.
219 if (err == ESP_ERR_NOT_SUPPORTED) {
220 err = chip->chip_drv->set_chip_write_protect(chip, true);
221 }
222
223 return err;
224 }
225
spi_flash_chip_generic_read(esp_flash_t * chip,void * buffer,uint32_t address,uint32_t length)226 esp_err_t spi_flash_chip_generic_read(esp_flash_t *chip, void *buffer, uint32_t address, uint32_t length)
227 {
228 esp_err_t err = ESP_OK;
229 const uint32_t page_size = chip->chip_drv->page_size;
230 uint32_t align_address;
231 uint8_t temp_buffer[64]; //spiflash hal max length of read no longer than 64byte
232 uint32_t config_io_flags = 0;
233
234 // Configure the host, and return
235 err = chip->chip_drv->config_host_io_mode(chip, config_io_flags);
236
237 if (err == ESP_ERR_NOT_SUPPORTED) {
238 ESP_LOGE(TAG, "configure host io mode failed - unsupported");
239 return err;
240 }
241
242 while (err == ESP_OK && length > 0) {
243 memset(temp_buffer, 0xFF, sizeof(temp_buffer));
244 uint32_t read_len = chip->host->driver->read_data_slicer(chip->host, address, length, &align_address, page_size);
245 uint32_t left_off = address - align_address;
246 uint32_t data_len = MIN(align_address + read_len, address + length) - address;
247 err = chip->host->driver->read(chip->host, temp_buffer, align_address, read_len);
248
249 memcpy(buffer, temp_buffer + left_off, data_len);
250
251 address += data_len;
252 buffer = (void *)((intptr_t)buffer + data_len);
253 length = length - data_len;
254 }
255
256 return err;
257 }
258
spi_flash_chip_generic_page_program(esp_flash_t * chip,const void * buffer,uint32_t address,uint32_t length)259 esp_err_t spi_flash_chip_generic_page_program(esp_flash_t *chip, const void *buffer, uint32_t address, uint32_t length)
260 {
261 esp_err_t err;
262
263 err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->idle_timeout);
264 //The chip didn't accept the previous write command. Ignore this in preparationstage.
265 if (err == ESP_OK || err == ESP_ERR_NOT_SUPPORTED) {
266 // Perform the actual Page Program command
267 chip->host->driver->program_page(chip->host, buffer, address, length);
268 chip->busy = 1;
269
270 err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->page_program_timeout);
271 }
272 // Ensure WEL is 0, even if the page program failed.
273 if (err == ESP_ERR_NOT_SUPPORTED) {
274 err = chip->chip_drv->set_chip_write_protect(chip, true);
275 }
276 return err;
277 }
278
spi_flash_chip_generic_write(esp_flash_t * chip,const void * buffer,uint32_t address,uint32_t length)279 esp_err_t spi_flash_chip_generic_write(esp_flash_t *chip, const void *buffer, uint32_t address, uint32_t length)
280 {
281 esp_err_t err = ESP_OK;
282 const uint32_t page_size = chip->chip_drv->page_size;
283 uint32_t align_address;
284 uint8_t temp_buffer[64]; //spiflash hal max length of write no longer than 64byte
285
286 while (err == ESP_OK && length > 0) {
287 memset(temp_buffer, 0xFF, sizeof(temp_buffer));
288 uint32_t page_len = chip->host->driver->write_data_slicer(chip->host, address, length, &align_address, page_size);
289 uint32_t left_off = address - align_address;
290 uint32_t write_len = MIN(align_address + page_len, address + length) - address;
291 memcpy(temp_buffer + left_off, buffer, write_len);
292
293 err = chip->chip_drv->set_chip_write_protect(chip, false);
294 if (err == ESP_OK && length > 0) {
295 err = chip->chip_drv->program_page(chip, temp_buffer, align_address, page_len);
296
297 address += write_len;
298 buffer = (void *)((intptr_t)buffer + write_len);
299 length -= write_len;
300 }
301 }
302 // The caller is responsible to do host->driver->flush_cache, because this function may be
303 // called in small pieces. Frequency call of flush cache will do harm to the performance.
304 return err;
305 }
306
spi_flash_chip_generic_set_write_protect(esp_flash_t * chip,bool write_protect)307 esp_err_t spi_flash_chip_generic_set_write_protect(esp_flash_t *chip, bool write_protect)
308 {
309 esp_err_t err = ESP_OK;
310
311 err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->idle_timeout);
312 //The chip didn't accept the previous write command. Ignore this in preparationstage.
313 if (err == ESP_OK || err == ESP_ERR_NOT_SUPPORTED) {
314 chip->host->driver->set_write_protect(chip->host, write_protect);
315 }
316
317 bool wp_read;
318 err = chip->chip_drv->get_chip_write_protect(chip, &wp_read);
319 if (err == ESP_OK && wp_read != write_protect) {
320 // WREN flag has not been set!
321 err = ESP_ERR_NOT_FOUND;
322 }
323 return err;
324 }
325
spi_flash_chip_generic_get_write_protect(esp_flash_t * chip,bool * out_write_protect)326 esp_err_t spi_flash_chip_generic_get_write_protect(esp_flash_t *chip, bool *out_write_protect)
327 {
328 esp_err_t err = ESP_OK;
329 uint32_t status;
330 assert(out_write_protect!=NULL);
331 err = chip->chip_drv->read_reg(chip, SPI_FLASH_REG_STATUS, &status);
332 if (err != ESP_OK) {
333 return err;
334 }
335
336 *out_write_protect = ((status & SR_WREN) == 0);
337 return err;
338 }
339
spi_flash_chip_generic_read_reg(esp_flash_t * chip,spi_flash_register_t reg_id,uint32_t * out_reg)340 esp_err_t spi_flash_chip_generic_read_reg(esp_flash_t* chip, spi_flash_register_t reg_id, uint32_t* out_reg)
341 {
342 return chip->host->driver->read_status(chip->host, (uint8_t*)out_reg);
343 }
344
spi_flash_chip_generic_yield(esp_flash_t * chip,uint32_t wip)345 esp_err_t spi_flash_chip_generic_yield(esp_flash_t* chip, uint32_t wip)
346 {
347 esp_err_t err = ESP_OK;
348 uint32_t flags = wip? 1: 0; //check_yield() and yield() impls should not issue suspend/resume if this flag is zero
349
350 if (chip->os_func->check_yield) {
351 uint32_t request;
352 //According to the implementation, the check_yield() function may block, poll, delay or do nothing but return
353 err = chip->os_func->check_yield(chip->os_func_data, flags, &request);
354 if (err == ESP_OK) {
355 if (err == ESP_OK && (request & SPI_FLASH_YIELD_REQ_YIELD) != 0) {
356 uint32_t status;
357 //According to the implementation, the yield() function may block until something happen
358 err = chip->os_func->yield(chip->os_func_data, &status);
359 }
360 } else if (err == ESP_ERR_TIMEOUT) {
361 err = ESP_OK;
362 } else {
363 abort();
364 }
365 }
366 return err;
367 }
368
spi_flash_chip_generic_wait_idle(esp_flash_t * chip,uint32_t timeout_us)369 esp_err_t spi_flash_chip_generic_wait_idle(esp_flash_t *chip, uint32_t timeout_us)
370 {
371 bool timeout_en = (timeout_us != ESP_FLASH_CHIP_GENERIC_NO_TIMEOUT);
372 if (timeout_us == ESP_FLASH_CHIP_GENERIC_NO_TIMEOUT) {
373 timeout_us = 0;// In order to go into while
374 }
375 timeout_us++; // allow at least one pass before timeout, last one has no sleep cycle
376
377 uint8_t status = 0;
378 const int interval = CHIP_WAIT_IDLE_INTERVAL_US;
379 while (timeout_us > 0) {
380 while (!chip->host->driver->host_status(chip->host) && timeout_us > 0) {
381
382 #if HOST_DELAY_INTERVAL_US > 0
383 if (timeout_us > 1) {
384 int delay = MIN(HOST_DELAY_INTERVAL_US, timeout_us);
385 chip->os_func->delay_us(chip->os_func_data, delay);
386 timeout_us -= delay;
387 }
388 #endif
389 }
390
391 uint32_t read;
392 esp_err_t err = chip->chip_drv->read_reg(chip, SPI_FLASH_REG_STATUS, &read);
393 if (err != ESP_OK) {
394 return err;
395 }
396 status = read;
397
398 if ((status & SR_WIP) == 0) { // Verify write in progress is complete
399 if (chip->busy == 1) {
400 chip->busy = 0;
401 if ((status & SR_WREN) != 0) { // The previous command is not accepted, leaving the WEL still set.
402 return ESP_ERR_NOT_SUPPORTED;
403 }
404 }
405 break;
406 }
407 if (timeout_us > 0 && interval > 0) {
408 int delay = MIN(interval, timeout_us);
409 chip->os_func->delay_us(chip->os_func_data, delay);
410 if (timeout_en) {
411 timeout_us -= delay;
412 }
413 }
414 }
415 return (timeout_us > 0) ? ESP_OK : ESP_ERR_TIMEOUT;
416 }
417
spi_flash_chip_generic_config_host_io_mode(esp_flash_t * chip,uint32_t flags)418 esp_err_t spi_flash_chip_generic_config_host_io_mode(esp_flash_t *chip, uint32_t flags)
419 {
420 uint32_t dummy_cyclelen_base;
421 uint32_t addr_bitlen;
422 uint32_t read_command;
423 bool conf_required = false;
424 esp_flash_io_mode_t read_mode = chip->read_mode;
425 bool addr_32bit = (flags & SPI_FLASH_CONFIG_IO_MODE_32B_ADDR);
426
427 switch (read_mode & 0xFFFF) {
428 case SPI_FLASH_QIO:
429 //for QIO mode, the 4 bit right after the address are used for continuous mode, should be set to 0 to avoid that.
430 addr_bitlen = SPI_FLASH_QIO_ADDR_BITLEN;
431 dummy_cyclelen_base = (chip->hpm_dummy_ena ? rom_flash_chip_dummy_hpm->qio_dummy_bitlen : rom_flash_chip_dummy->qio_dummy_bitlen);
432 read_command = (addr_32bit? CMD_FASTRD_QIO_4B: CMD_FASTRD_QIO);
433 conf_required = true;
434 break;
435 case SPI_FLASH_QOUT:
436 addr_bitlen = SPI_FLASH_QOUT_ADDR_BITLEN;
437 dummy_cyclelen_base = (chip->hpm_dummy_ena ? rom_flash_chip_dummy_hpm->qout_dummy_bitlen : rom_flash_chip_dummy->qout_dummy_bitlen);
438 read_command = (addr_32bit? CMD_FASTRD_QUAD_4B: CMD_FASTRD_QUAD);
439 break;
440 case SPI_FLASH_DIO:
441 //for DIO mode, the 4 bit right after the address are used for continuous mode, should be set to 0 to avoid that.
442 addr_bitlen = SPI_FLASH_DIO_ADDR_BITLEN;
443 dummy_cyclelen_base = (chip->hpm_dummy_ena ? rom_flash_chip_dummy_hpm->dio_dummy_bitlen : rom_flash_chip_dummy->dio_dummy_bitlen);
444 read_command = (addr_32bit? CMD_FASTRD_DIO_4B: CMD_FASTRD_DIO);
445 conf_required = true;
446 break;
447 case SPI_FLASH_DOUT:
448 addr_bitlen = SPI_FLASH_DOUT_ADDR_BITLEN;
449 dummy_cyclelen_base = (chip->hpm_dummy_ena ? rom_flash_chip_dummy_hpm->dout_dummy_bitlen : rom_flash_chip_dummy->dout_dummy_bitlen);
450 read_command = (addr_32bit? CMD_FASTRD_DUAL_4B: CMD_FASTRD_DUAL);
451 break;
452 case SPI_FLASH_FASTRD:
453 addr_bitlen = SPI_FLASH_FASTRD_ADDR_BITLEN;
454 dummy_cyclelen_base = (chip->hpm_dummy_ena ? rom_flash_chip_dummy_hpm->fastrd_dummy_bitlen : rom_flash_chip_dummy->fastrd_dummy_bitlen);
455 read_command = (addr_32bit? CMD_FASTRD_4B: CMD_FASTRD);
456 break;
457 case SPI_FLASH_SLOWRD:
458 addr_bitlen = SPI_FLASH_SLOWRD_ADDR_BITLEN;
459 dummy_cyclelen_base = (chip->hpm_dummy_ena ? rom_flash_chip_dummy_hpm->slowrd_dummy_bitlen : rom_flash_chip_dummy->slowrd_dummy_bitlen);
460 read_command = (addr_32bit? CMD_READ_4B: CMD_READ);
461 break;
462 default:
463 return ESP_ERR_FLASH_NOT_INITIALISED;
464 }
465 //For W25Q256 chip, the only difference between 4-Byte address command and 3-Byte version is the command value and the address bit length.
466 if (addr_32bit) {
467 addr_bitlen += 8;
468 }
469
470 if (conf_required) {
471 read_mode |= SPI_FLASH_CONFIG_CONF_BITS;
472 }
473
474 return chip->host->driver->configure_host_io_mode(chip->host, read_command, addr_bitlen, dummy_cyclelen_base, read_mode);
475 }
476
spi_flash_chip_generic_get_io_mode(esp_flash_t * chip,esp_flash_io_mode_t * out_io_mode)477 esp_err_t spi_flash_chip_generic_get_io_mode(esp_flash_t *chip, esp_flash_io_mode_t* out_io_mode)
478 {
479 // On "generic" chips, this involves checking
480 // bit 1 (QE) of RDSR2 (35h) result
481 // (it works this way on GigaDevice & Fudan Micro chips, probably others...)
482 const uint8_t BIT_QE = 1 << 1;
483 uint32_t sr;
484 esp_err_t ret = spi_flash_common_read_status_8b_rdsr2(chip, &sr);
485 if (ret == ESP_OK) {
486 *out_io_mode = ((sr & BIT_QE)? SPI_FLASH_QOUT: 0);
487 }
488 return ret;
489 }
490
spi_flash_chip_generic_set_io_mode(esp_flash_t * chip)491 esp_err_t spi_flash_chip_generic_set_io_mode(esp_flash_t *chip)
492 {
493 // On "generic" chips, this involves checking
494 // bit 9 (QE) of RDSR (05h) result
495 const uint32_t BIT_QE = 1 << 9;
496 return spi_flash_common_set_io_mode(chip,
497 spi_flash_common_write_status_16b_wrsr,
498 spi_flash_common_read_status_16b_rdsr_rdsr2,
499 BIT_QE);
500 }
501 #endif // CONFIG_SPI_FLASH_ROM_IMPL
502
503 #if !CONFIG_SPI_FLASH_ROM_IMPL || ESP_ROM_HAS_ENCRYPTED_WRITES_USING_LEGACY_DRV
spi_flash_chip_generic_write_encrypted(esp_flash_t * chip,const void * buffer,uint32_t address,uint32_t length)504 esp_err_t spi_flash_chip_generic_write_encrypted(esp_flash_t *chip, const void *buffer, uint32_t address, uint32_t length)
505 {
506 spi_flash_encryption_t *esp_flash_encryption = &esp_flash_encryption_default;
507 esp_err_t err = ESP_OK;
508 // Encryption must happen on main flash.
509 if (chip != esp_flash_default_chip) {
510 return ESP_ERR_NOT_SUPPORTED;
511 }
512
513 /* Check if the buffer and length can qualify the requirements */
514 if (esp_flash_encryption->flash_encryption_check(address, length) != true) {
515 return ESP_ERR_NOT_SUPPORTED;
516 }
517
518 const uint8_t *data_bytes = (const uint8_t *)buffer;
519 esp_flash_encryption->flash_encryption_enable();
520 while (length > 0) {
521 int block_size;
522 /* Write the largest block if possible */
523 if (address % 64 == 0 && length >= 64) {
524 block_size = 64;
525 } else if (address % 32 == 0 && length >= 32) {
526 block_size = 32;
527 } else {
528 block_size = 16;
529 }
530 // Prepare the flash chip (same time as AES operation, for performance)
531 esp_flash_encryption->flash_encryption_data_prepare(address, (uint32_t *)data_bytes, block_size);
532 err = chip->chip_drv->set_chip_write_protect(chip, false);
533 if (err != ESP_OK) {
534 return err;
535 }
536 // Waiting for encrypting buffer to finish and making result visible for SPI1
537 esp_flash_encryption->flash_encryption_done();
538
539 // Note: For encryption function, after write flash command is sent. The hardware will write the encrypted buffer
540 // prepared in XTS_FLASH_ENCRYPTION register in function `flash_encryption_data_prepare`, instead of the origin
541 // buffer named `data_bytes`.
542
543 err = chip->chip_drv->write(chip, (uint32_t *)data_bytes, address, length);
544 if (err != ESP_OK) {
545 return err;
546 }
547 err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->page_program_timeout);
548 if (err != ESP_OK) {
549 return err;
550 }
551
552 // Note: we don't wait for idle status here, because this way
553 // the AES peripheral can start encrypting the next
554 // block while the SPI flash chip is busy completing the write
555
556 esp_flash_encryption->flash_encryption_destroy();
557
558 length -= block_size;
559 data_bytes += block_size;
560 address += block_size;
561 }
562
563 esp_flash_encryption->flash_encryption_disable();
564 return err;
565 }
566 #endif // !CONFIG_SPI_FLASH_ROM_IMPL || ESP_ROM_HAS_ENCRYPTED_WRITES_USING_LEGACY_DRV
567
spi_flash_chip_generic_read_unique_id(esp_flash_t * chip,uint64_t * flash_unique_id)568 esp_err_t spi_flash_chip_generic_read_unique_id(esp_flash_t *chip, uint64_t* flash_unique_id)
569 {
570 uint64_t unique_id_buf = 0;
571 spi_flash_trans_t transfer = {
572 .command = CMD_RDUID,
573 .miso_len = 8,
574 .miso_data = ((uint8_t *)&unique_id_buf),
575 .dummy_bitlen = 32, //RDUID command followed by 4 bytes (32 bits) of dummy clocks.
576 };
577 esp_err_t err = chip->host->driver->common_command(chip->host, &transfer);
578
579 if (unique_id_buf == 0 || unique_id_buf == UINT64_MAX) {
580 ESP_EARLY_LOGE(TAG, "No response from device when trying to retrieve Unique ID\n");
581 *flash_unique_id = unique_id_buf;
582 return ESP_ERR_NOT_SUPPORTED;
583 }
584
585 *flash_unique_id = __builtin_bswap64(unique_id_buf);
586 return err;
587 }
588
spi_flash_chip_generic_read_unique_id_none(esp_flash_t * chip,uint64_t * flash_unique_id)589 esp_err_t spi_flash_chip_generic_read_unique_id_none(esp_flash_t *chip, uint64_t* flash_unique_id)
590 {
591 // For flash doesn't support read unique id.
592 return ESP_ERR_NOT_SUPPORTED;
593 }
594
spi_flash_chip_generic_get_caps(esp_flash_t * chip)595 spi_flash_caps_t spi_flash_chip_generic_get_caps(esp_flash_t *chip)
596 {
597 // For generic part flash capability, take the XMC chip as reference.
598 spi_flash_caps_t caps_flags = 0;
599 // 32M-bits address support
600
601 // flash suspend support
602 // XMC-D support suspend
603 if (chip->chip_id >> 16 == 0x46) {
604 caps_flags |= SPI_FLASH_CHIP_CAP_SUSPEND;
605 }
606
607 // XMC-D support suspend (some D series flash chip begin with 0x20, difference checked by SFDP)
608 if (chip->chip_id >> 16 == 0x20) {
609 uint8_t data = 0;
610 spi_flash_trans_t t = {
611 .command = CMD_RDSFDP,
612 .address_bitlen = 24,
613 .address = 0x32,
614 .mosi_len = 0,
615 .mosi_data = 0,
616 .miso_len = 1,
617 .miso_data = &data,
618 .dummy_bitlen = 8,
619 };
620 chip->host->driver->common_command(chip->host, &t);
621 if((data & 0x8) == 0x8) {
622 caps_flags |= SPI_FLASH_CHIP_CAP_SUSPEND;
623 }
624 }
625
626 #if CONFIG_SPI_FLASH_FORCE_ENABLE_XMC_C_SUSPEND
627 // XMC-C suspend has big risk. But can enable this anyway.
628 if (chip->chip_id >> 16 == 0x20) {
629 caps_flags |= SPI_FLASH_CHIP_CAP_SUSPEND;
630 }
631 #endif
632
633 // FM support suspend
634 if (chip->chip_id >> 16 == 0xa1) {
635 caps_flags |= SPI_FLASH_CHIP_CAP_SUSPEND;
636 }
637 // flash read unique id.
638 caps_flags |= SPI_FLASH_CHIP_CAP_UNIQUE_ID;
639 return caps_flags;
640 }
641
642 static const char chip_name[] = "generic";
643
644 const spi_flash_chip_t esp_flash_chip_generic = {
645 .name = chip_name,
646 .timeout = &spi_flash_chip_generic_timeout,
647 .probe = spi_flash_chip_generic_probe,
648 .reset = spi_flash_chip_generic_reset,
649 .detect_size = spi_flash_chip_generic_detect_size,
650 .erase_chip = spi_flash_chip_generic_erase_chip,
651 .erase_sector = spi_flash_chip_generic_erase_sector,
652 .erase_block = spi_flash_chip_generic_erase_block,
653 .sector_size = 4 * 1024,
654 .block_erase_size = 64 * 1024,
655
656 // TODO: figure out if generic chip-wide protection bits exist across some manufacturers
657 .get_chip_write_protect = spi_flash_chip_generic_get_write_protect,
658 .set_chip_write_protect = spi_flash_chip_generic_set_write_protect,
659
660 // Chip write protection regions do not appear to be standardised
661 // at all, this is implemented in chip-specific drivers only.
662 .num_protectable_regions = 0,
663 .protectable_regions = NULL,
664 .get_protected_regions = NULL,
665 .set_protected_regions = NULL,
666
667 .read = spi_flash_chip_generic_read,
668 .write = spi_flash_chip_generic_write,
669 .program_page = spi_flash_chip_generic_page_program,
670 .page_size = 256,
671 .write_encrypted = spi_flash_chip_generic_write_encrypted,
672
673 .wait_idle = spi_flash_chip_generic_wait_idle,
674 .set_io_mode = spi_flash_chip_generic_set_io_mode,
675 .get_io_mode = spi_flash_chip_generic_get_io_mode,
676
677 .read_reg = spi_flash_chip_generic_read_reg,
678 .yield = spi_flash_chip_generic_yield,
679 .sus_setup = spi_flash_chip_generic_suspend_cmd_conf,
680 .read_unique_id = spi_flash_chip_generic_read_unique_id,
681 .get_chip_caps = spi_flash_chip_generic_get_caps,
682 .config_host_io_mode = spi_flash_chip_generic_config_host_io_mode,
683 };
684
685 #ifndef CONFIG_SPI_FLASH_ROM_IMPL
686 /*******************************************************************************
687 * Utility functions
688 ******************************************************************************/
689
spi_flash_common_read_qe_sr(esp_flash_t * chip,uint8_t qe_rdsr_command,uint8_t qe_sr_bitwidth,uint32_t * sr)690 static esp_err_t spi_flash_common_read_qe_sr(esp_flash_t *chip, uint8_t qe_rdsr_command, uint8_t qe_sr_bitwidth, uint32_t *sr)
691 {
692 uint32_t sr_buf = 0;
693 spi_flash_trans_t t = {
694 .command = qe_rdsr_command,
695 .miso_data = (uint8_t*) &sr_buf,
696 .miso_len = qe_sr_bitwidth / 8,
697 };
698 esp_err_t ret = chip->host->driver->common_command(chip->host, &t);
699 *sr = sr_buf;
700 return ret;
701 }
702
spi_flash_common_write_qe_sr(esp_flash_t * chip,uint8_t qe_wrsr_command,uint8_t qe_sr_bitwidth,uint32_t qe)703 static esp_err_t spi_flash_common_write_qe_sr(esp_flash_t *chip, uint8_t qe_wrsr_command, uint8_t qe_sr_bitwidth, uint32_t qe)
704 {
705 spi_flash_trans_t t = {
706 .command = qe_wrsr_command,
707 .mosi_data = ((uint8_t*) &qe),
708 .mosi_len = qe_sr_bitwidth / 8,
709 .miso_len = 0,
710 };
711 return chip->host->driver->common_command(chip->host, &t);
712 }
713
spi_flash_common_read_status_16b_rdsr_rdsr2(esp_flash_t * chip,uint32_t * out_sr)714 esp_err_t spi_flash_common_read_status_16b_rdsr_rdsr2(esp_flash_t* chip, uint32_t* out_sr)
715 {
716 uint32_t sr, sr2;
717 esp_err_t ret = spi_flash_common_read_qe_sr(chip, CMD_RDSR2, 8, &sr2);
718 if (ret == ESP_OK) {
719 ret = spi_flash_common_read_qe_sr(chip, CMD_RDSR, 8, &sr);
720 }
721 if (ret == ESP_OK) {
722 *out_sr = (sr & 0xff) | ((sr2 & 0xff) << 8);
723 }
724 return ret;
725 }
726
spi_flash_common_read_status_8b_rdsr2(esp_flash_t * chip,uint32_t * out_sr)727 esp_err_t spi_flash_common_read_status_8b_rdsr2(esp_flash_t* chip, uint32_t* out_sr)
728 {
729 return spi_flash_common_read_qe_sr(chip, CMD_RDSR2, 8, out_sr);
730 }
731
spi_flash_common_read_status_8b_rdsr(esp_flash_t * chip,uint32_t * out_sr)732 esp_err_t spi_flash_common_read_status_8b_rdsr(esp_flash_t* chip, uint32_t* out_sr)
733 {
734 return spi_flash_common_read_qe_sr(chip, CMD_RDSR, 8, out_sr);
735 }
736
spi_flash_common_write_status_16b_wrsr(esp_flash_t * chip,uint32_t sr)737 esp_err_t spi_flash_common_write_status_16b_wrsr(esp_flash_t* chip, uint32_t sr)
738 {
739 return spi_flash_common_write_qe_sr(chip, CMD_WRSR, 16, sr);
740 }
741
spi_flash_common_write_status_8b_wrsr(esp_flash_t * chip,uint32_t sr)742 esp_err_t spi_flash_common_write_status_8b_wrsr(esp_flash_t* chip, uint32_t sr)
743 {
744 return spi_flash_common_write_qe_sr(chip, CMD_WRSR, 8, sr);
745 }
746
spi_flash_common_write_status_8b_wrsr2(esp_flash_t * chip,uint32_t sr)747 esp_err_t spi_flash_common_write_status_8b_wrsr2(esp_flash_t* chip, uint32_t sr)
748 {
749 return spi_flash_common_write_qe_sr(chip, CMD_WRSR2, 8, sr);
750 }
751
spi_flash_common_set_io_mode(esp_flash_t * chip,esp_flash_wrsr_func_t wrsr_func,esp_flash_rdsr_func_t rdsr_func,uint32_t qe_sr_bit)752 esp_err_t spi_flash_common_set_io_mode(esp_flash_t *chip, esp_flash_wrsr_func_t wrsr_func, esp_flash_rdsr_func_t rdsr_func, uint32_t qe_sr_bit)
753 {
754 esp_err_t ret = ESP_OK;
755 const bool is_quad_mode = esp_flash_is_quad_mode(chip);
756 bool update_config = false;
757 /*
758 * By default, we don't clear the QE bit even the flash mode is not QIO or QOUT. Force clearing
759 * QE bit by the generic chip driver (command 01H with 2 bytes) may cause the output of some
760 * chips (MXIC) no longer valid.
761 * Enable this option when testing a new flash chip for clearing of QE.
762 */
763 const bool force_check = false;
764
765 bool need_check = is_quad_mode || force_check;
766
767 uint32_t sr_update;
768 if (need_check) {
769 // Ensure quad modes are enabled, using the Quad Enable parameters supplied.
770 uint32_t sr;
771 ret = (*rdsr_func)(chip, &sr);
772 if (ret != ESP_OK) {
773 return ret;
774 }
775 ESP_EARLY_LOGD(TAG, "set_io_mode: status before 0x%x", sr);
776 if (is_quad_mode) {
777 sr_update = sr | qe_sr_bit;
778 } else {
779 sr_update = sr & (~qe_sr_bit);
780 }
781 ESP_EARLY_LOGV(TAG, "set_io_mode: status update 0x%x", sr_update);
782 if (sr != sr_update) {
783 update_config = true;
784 }
785 }
786
787 if (update_config) {
788 //some chips needs the write protect to be disabled before writing to Status Register
789 chip->chip_drv->set_chip_write_protect(chip, false);
790
791 ret = (*wrsr_func)(chip, sr_update);
792 if (ret != ESP_OK) {
793 chip->chip_drv->set_chip_write_protect(chip, true);
794 return ret;
795 }
796
797 ret = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->idle_timeout);
798 if (ret == ESP_ERR_NOT_SUPPORTED) {
799 chip->chip_drv->set_chip_write_protect(chip, true);
800 }
801 /* This function is the fallback approach, so we give it higher tolerance.
802 * When the previous WRSR is rejected by the flash,
803 * the result of this function is determined by the result -whether the value of RDSR meets the expectation.
804 */
805 if (ret != ESP_OK && ret != ESP_ERR_NOT_SUPPORTED) {
806 return ret;
807 }
808
809 /* Check the new QE bit has stayed set */
810 uint32_t sr;
811 ret = (*rdsr_func)(chip, &sr);
812 if (ret != ESP_OK) {
813 return ret;
814 }
815 ESP_EARLY_LOGD(TAG, "set_io_mode: status after 0x%x", sr);
816 if (sr != sr_update) {
817 ret = ESP_ERR_FLASH_NO_RESPONSE;
818 }
819 }
820 return ret;
821 }
822
823 #endif // !CONFIG_SPI_FLASH_ROM_IMPL
824
spi_flash_chip_generic_suspend_cmd_conf(esp_flash_t * chip)825 esp_err_t spi_flash_chip_generic_suspend_cmd_conf(esp_flash_t *chip)
826 {
827 // Only XMC support auto-suspend
828 if (chip->chip_id >> 16 != 0x20) {
829 ESP_EARLY_LOGE(TAG, "The flash you use doesn't support auto suspend, only \'XMC\' is supported");
830 return ESP_ERR_NOT_SUPPORTED;
831 }
832 spi_flash_sus_cmd_conf sus_conf = {
833 .sus_mask = 0x80,
834 .cmd_rdsr = CMD_RDSR2,
835 .sus_cmd = CMD_SUSPEND,
836 .res_cmd = CMD_RESUME,
837 };
838
839 return chip->host->driver->sus_setup(chip->host, &sus_conf);
840 }
841
