| /hal_espressif-latest/components/hal/esp32s2/include/hal/ |
| D | cp_dma_ll.h | 35 dev->dma_conf.dma_in_rst = 1; in cp_dma_ll_reset_in_link()
36 dev->dma_conf.dma_in_rst = 0; in cp_dma_ll_reset_in_link()
41 dev->dma_conf.dma_out_rst = 1; in cp_dma_ll_reset_out_link()
42 dev->dma_conf.dma_out_rst = 0; in cp_dma_ll_reset_out_link()
47 dev->dma_conf.dma_fifo_rst = 1; in cp_dma_ll_reset_fifo()
48 dev->dma_conf.dma_fifo_rst = 0; in cp_dma_ll_reset_fifo()
53 dev->dma_conf.dma_cmdfifo_rst = 1; in cp_dma_ll_reset_cmd_fifo()
54 dev->dma_conf.dma_cmdfifo_rst = 0; in cp_dma_ll_reset_cmd_fifo()
59 dev->dma_conf.dma_check_owner = enable; in cp_dma_ll_enable_owner_check()
60 dev->dma_conf.dma_out_auto_wrback = 1; in cp_dma_ll_enable_owner_check()
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| D | spi_ll.h | 159 hw->dma_conf.rx_eof_en = 0; in spi_ll_slave_init()
262 hw->dma_conf.val |= SPI_LL_DMA_FIFO_RST_MASK; in spi_ll_dma_tx_fifo_reset()
263 hw->dma_conf.val &= ~SPI_LL_DMA_FIFO_RST_MASK; in spi_ll_dma_tx_fifo_reset()
275 hw->dma_conf.val |= SPI_LL_DMA_FIFO_RST_MASK; in spi_ll_dma_rx_fifo_reset()
276 hw->dma_conf.val &= ~SPI_LL_DMA_FIFO_RST_MASK; in spi_ll_dma_rx_fifo_reset()
286 hw->dma_conf.infifo_full_clr = 1; in spi_ll_infifo_full_clr()
287 hw->dma_conf.infifo_full_clr = 0; in spi_ll_infifo_full_clr()
297 hw->dma_conf.outfifo_empty_clr = 1; in spi_ll_outfifo_empty_clr()
298 hw->dma_conf.outfifo_empty_clr = 0; in spi_ll_outfifo_empty_clr()
334 hw->dma_conf.rx_eof_en = enable; in spi_ll_dma_set_rx_eof_generation()
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| D | adc_ll.h | 516 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.dma_conf, apb_adc_eof_num, num); in adc_ll_digi_dma_set_eof_num()
524 APB_SARADC.dma_conf.apb_adc_trans = 1; in adc_ll_digi_dma_enable()
532 APB_SARADC.dma_conf.apb_adc_trans = 0; in adc_ll_digi_dma_disable()
540 APB_SARADC.dma_conf.apb_adc_reset_fsm = 1; in adc_ll_digi_reset()
541 APB_SARADC.dma_conf.apb_adc_reset_fsm = 0; in adc_ll_digi_reset()
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| /hal_espressif-latest/components/hal/esp32s3/include/hal/ |
| D | spi_ll.h | 139 hw->dma_conf.val = 0; in spi_ll_master_init()
140 hw->dma_conf.tx_seg_trans_clr_en = 1; in spi_ll_master_init()
141 hw->dma_conf.rx_seg_trans_clr_en = 1; in spi_ll_master_init()
142 hw->dma_conf.dma_seg_trans_en = 0; in spi_ll_master_init()
166 hw->dma_conf.rx_eof_en = 0; in spi_ll_slave_init()
167 hw->dma_conf.dma_seg_trans_en = 0; in spi_ll_slave_init()
266 hw->dma_conf.buf_afifo_rst = 1; in spi_ll_cpu_tx_fifo_reset()
267 hw->dma_conf.buf_afifo_rst = 0; in spi_ll_cpu_tx_fifo_reset()
279 hw->dma_conf.rx_afifo_rst = 1; in spi_ll_cpu_rx_fifo_reset()
280 hw->dma_conf.rx_afifo_rst = 0; in spi_ll_cpu_rx_fifo_reset()
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| D | gpspi_flash_ll.h | 60 dev->dma_conf.val = 0; in gpspi_flash_ll_reset()
61 dev->dma_conf.tx_seg_trans_clr_en = 1; in gpspi_flash_ll_reset()
62 dev->dma_conf.rx_seg_trans_clr_en = 1; in gpspi_flash_ll_reset()
63 dev->dma_conf.dma_seg_trans_en = 0; in gpspi_flash_ll_reset()
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| D | adc_ll.h | 503 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.dma_conf, apb_adc_eof_num, num); in adc_ll_digi_dma_set_eof_num()
511 APB_SARADC.dma_conf.apb_adc_trans = 1; in adc_ll_digi_dma_enable()
519 APB_SARADC.dma_conf.apb_adc_trans = 0; in adc_ll_digi_dma_disable()
527 APB_SARADC.dma_conf.apb_adc_reset_fsm = 1; in adc_ll_digi_reset()
528 APB_SARADC.dma_conf.apb_adc_reset_fsm = 0; in adc_ll_digi_reset()
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| /hal_espressif-latest/components/hal/esp32c6/include/hal/ |
| D | spi_ll.h | 141 hw->dma_conf.val = 0; in spi_ll_master_init()
142 hw->dma_conf.slv_tx_seg_trans_clr_en = 1; in spi_ll_master_init()
143 hw->dma_conf.slv_rx_seg_trans_clr_en = 1; in spi_ll_master_init()
144 hw->dma_conf.dma_slv_seg_trans_en = 0; in spi_ll_master_init()
168 hw->dma_conf.rx_eof_en = 0; in spi_ll_slave_init()
169 hw->dma_conf.dma_slv_seg_trans_en = 0; in spi_ll_slave_init()
268 hw->dma_conf.buf_afifo_rst = 1; in spi_ll_cpu_tx_fifo_reset()
269 hw->dma_conf.buf_afifo_rst = 0; in spi_ll_cpu_tx_fifo_reset()
281 hw->dma_conf.rx_afifo_rst = 1; in spi_ll_cpu_rx_fifo_reset()
282 hw->dma_conf.rx_afifo_rst = 0; in spi_ll_cpu_rx_fifo_reset()
[all …]
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| D | gpspi_flash_ll.h | 55 dev->dma_conf.val = 0; in gpspi_flash_ll_reset()
56 dev->dma_conf.slv_tx_seg_trans_clr_en = 1; in gpspi_flash_ll_reset()
57 dev->dma_conf.slv_rx_seg_trans_clr_en = 1; in gpspi_flash_ll_reset()
58 dev->dma_conf.dma_slv_seg_trans_en = 0; in gpspi_flash_ll_reset()
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| /hal_espressif-latest/components/hal/esp32c2/include/hal/ |
| D | spi_ll.h | 137 hw->dma_conf.val = 0; in spi_ll_master_init()
138 hw->dma_conf.tx_seg_trans_clr_en = 1; in spi_ll_master_init()
139 hw->dma_conf.rx_seg_trans_clr_en = 1; in spi_ll_master_init()
140 hw->dma_conf.dma_seg_trans_en = 0; in spi_ll_master_init()
164 hw->dma_conf.rx_eof_en = 0; in spi_ll_slave_init()
165 hw->dma_conf.dma_seg_trans_en = 0; in spi_ll_slave_init()
264 hw->dma_conf.buf_afifo_rst = 1; in spi_ll_cpu_tx_fifo_reset()
265 hw->dma_conf.buf_afifo_rst = 0; in spi_ll_cpu_tx_fifo_reset()
277 hw->dma_conf.rx_afifo_rst = 1; in spi_ll_cpu_rx_fifo_reset()
278 hw->dma_conf.rx_afifo_rst = 0; in spi_ll_cpu_rx_fifo_reset()
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| D | gpspi_flash_ll.h | 54 dev->dma_conf.val = 0; in gpspi_flash_ll_reset()
55 dev->dma_conf.tx_seg_trans_clr_en = 1; in gpspi_flash_ll_reset()
56 dev->dma_conf.rx_seg_trans_clr_en = 1; in gpspi_flash_ll_reset()
57 dev->dma_conf.dma_seg_trans_en = 0; in gpspi_flash_ll_reset()
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| /hal_espressif-latest/components/hal/esp32c3/include/hal/ |
| D | spi_ll.h | 137 hw->dma_conf.val = 0; in spi_ll_master_init()
138 hw->dma_conf.tx_seg_trans_clr_en = 1; in spi_ll_master_init()
139 hw->dma_conf.rx_seg_trans_clr_en = 1; in spi_ll_master_init()
140 hw->dma_conf.dma_seg_trans_en = 0; in spi_ll_master_init()
164 hw->dma_conf.rx_eof_en = 0; in spi_ll_slave_init()
165 hw->dma_conf.dma_seg_trans_en = 0; in spi_ll_slave_init()
264 hw->dma_conf.buf_afifo_rst = 1; in spi_ll_cpu_tx_fifo_reset()
265 hw->dma_conf.buf_afifo_rst = 0; in spi_ll_cpu_tx_fifo_reset()
277 hw->dma_conf.rx_afifo_rst = 1; in spi_ll_cpu_rx_fifo_reset()
278 hw->dma_conf.rx_afifo_rst = 0; in spi_ll_cpu_rx_fifo_reset()
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| D | gpspi_flash_ll.h | 55 dev->dma_conf.val = 0; in gpspi_flash_ll_reset()
56 dev->dma_conf.tx_seg_trans_clr_en = 1; in gpspi_flash_ll_reset()
57 dev->dma_conf.rx_seg_trans_clr_en = 1; in gpspi_flash_ll_reset()
58 dev->dma_conf.dma_seg_trans_en = 0; in gpspi_flash_ll_reset()
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| D | adc_ll.h | 444 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.dma_conf, apb_adc_eof_num, num); in adc_ll_digi_dma_set_eof_num()
452 uint32_t eof_num = HAL_FORCE_READ_U32_REG_FIELD(APB_SARADC.dma_conf, apb_adc_eof_num); in adc_ll_digi_dma_clr_eof()
455 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.dma_conf, apb_adc_eof_num, i); in adc_ll_digi_dma_clr_eof()
464 APB_SARADC.dma_conf.apb_adc_trans = 1; in adc_ll_digi_dma_enable()
472 APB_SARADC.dma_conf.apb_adc_trans = 0; in adc_ll_digi_dma_disable()
480 APB_SARADC.dma_conf.apb_adc_reset_fsm = 1; in adc_ll_digi_reset()
481 APB_SARADC.dma_conf.apb_adc_reset_fsm = 0; in adc_ll_digi_reset()
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| /hal_espressif-latest/components/hal/esp32h2/include/hal/ |
| D | spi_ll.h | 143 hw->dma_conf.val = 0; in spi_ll_master_init()
144 hw->dma_conf.slv_tx_seg_trans_clr_en = 1; in spi_ll_master_init()
145 hw->dma_conf.slv_rx_seg_trans_clr_en = 1; in spi_ll_master_init()
146 hw->dma_conf.dma_slv_seg_trans_en = 0; in spi_ll_master_init()
170 hw->dma_conf.rx_eof_en = 0; in spi_ll_slave_init()
171 hw->dma_conf.dma_slv_seg_trans_en = 0; in spi_ll_slave_init()
270 hw->dma_conf.buf_afifo_rst = 1; in spi_ll_cpu_tx_fifo_reset()
271 hw->dma_conf.buf_afifo_rst = 0; in spi_ll_cpu_tx_fifo_reset()
283 hw->dma_conf.rx_afifo_rst = 1; in spi_ll_cpu_rx_fifo_reset()
284 hw->dma_conf.rx_afifo_rst = 0; in spi_ll_cpu_rx_fifo_reset()
[all …]
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| D | gpspi_flash_ll.h | 55 dev->dma_conf.val = 0; in gpspi_flash_ll_reset()
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| /hal_espressif-latest/components/hal/esp32/include/hal/ |
| D | spi_ll.h | 187 hw->dma_conf.val |= SPI_LL_DMA_FIFO_RST_MASK; in spi_ll_dma_tx_fifo_reset()
188 hw->dma_conf.val &= ~SPI_LL_DMA_FIFO_RST_MASK; in spi_ll_dma_tx_fifo_reset()
200 hw->dma_conf.val |= SPI_LL_DMA_FIFO_RST_MASK; in spi_ll_dma_rx_fifo_reset()
201 hw->dma_conf.val &= ~SPI_LL_DMA_FIFO_RST_MASK; in spi_ll_dma_rx_fifo_reset()
981 dma_in->dma_conf.in_rst = 1; in spi_dma_ll_rx_reset()
982 dma_in->dma_conf.in_rst = 0; in spi_dma_ll_rx_reset()
1019 dma_in->dma_conf.indscr_burst_en = enable; in spi_dma_ll_rx_enable_burst_desc()
1031 dma_out->dma_conf.out_rst = 1; in spi_dma_ll_tx_reset()
1032 dma_out->dma_conf.out_rst = 0; in spi_dma_ll_tx_reset()
1057 dma_out->dma_conf.out_data_burst_en = enable; in spi_dma_ll_tx_enable_burst_data()
[all …]
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| /hal_espressif-latest/components/soc/esp32s2/include/soc/ |
| D | cp_dma_struct.h | 564 volatile cp_dma_conf_reg_t dma_conf; member
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| D | apb_saradc_struct.h | 165 } dma_conf; member
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| /hal_espressif-latest/components/soc/esp32c3/include/soc/ |
| D | spi_struct.h | 185 } dma_conf; member
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| D | apb_saradc_struct.h | 207 } dma_conf; member
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| /hal_espressif-latest/components/soc/esp32c2/include/soc/ |
| D | spi_struct.h | 208 } dma_conf; member
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| /hal_espressif-latest/components/soc/esp32s3/include/soc/ |
| D | spi_struct.h | 216 } dma_conf; member
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| D | apb_saradc_struct.h | 203 } dma_conf; member
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| /hal_espressif-latest/components/soc/esp32c6/include/soc/ |
| D | spi_struct.h | 1376 volatile spi_dma_conf_reg_t dma_conf; member
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| /hal_espressif-latest/components/soc/esp32h2/include/soc/ |
| D | spi_struct.h | 1382 volatile spi_dma_conf_reg_t dma_conf; member
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